Freescale Semiconductor KL02 Series User manual

KL02 Sub-Family Reference Manual
Supports: MKL02Z32CAF4R and KKL02Z32CAF4R
Document Number: KL02P20M48SF0RM
Rev 2.1, July 2013

KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................25
1.1.1 Purpose...........................................................................................................................................................25
1.1.2 Audience........................................................................................................................................................25
1.2 Conventions..................................................................................................................................................................25
1.2.1 Numbering systems........................................................................................................................................25
1.2.2 Typographic notation.....................................................................................................................................26
1.2.3 Special terms..................................................................................................................................................26
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................27
2.2 Kinetis L series.............................................................................................................................................................27
2.3 KL02 sub-family introduction......................................................................................................................................30
2.4 Module functional categories........................................................................................................................................31
2.4.1 ARM Cortex-M0+ core modules...................................................................................................................32
2.4.2 System modules.............................................................................................................................................32
2.4.3 Memories and memory interfaces..................................................................................................................33
2.4.4 Clocks.............................................................................................................................................................33
2.4.5 Security and integrity modules......................................................................................................................33
2.4.6 Analog modules.............................................................................................................................................34
2.4.7 Timer modules...............................................................................................................................................34
2.4.8 Communication interfaces.............................................................................................................................34
2.4.9 Human-machine interfaces............................................................................................................................35
2.5 Orderable part numbers.................................................................................................................................................35
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................37
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Section number Title Page
3.2 Module to module interconnects...................................................................................................................................37
3.2.1 Interconnection overview...............................................................................................................................37
3.2.2 Analog reference options...............................................................................................................................38
3.3 Core modules................................................................................................................................................................39
3.3.1 ARM Cortex-M0+ core configuration...........................................................................................................39
3.3.2 Nested vectored interrupt controller (NVIC) configuration...........................................................................42
3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration..............................................................45
3.4 System modules............................................................................................................................................................46
3.4.1 SIM configuration..........................................................................................................................................46
3.4.2 System mode controller (SMC) configuration...............................................................................................47
3.4.3 PMC configuration.........................................................................................................................................48
3.4.4 MCM configuration.......................................................................................................................................48
3.4.5 Crossbar-light switch configuration...............................................................................................................49
3.4.6 Peripheral bridge configuration.....................................................................................................................51
3.4.7 Computer operating properly (COP) watchdog configuration......................................................................52
3.5 Clock modules..............................................................................................................................................................54
3.5.1 MCG configuration........................................................................................................................................54
3.5.2 OSC configuration.........................................................................................................................................55
3.6 Memories and memory interfaces.................................................................................................................................56
3.6.1 Flash memory configuration..........................................................................................................................56
3.6.2 Flash memory controller configuration..........................................................................................................58
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Section number Title Page
3.6.3 SRAM configuration......................................................................................................................................59
3.7 Analog...........................................................................................................................................................................61
3.7.1 12-bit SAR ADC configuration.....................................................................................................................61
3.7.2 CMP configuration.........................................................................................................................................63
3.8 Timers...........................................................................................................................................................................66
3.8.1 Timer/PWM module configuration................................................................................................................66
3.8.2 Low-power timer configuration.....................................................................................................................68
3.9 Communication interfaces............................................................................................................................................70
3.9.1 SPI configuration...........................................................................................................................................70
3.9.2 I2C configuration...........................................................................................................................................71
3.9.3 UART configuration......................................................................................................................................72
3.10 Human-machine interfaces (HMI)................................................................................................................................73
3.10.1 GPIO configuration........................................................................................................................................73
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................77
4.2 System memory map.....................................................................................................................................................77
4.3 Flash memory map........................................................................................................................................................78
4.3.1 Alternate non-volatile IRC user trim description...........................................................................................78
4.4 SRAM memory map.....................................................................................................................................................79
4.5 Bit Manipulation Engine...............................................................................................................................................79
4.6 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................79
4.6.1 Read-after-write sequence and required serialization of memory operations................................................80
4.6.2 Peripheral bridge (AIPS-Lite) memory map..................................................................................................80
4.6.3 Modules restricted access in user mode.........................................................................................................84
4.7 Private Peripheral Bus (PPB) memory map..................................................................................................................84
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................85
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5.2 Programming model......................................................................................................................................................85
5.3 High-level device clocking diagram.............................................................................................................................85
5.4 Clock definitions...........................................................................................................................................................86
5.4.1 Device clock summary...................................................................................................................................87
5.5 Internal clocking requirements.....................................................................................................................................88
5.5.1 Clock divider values after reset......................................................................................................................89
5.5.2 VLPR mode clocking.....................................................................................................................................89
5.6 Clock gating..................................................................................................................................................................90
5.7 Module clocks...............................................................................................................................................................90
5.7.1 PMC 1-kHz LPO clock..................................................................................................................................91
5.7.2 COP clocking.................................................................................................................................................91
5.7.3 LPTMR clocking............................................................................................................................................92
5.7.4 TPM clocking.................................................................................................................................................92
5.7.5 UART clocking..............................................................................................................................................93
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................95
6.2 Reset..............................................................................................................................................................................95
6.2.1 Power-on reset (POR)....................................................................................................................................95
6.2.2 System reset sources......................................................................................................................................96
6.2.3 MCU resets....................................................................................................................................................99
6.2.4 RESET_b pin ................................................................................................................................................100
6.2.5 Debug resets...................................................................................................................................................100
6.3 Boot...............................................................................................................................................................................101
6.3.1 Boot sources...................................................................................................................................................101
6.3.2 FOPT boot options.........................................................................................................................................101
6.3.3 Boot sequence................................................................................................................................................103
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Section number Title Page
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................105
7.2 Clocking modes............................................................................................................................................................105
7.2.1 Partial Stop.....................................................................................................................................................105
7.2.2 Compute Operation........................................................................................................................................106
7.2.3 Peripheral Doze..............................................................................................................................................107
7.2.4 Clock gating...................................................................................................................................................107
7.3 Power modes.................................................................................................................................................................108
7.4 Entering and exiting power modes...............................................................................................................................109
7.5 Module operation in low-power modes........................................................................................................................110
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................113
8.2 Flash security................................................................................................................................................................113
8.3 Security interactions with other modules......................................................................................................................113
8.3.1 Security interactions with Debug...................................................................................................................114
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................115
9.2 Debug port pin descriptions..........................................................................................................................................115
9.3 SWD status and control registers..................................................................................................................................116
9.3.1 MDM-AP Control Register............................................................................................................................117
9.3.2 MDM-AP Status Register..............................................................................................................................118
9.4 Debug resets..................................................................................................................................................................120
9.5 Micro Trace Buffer (MTB)...........................................................................................................................................120
9.6 Debug in low-power modes..........................................................................................................................................121
9.7 Debug and security.......................................................................................................................................................122
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Section number Title Page
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................123
10.2 Signal multiplexing integration....................................................................................................................................123
10.2.1 Port control and interrupt module features....................................................................................................124
10.2.2 Clock gating...................................................................................................................................................125
10.2.3 Signal multiplexing constraints......................................................................................................................125
10.3 Pinout............................................................................................................................................................................125
10.3.1 KL02 signal multiplexing and pin assignments.............................................................................................125
10.3.2 KL02 pinouts..................................................................................................................................................126
10.4 Module Signal Description Tables................................................................................................................................127
10.4.1 Core modules.................................................................................................................................................127
10.4.2 System modules.............................................................................................................................................127
10.4.3 Clock modules................................................................................................................................................128
10.4.4 Memories and memory interfaces..................................................................................................................128
10.4.5 Analog............................................................................................................................................................128
10.4.6 Timer Modules...............................................................................................................................................129
10.4.7 Communication interfaces.............................................................................................................................129
10.4.8 Human-machine interfaces (HMI).................................................................................................................130
Chapter 11
Port Control and Interrupts (PORT)
11.1 Introduction...................................................................................................................................................................131
11.2 Overview.......................................................................................................................................................................131
11.2.1 Features..........................................................................................................................................................131
11.2.2 Modes of operation........................................................................................................................................132
11.3 External signal description............................................................................................................................................132
11.4 Detailed signal description............................................................................................................................................133
11.5 Memory map and register definition.............................................................................................................................133
11.5.1 Pin Control Register n (PORTx_PCRn).........................................................................................................136
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11.5.2 Global Pin Control Low Register (PORTx_GPCLR)....................................................................................138
11.5.3 Global Pin Control High Register (PORTx_GPCHR)...................................................................................139
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)..............................................................................................139
11.6 Functional description...................................................................................................................................................140
11.6.1 Pin control......................................................................................................................................................140
11.6.2 Global pin control..........................................................................................................................................141
11.6.3 External interrupts..........................................................................................................................................141
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................143
12.1.1 Features..........................................................................................................................................................143
12.2 Memory map and register definition.............................................................................................................................143
12.2.1 System Options Register 2 (SIM_SOPT2)....................................................................................................144
12.2.2 System Options Register 4 (SIM_SOPT4)....................................................................................................145
12.2.3 System Options Register 5 (SIM_SOPT5)....................................................................................................147
12.2.4 System Options Register 7 (SIM_SOPT7)....................................................................................................148
12.2.5 System Device Identification Register (SIM_SDID).....................................................................................149
12.2.6 System Clock Gating Control Register 4 (SIM_SCGC4)..............................................................................151
12.2.7 System Clock Gating Control Register 5 (SIM_SCGC5)..............................................................................153
12.2.8 System Clock Gating Control Register 6 (SIM_SCGC6)..............................................................................154
12.2.9 System Clock Divider Register 1 (SIM_CLKDIV1).....................................................................................155
12.2.10 Flash Configuration Register 1 (SIM_FCFG1).............................................................................................157
12.2.11 Flash Configuration Register 2 (SIM_FCFG2).............................................................................................158
12.2.12 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................159
12.2.13 Unique Identification Register Mid Low (SIM_UIDML).............................................................................159
12.2.14 Unique Identification Register Low (SIM_UIDL)........................................................................................160
12.2.15 COP Control Register (SIM_COPC).............................................................................................................160
12.2.16 Service COP Register (SIM_SRVCOP)........................................................................................................161
12.3 Functional description...................................................................................................................................................162
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Section number Title Page
Chapter 13
System Mode Controller (SMC)
13.1 Introduction...................................................................................................................................................................163
13.2 Modes of operation.......................................................................................................................................................163
13.3 Memory map and register descriptions.........................................................................................................................165
13.3.1 Power Mode Protection register (SMC_PMPROT).......................................................................................165
13.3.2 Power Mode Control register (SMC_PMCTRL)...........................................................................................167
13.3.3 Stop Control Register (SMC_STOPCTRL)...................................................................................................168
13.3.4 Power Mode Status register (SMC_PMSTAT).............................................................................................169
13.4 Functional description...................................................................................................................................................170
13.4.1 Power mode transitions..................................................................................................................................170
13.4.2 Power mode entry/exit sequencing................................................................................................................173
13.4.3 Run modes......................................................................................................................................................175
13.4.4 Wait modes....................................................................................................................................................176
13.4.5 Stop modes.....................................................................................................................................................177
13.4.6 Debug in low power modes...........................................................................................................................179
Chapter 14
Power Management Controller (PMC)
14.1 Introduction...................................................................................................................................................................181
14.2 Features.........................................................................................................................................................................181
14.3 Low-voltage detect (LVD) system................................................................................................................................181
14.3.1 LVD reset operation.......................................................................................................................................182
14.3.2 LVD interrupt operation.................................................................................................................................182
14.3.3 Low-voltage warning (LVW) interrupt operation.........................................................................................182
14.4 I/O retention..................................................................................................................................................................183
14.5 Memory map and register descriptions.........................................................................................................................183
14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)..........................................................184
14.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)..........................................................185
14.5.3 Regulator Status And Control register (PMC_REGSC)................................................................................186
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