Freescale Semiconductor M54455EVB User manual

Freescale Semiconductor
User’s Manual M54455EVBUM
Rev. 4, 01/2008
Contents
© Freescale Semiconductor, Inc., 2008. All rights reserved.
1 Introduction
1.1 Purpose
This document provides design and usage information
for the Freescale M54455EVB evaluation, development
and reference platform.
The M54455EVB platform provides an evaluation
system for the Freescale MCF5445xColdFire®V4m
embedded microprocessor family. The MCF54455 is the
superset device in the family and is the processor
featured on this platform. This allows evaluation and
development for the entire family on a single hardware
platform.
1.2 Related Documents
• MCF54455 Reference Manual
• M54455EVB Quick Start Guide
• M54455EVB Schematics
• MC34702 Switch-Mode with Linear Power
Supply Datasheet
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2.1 MCF54455 Overview. . . . . . . . . . . . . . . . . . . . . . . . 2
2.2 M54455EVB Overview . . . . . . . . . . . . . . . . . . . . . . 4
2.3 Memory Map Overview . . . . . . . . . . . . . . . . . . . . . . 6
2.4 I/O Back Panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . 7
4 Hardware Submodules . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 DDR SDRAM Interface . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Reset Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.3 MCF5445xBoot Options. . . . . . . . . . . . . . . . . . . . . 9
4.4 System Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.5 SPI Flash. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.6 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.7 PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.8 Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.9 BDM and JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.10 USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.11 Ethernet. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.12 ATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.13 FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.14 CPLD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.15 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
4.16 Serial Interface Header . . . . . . . . . . . . . . . . . . . . . 33
4.17 Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.18 Logic Analyzer Connections . . . . . . . . . . . . . . . . . 35
4.19 Power Regulation . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.20 Jumpers, Headers, and Switches . . . . . . . . . . . . . 35
5 U-Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
M54455EVB User’s Manual
by: Microcontroller Solutions Group

M54455EVB User’s Manual, Rev. 4
2Freescale Semiconductor
• Universal Serial Bus Specification, Revision 2.0
• PCI Local Bus Specification, Revision 2.2
• DDR2 SDRAM Specification (JESD79-2C)
2 Overview
2.1 MCF54455 Overview
The MCF54455 is the host processor for the M54455EVB. Figure 1 shows a top-level block diagram of
the MCF54455 superset device. The following is a brief summary of the functional blocks in the
MCF54455 superset device.
• Version 4 ColdFire Core with MMU and EMAC
— Up to 410 Dhrystone 2.1 MIPS @ 266 MHz
• 16 KBytes instruction cache and 16 KBytes data cache
• 32 Kbytes internal SRAM
• Support for booting from SPI-compatible flash, EEPROM, and FRAM devices
• Crossbar switch technology (XBS) for concurrent access to peripherals or RAM from multiple bus
masters
• 16 channel DMA controller
• 16-bit 133MHz DDR/mobile-DDR/DDR2 Controller
• USB 2.0 On-the-Go controller with ULPI support
• 32-bit PCI controller @ 66MHz
• ATA/ATAPI controller
• Two 10/100 Fast Ethernet Controllers (FECn)
• Cryptographic acceleration unit (CAU)
• Random number generator
• Synchronous serial interface
• Four periodic interrupt timers
• Four 32-bit timers with DMA support
• DMA-supported serial peripheral interface (DSPI)
• Three UARTs
•I
2C bus interface

M54455EVB User’s Manual, Rev. 4
Freescale Semiconductor 3
Figure 1. MCF54455 Block Diagram
Version 4 ColdFire Core
LEGEND
2 INTCs
DSPI
EPORT
3 UARTs
I2C
Watchdog
4 DMA
RTC
ATA – Advanced Technology Attachment Controller
BDM – Background debug module
CAU – Cryptography acceleration unit
DSPI – DMA serial peripheral interface
eDMA – Enhanced direct memory access
EMAC – Enhanced multiply-accumulate unit
EPORT – Edge port module
FEC – Fast Ethernet Controller
GPIO – General Purpose Input/Output
I2C– Inter-Integrated Circuit
INTC – Interrupt controller
JTAG – Joint Test Action Group interface
MMU – Memory management unit
PCI – Peripheral Component Interconnect
PIT – Programmable interrupt timers
PLL – Phase locked loop module
RNG – Random Number Generator
RTC – Real time clock
SSI – Synchronous Serial Interface
USB OTG – Universal Serial Bus On-the-Go controller
MCF54455
EMAC 2 FECs
Crossbar Switch (XBS)
32K
SRAM
Peripheral Bridge
CAU
16K
Instruction
Cache
16K
Data
Cache
Timers
BDM
ATA SDRAM
Controller FlexBus
eDMA
USB OTG
4 PITs
SSI RNG GPIO
MMU
Hardware
Divide
Oscillator PLLJTAG
PCI Serial Boot

M54455EVB User’s Manual, Rev. 4
4Freescale Semiconductor
2.2 M54455EVB Overview
The M54455EVB provides hardware to evaluate as many of the configurations of the MCF5445xfamily
as possible. The M54455EVB features:
• Freescale MCF54455 ColdFire microprocessor
• DDR2 SDRAM (256 MByte)
• Two NOR flash memory devices (16 MByte, 512 KByte)
• Serial flash
• MRAM (512 KByte, accessible through FPGA Flexbus interface)
• Four PCI slots (32-bit, for MCF5445xas a PCI host system)
• Two-port Ethernet interface
• 40-pin ATA connector
• Audio interface (I2S mode of SSI module connected to audio codec)
• Multiple USB interface options
— FS/LS Host via on-chip transceiver with host support (Type A receptacle)
— HS/FS/LS dual-role via external ULPI PHY (Mini-AB receptacle)
• Two RS232 serial ports (RS232 transceivers on UART0 & UART1)
• One USB serial port (UART0 serial converted to USB converted on UART0)
• Built-in P&E Micro USB Multilink debug interface
• Standard 26-pin BDM header
• Serial interface header for access to timers, interrupts, DSPI, I2C, and more
• Clock generation logic adjustable via I2C
• LEDs and 7-segment display programmable via CPLD and FPGA
• Low-profile, micro-ATX computer case with built-in power supply
Figure 2. M54455EVB Kit

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Freescale Semiconductor 5
Figure 3. M54455EVB Block Diagram
ColdFire
MCF5445x
SDRAM Bus
DDR2 Term Reg
0.9V VTT 0.9V VREF
MC34702
1.5V3.3V 1.8V
ATX Power Supply
Barrel Pwr
Connector
5V
MC34702
1.2V
3.3V 1.8V
CPLD
512K Flash
8-bit data bus
Flash0
16MB Flash
8-bit data bus
Flash1
FPGA
MRAM
Buffered Flexbus
PCI Slot 0
3.3V PCI Bus
PCI Slot 1 PCI Slot 2 PCI Slot 3
PCI Clock Buffer Programmable Clock
Generator
EXTAL
PCI Arbi Cntrl and
Interrupts
Interfaces for RS232,
RS232-to-USB, DSPI, I2C,
Timers, etc.
SSI Audio
Interface USB Full-
speed
Interface
USB ULPI
Interface
ULPI
Dual FEC PHY (RMII
mode) and 2xRJ45 w/
integrated magnetics and
LEDs
FEC0RMII
FEC1 RMII / ATA_DATA[8:15]
ATA
ATA_DATA[15:8]
ATA_DATA[7:0], Control
Serial I/O,
Interrupts,
Timers, etc.
DDR2 Parallel Termination
VTTVREF
DDR2
4 x 512Kbit (64M8)
Serial Flash
Reset
Configuration
Latch
BDM & JTAG 26-pin Connector
Boot Mode
Selection
Compression Logic
Analyzer Connectors
surrounding processor for
access to all switching
signals
PCI Arbitration and Interrupts
PCI Arbitration and Interrupts
Chip Selects
CPLD Switchable Options
Clocks for FPGA, Eth PHY, USB
ATA Buffer
ATA_DATA[15:8]
FlexBus

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6Freescale Semiconductor
2.3 Memory Map Overview
Figure 1 illustrates the overall memory map for the MCF54455 and M54455EVB.
Much of the memory map is dictated by the MCF5445xmemory map. Refer to the “Overview” and
“Crossbar Switch” sections of the MCF54455 Reference Manual for more details.
Table 1. M54455EVB Memory Map
Function Start Address End Address Size
Flexbus—Flash1 0x0000_0000 0x00FF_FFFF 16 MB
Flexbus—Flash0 0x0400_0000 0x0407_FFFF 512 KB
Flexbus—CPLD1
1The CPLD and FPGA sections contain details on the memory-mapped registers within
these address spaces.
0x0800_0000 0x08FF_FFFF 16 MB
Flexbus—FPGA/MRAM10x0900_0000 0x09FF_FFFF 16 MB
DDR2 SDRAM 0x4000_0000 0x4FFF_FFFF 256 MB
MCF5445xInternal SRAM 0x8000_0000 0x8000_7FFF 32 KB
ATA 0x9000_0000 0x9FFF_FFFF 256 MB
PCI 0xA000_0000 0xBFFF_FFFF 512 MB
Flexbus—Unused 0xC000_0000 0xDFFF_FFFF 512 MB
Reserved 0xE000_0000 0xEFFF_FFFF 256 MB
Internal Peripheral Space 0xF000_0000 0xFFFF_FFFF 256 MB

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2.4 I/O Back Panel
Refer to Figure 4 for the I/O back panel descriptions.
Figure 4. M54455EVB I/O Back Panel Port Locations
3 Installation and Configuration
The M54455EVB comes pre-programmed with U-Boot and Linux pre-configured to run a demo
application. This section describes how to setup the evaluation board to access the bootloader to start
Linux.
The default communication interface with the M54455EVB is a simple serial port console. A terminal
emulator on a host PC and the supplied serial cable is required to interact with the serial port. Alternately,
a USB cable can be used if the USB serial port is configured for use (refer to Section 4.17, “Serial Ports”
for details).
The basic installation steps are as follows:
1. Plug in the case’s power supply with the power cable provided.
2. Connect one end of the provided serial cable to the DB9 serial port connector labelled UART0
(Refer to Figure 4).
3. Connect the other end of the serial cable to a free DB9 serial port connector on a host PC.
4. Open the terminal emulator of your choice (e.g. HyperTerminal, Tera Term, minicom, etc.).
USB Serial Port
FS/LS USB Host
HS/FS/LS USB Dual-role
Serial Ports:
Top = UART0
Bottom = UART1
Audio Interface:
Blue = Line-in
Green = Line-out
Pink = Mic
Ethernetl Ports:
Top = FEC1
Bottom = FEC0
USB BDM interface

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8Freescale Semiconductor
5. Configure the COM port as follows:
6. Press the power switch on the front of the computer case and the U-Boot banner (example below)
should appear in the terminal window.
U-Boot 1.2.0-g4a442d31-dirty (Aug 23 2007 - 11:14:19)
CPU: Freescale MCF54455 (Mask:48 Version:1)
CPU CLK 266 Mhz BUS CLK 133 Mhz FLB CLK 33 Mhz
INP CLK 33 Mhz VCO CLK 533 Mhz
Board: Freescale M54455 EVB
I2C: ready
DRAM: 256 MB
FLASH: 16.5 MB
In: serial
Out: serial
Err: serial
Net: FEC0, FEC1
IDE: Bus 0: not available Status = 0x60
->
Linux and a root file system are preprogrammed into the second Flash device (Flash1) at address
0x0000_0000. A demo application automatically runs when Linux is started. A network
connection is required for the web server portion of the demo to work.
7. Plug one end of the provided Ethernet cable into a network or host PC with a DHCP server running.
Plug the other end of the cable into the FEC0 interface (bottom RJ45 receptacle) of the
M54455EVB.
8. To boot Linux, issue the following U-Boot command.
-> bootm 0
9. The demo application prints out a banner message including the IP address that it obtained from
the DHCP server. Launch a web client (e.g. Firefox or Internet Explorer) and copy this IP address
into the web browser. The M54455EVB serves up a web page with more information on the
available demos.
4 Hardware Submodules
The following sections describe the hardware submodules of the M54455EVB.
Table 2. Default Serial Console Settings
Parameter Setting
Baud Rate 115,200 bps
Data bits 8
Parity None
Stop bits 1
Flow Control None or Software (Xon/Xoff)

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Freescale Semiconductor 9
4.1 DDR SDRAM Interface
The MCF5445xDDR SDRAM controller has the following features:
• Supports a glueless interface to DDR, DDR2, and mobile/low-power DDR SDRAM devices
• Support for 16-bit fixed memory port width
• 16-byte critical word first burst transfer
• Up to 14 lines of row address, up to 11 column address lines, 2 bits of bank address, and two chip
selects.
• Supports up to 512 MByte of memory; minimum memory configuration of 8 MByte
• Supports page mode to maximize the data rate
• Supports sleep mode and self-refresh mode
The M54455EVB features 256 MBytes of DDR2 SDRAM. Four 8-bit wide Micron MT47H64M8
(512 Mbit) devices are arranged as two 16 M ×8 ×4 banks per SDRAM controller chip select. This results
in two 16-bit wide, 128 MBytes blocks of DDR2 memory
The SDRAM interface is terminated with parallel termination resistors. The MCF5445xdoes not provide
control for the DDR2 on-die termination. The ODT pins on the DDR2 devices are connected to control
signals from the CPLD for test purposes only. These signals are disabled in the normal functional mode.
4.2 Reset Controller
The reset controller on the M54455EVB is implemented in a Xilinx XC95144XL CPLD. The CPLD
controlsthestate of the system reset signal(SYSRESET)gathers reset information from a pushbutton reset
(SW2), the BDM interface, and the FPGA (FPGA_DONE). At system power-on, the CPLD holds
SYSRESET asserted until the FPGA has loaded its image from the platform flash PROM and asserted the
FPGA_DONE signal. After system power-on, the CPLD asserts SYSRESET when it detects the assertion
of any of the reset sources.
4.3 MCF5445xBoot Options
During a system reset, the CPLD also drives the boot mode configuration signals into the MCF5445x. The
MCF5445xhas three boot mode options:
• Boot with default configuration constants specified in the RCON register,
• Boot with configuration data specified by the Flexbus FB_AD[7:0] pins, and
• Boot with configuration data obtained from an external SPI memory through the serial boot
facility.
In all of these cases, the boot code is fetched from an external memory connected to the Flexbus on
FB_CS0 with the possible exception of the serial boot mode. In serial boot mode, if the boot load length
field (BLL) in the reset configuration data stored in the SPI memory is non-zero, then boot code is loaded
from the SPI memory instead of from Flexbus.
The MCF5445xboot mode is determined by the state of the BOOTMOD[1:0] input pins during the rising
edge of RSTOUT (MCF5445xreset output signal). The CPLD drives BOOTMOD[1:0] to the values that

M54455EVB User’s Manual, Rev. 4
10 Freescale Semiconductor
are set on the CPLD mode signals (CPLD_MODE[1:0]). The CPLD_MODE signals are set by the CPLD
configuration switch, SW1. See Section 4.14, “CPLD” for more details. Table 3 shows the SW1 settings
and their corresponding boot mode configurations.
4.3.1 Default Configuration (SW1[2:1] = ON:ON)
If the BOOTMOD pins are 00 during reset, the MCF5445xRCON register determines the chip
configuration after reset, regardless of the states of the external data pins. The RCON register specifies the
following default configuration for the MCF54455:
• PCI enabled, muxed Flexbus address/data, 8-bit port-size boot
• PLL enabled
• PCI host mode
• 66MHz PCI slew rate mode
• PLL multiplier: fVCO = 6 ×fREF
4.3.2 Parallel Configuration (SW1[2:1] = OFF:ON)
If the BOOTMOD pins are 10 during reset, the MCF5445xconfiguration after reset is determined
according to the levels driven onto the FB_AD[7:0] pins. On the M54455EVB, the FB_AD[7:0] pins are
actively driven by an 8-bit buffer enabled when the MCF5445xRSTOUT signal is asserted. The values
driven by the buffer are set by the SW3 DIP switch settings. Refer to Table 4 for the configuration setting
information.
Table 3. M54455EVB Boot Mode Selection
BOOTMOD[1:0] SW1[2:1] Meaning
00 ON:ON Boot from Flexbus with defaults (from RCON register)
01 ON:OFF Reserved
10 OFF:ON Boot from Flexbus and override defaults via data bus (FB_AD[7:0])
11 OFF:OFF Boot from Flexbus and override defaults via serial boot facility (SPI memory)

M54455EVB User’s Manual, Rev. 4
Freescale Semiconductor 11
Table 4. MCF54455 Parallel Configuration During Reset
Pin(s) Affected Corresponding SW3
Settings Function
FB_AD[31:0], PCI_*
SW3[8] SW3[7] SW3[6] Flexbus, PCI, Port Size Mode
ON ON ON PCI, muxed FB addr/data, 8-bit boot1
ON ON OFF No PCI, muxed FB addr/data, 16-bit boot
ON OFF ON No PCI, muxed FB addr/data, 8-bit boot
ON OFF OFF No PCI, muxed FB addr/data, 32-bit boot
OFF ON ON PCI, muxed FB addr/data, 16-bit boot
OFF ON OFF No PCI, non-muxed FB addr/data, 16-bit boot
OFF OFF ON No PCI, non-muxed FB addr/data, 8-bit boot
OFF OFF OFF No PCI, non-muxed FB addr/data, 32-bit boot
Output Clocks
SW3[5] PLL Mode
ON Limp mode
OFF PLL mode
(none)
SW3[4] PCI Host/Agent Mode (when in a PCI mode)
ON PCI host mode
OFF PCI agent mode
(none)
SW3[4] Oscillator Mode (when in a No PCI mode)
ON Oscillator bypass mode
OFF Crystal oscillator mode
PCI_*
SW3[3] PCI Slew Rate Mode (when in a PCI mode)
ON 66 MHz slew rate mode
OFF 33 MHz slew rate mode
(none)
SW3[3] SW3[2] SW3[1] PLL Multiplier (when in a No PCI mode)
ON ON ON fVCO = 8 x fREF
ON ON OFF fVCO = 16 x fREF
ON OFF ON fVCO = 6 x fREF
ON OFF OFF fVCO = 12 x fREF
OFF ON ON fVCO = 18 x fREF
OFF ON OFF fVCO = 24 x fREF
OFF OFF ON fVCO = 10 x fREF
OFF OFF OFF fVCO = 20 x fREF

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12 Freescale Semiconductor
4.3.3 Serial Configuration (SW1[2:1] = OFF:OFF)
If the BOOTMOD pins are 11 during reset, then the chip configuration after reset is determined by data
obtained from an external SPI memory through serial boot using the SBF_DI, SBF_DO, SBF_CS, and
SBF_CK signals. The internal configuration signals are driven to reflect the data being received from the
external SPI memory to allow for module configuration. See “Serial Boot Facility” and “Chip
Configuration Module” chapters of the MCF54455 Reference Manual for more details.
4.4 System Clocks
A single Cypress CY22393 device generates all of the clock signals on the M54455EVB. Alternatively,
you can supply the clock signals using external SMA connectors for test purposes. The different clock
signals and configurations are described below. Please refer to the MCF54455 Reference Manual for
further information on the clocking requirements for the MCF5445xfamily.
The CY22393 is programmed prior to assembly on the M54455EVB PCB. There is an I2C interface on
this device that allows it to be reprogrammed. However, these settings are not retained following a
power-on reset.
The state of the CY22393’s S2 frequency control input pin is controlled by a jumper (H4[3:4]) and the
system FPGA signal, CLK_GEN_S2. The FPGA uses two conditions to determine how to drive the
CLK_GEN_S2 signal: the M66EN signal and a programmable bit in the PCICLKCFG register. The
M66EN signal is a PCI bus signal that is tied to logic 0 if a 33MHz PCI card is installed in any one of the
four PCI slots. By default, the PCICLKCFG[CLKGENS2EN] bit is cleared, which forces the clocks to
33 MHz. Table 5 summarizes the three controls over the state of the S2 pin.
(none)
SW3[2] SW3[1] PLL Multiplier (when in a PCI mode)
ON ON fVCO = 8 x fREF
e.g. CPU = 266 MHz; PCI = 66 MHz
ON OFF fVCO = 16 x fREF
e.g. CPU = 266 MHz; PCI = 33 MHz
OFF ON fVCO = 6 x fREF
e.g. CPU = 200 MHz; PCI = 66 MHz
OFF OFF fVCO = 12 x fREF
e.g. CPU = 200 MHz; PCI = 33 MHz
1This setting is required if booting from Flash device, Flash0, or Flash1.
Table 4. MCF54455 Parallel Configuration During Reset (continued)
Pin(s) Affected Corresponding SW3
Settings Function

M54455EVB User’s Manual, Rev. 4
Freescale Semiconductor 13
The following pseudocode illustrates the input clock determination logic:
if ((H4[3:4] shunt is not installed) and
(no 33MHz PCI cards installed (M66EN logic 1)) and
(FPGA_PCICLKCFG[CLKGENS2EN] is set))
{S2 = 1; PCI Clocks and MCF5445x input clock are 66MHz
}
else
{S2 = 0; PCI Clocks and MCF5445x input clock are 33MHz
}
Refer to Section 4.13, “FPGA” for details on the FPGA_PCICLKCFG register. Table 6 shows the default
system clock frequencies generated by the CY22393.
There is a provision on the M54455EVB for clocking the MCF5445xwith a 25MHz crystal instead of the
33/66MHz external clock. A cut-trace (CT11) can be modified to route the provided 25MHz crystal
oscillator circuit to the EXTAL input. Refer to Figure 5 for details on how to make this modification.
Table 5. PCI Clocks and MCF5445xInput Clock Speed Selection
M66EN signal FPGA_PCICLKCFG
[CLKGENS2EN] H4[3:4] Jumper Resulting S2 Value CPU input and PCI Bus Speed
0 — — 0 33 MHz
—01
1Indicates the default values.
—0133 MHz1
— — Jumper Shunt ON 0 33 MHz
111Jumper Shunt OFF11 66 MHz
Table 6. Clock Generator Outputs
Clock CY22393
Output S2 Value Default Clock Frequency (MHz) Description
MCF5445xInput Clock CLKA 0 33 Clock driven into the EXTAL pin on the MCF5445x. This is the operating frequency in limp mode and the
PLL reference when the PLL is enabled.
166
PCI Clock CLKB 0 33 Duplicate of the MCF5445xinput clock. This is driven to clock buffers and on to each PCI slot, the FPGA,
and the CPLD.
166
MCF5445xUSB Clock CLKC N/A Disabled1
1CLKC is disabled by default. Instead, USBCLKIN is driven by the 60MHz clock output of the ULPI PHY. However, JP918
provides an option to select CLKC as the source for USBCLKIN. If this is selected, the CY22393 must be programmed via
I2C to generate a 60MHz clock signal.
MCF5445xUSB clock1
ULPI PHY Clock CLKD N/A 24 Reference clock for the external ULPI PHY
RMII Ethernet Clocks CLKE N/A 50 Duplicate, matched clocks driven to each MCF5445x FECRMIIclockinputandtotheexternaldualEthernet
PHY

M54455EVB User’s Manual, Rev. 4
14 Freescale Semiconductor
Figure 5. MCF5445xInput Clock Selection Cut-Trace
4.5 SPI Flash
A 16 Mbit SPI flash is connected to the MCF5445xvia the DSPI interface. This same SPI flash can be
used to store reset configuration parameters and boot code when using the serial boot facility. Refer to
Section 4.3, “MCF5445x Boot Options” for more information on how to configure the M54455EVB for
serial boot.
4.6 Flash
The M54455EVB features two flash devices connected to the FlexBus expansion bus. The smaller of the
two flashes is a 512KByte, 8-bit wide AT49BV040 (or compatible) device referred to as Flash0. This
device contains the U-Boot bootloader. The larger of the two flashes is a 16 MByte, 8-bit wide 28F128J3D
(or compatible) device referred to as Flash1. By default, this flash device is programmed with a Linux
image, but it can be reprogrammed and used as a boot device if desired.
The selection of a boot flash device is achieved with a CPLD mode switch setting, specifically
CPLD_MODE2 which is controllable by DIP switch SW1[3]. The device that is connected to the global
chip-select from the MCF5445x(FB_CS0) is the boot device. The other device is connected to FB_CS1.
Table 7 shows the boot device selection settings.
Table 7. Flash Chip Select Configuration
SW1[3] Meaning Application
OFF Flash1 is the boot device FLASH1_CS = FB_CS0
FLASH0_CS = FB_CS1 Boot custom image
ON Flash0 is the boot device FLASH1_CS = FB_CS1
FLASH0_CS = FB_CS0 Boot U-Boot
cut trace solder

M54455EVB User’s Manual, Rev. 4
Freescale Semiconductor 15
4.7 PCI
The MCF5445xprocessor's PCI controller module has the following features:
• Compatible with PCI 2.2 specification
• Supports up to four external PCI masters
• 32-bit target and initiator operation
• 33–66 MHz operation with PCI bus to internal bus divider ratios of 1:1, 1:2, 1:3, 2:3, 1:4, and 1:5.
• Support for host and agent configurations.
The M54455EVB is designed to feature the MCF5445xas a PCI host. It provides four, 32-bit, 3.3V PCI
slots. The IDSEL pins on each of the slots and the MCF5445xis connected to a different PCI_AD signal.
Table 8 shows the IDSEL connections.
4.7.1 PCI Clocking
The MCF5445xdoes not output a PCI clock. The PCI controller of the MCF5445xis timed to the input
reference clock on EXTAL. Therefore, the input reference clock to the MCF5445xis matched to each of
the PCI slots on the M54455EVB to maintain clock phase alignment and ensure proper PCI timings.
The M54455EVB is designed to support 33- and 66-MHz 32-bit PCI cards. However, the speed of the PCI
clocks and input clock is limited to that of the slowest device by logic on the M54455EVB. The frequency
of these clocks is controlled by an input (S2) into the clock generator logic. The FPGA automatically
adjuststhiscontrolsignalbasedontheM66ENsignal fromeach PCI slot. The S2 signalisalso controllable
by a jumper and a memory mapped register in the FPGA. See Section 4.4, “System Clocks” and
Section 4.13, “FPGA” for more information. Table 5 provides a summary of the PCI bus speed controls.
4.7.2 PCI Power
The PCI is only available if an ATX supply is used to power the board. If the optional barrel power
connector is used, then the ATX3V3 supply is not available. This also affects the clocking of the
MCF5445x. The M66EN signal is pulled-up to the ATX3V3 supply. Without this supply, the M66EN
signal is detected as a logic 0 and the CPU input reference frequency is forced to 33MHz.
Table 8. PCI IDSEL Assignments
PCI Slot IDSEL Assignment
Slot 0 PCI_AD17
Slot 1 PCI_AD18
Slot 2 PCI_AD19
Slot 3 PCI_AD20
MCF5445xPCI_AD16

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4.7.3 PCI Arbitration
By default, the EVB uses the MCF5445xon-chip PCI arbiter, and the request/grant signals from the PCI
slots are routed directly to the MCF5445x. The board does provide cut-trace options to allow you to route
these PCI arbitration signals to the FPGA. It would then be left to you to implement an external arbitration
scheme in the FPGA.
The following figures describe how to alter the M54455EVB to route the PCI arbitration signals to the
FPGA. Reference designators for the cut-trace board footprints are CT1-CT10. CT1-CT2, CT5-CT7 and
CT9 can be found near the PCI slots (J14, J15, J16, J17), and CT8, CT10, CT3 and CT4 can be found near
the MCF5445x(U1).
Figure 6. PCI Request 0 Cut Trace Option—Use FPGA for Arbitration

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Figure 7. PCI Request 1 and Request 2 Cut Trace Option—Use FPGA for Arbitration
Figure 8. PCI Request 3 Cut Trace Option—Use FPGA for Arbitration

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Figure 9. PCI Grant 0 Cut Trace Option—Use FPGA for Arbitration
Figure 10. PCI Grant 1 Cut Trace Option—Use FPGA for Arbitration

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Figure 11. PCI Grant 2 and Grant 3 Cut Trace Option—Use FPGA for Arbitration
4.7.4 PCI Interrupts
The four interrupt signals on each PCI slot (INTA–INTD) are wire ORed together to form one interrupt
source per slot. These four interrupt sources are routed to the system FPGA. The FPGA routes these
interrupts to the MCF5445xas programmed by you. Please refer to Section 4.13.1, “FPGA Registers” for
details on how to program the FPGA’s interrupt controller.
4.8 Audio
A stereo audio codec is connected to the MCF5445x’s SSI interface. The SSI operates in I2S mode to
transfer audio data to and from a TLV320AIC23B device. The codec’s control communications SPI
channel is accessed through the MCF5445x’s DSPI interface using DSPI_PCS5. The line-in, line-out, and
microphone inputs of the codec are brought to a 3.5-mm triple audio connector with PC-99 standard color
coding. Refer to Section 2.4, “I/O Back Panel” for location and connection information.
For accessibility ease, all the SSI signals from the MCF5445xare brought to a header, J910.
Table 9. SSI Signals on J910
Signal Name Pin Pin Signal Name
SSI_RXD 12 SSI_TXD
SSI_MCLK 34 SSI_BCLK
SSI_FS 56 GND

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4.9 BDM and JTAG
The primary debug port on the MCF5445xis referred to as the background debug module or BDM. The
standard 26-pin BDM header (J24) is provided on the M54455EVB for attachment of an external BDM
control interface. However, the M54455EVB also features a built-in P&E USB ColdFire Multilink. This
interface is brought out to the I/O back panel to a standard Type-B USB receptacle. Refer to Section 2.4,
“I/O Back Panel” for the location of the connector. This allows for run-control debugging with a standard
USB cable (provided in the M54455EVB kit).
The MCF5445xalso features IEEE 1149.1 Test Access Port (JTAG) test logic that can be used for
boundary-scan testability. The access pins for JTAG are multiplexed over the BDM control signals and are
available on J24.
The JTAG_EN input signal to the MCF5445xdetermines the debug mode: BDM or JTAG. This signal is
controllable by JP903 as shown below.
The TCLK and PSTCLK signals are the only two multiplexed signals that switch input/output state
dependingonwhichdebugmodeisselected. In BDMmode, the PSTCLK isanoutputfrom the MCF5445x
to the external BDM control interface. In JTAG mode, TCLK is the test clock input. The standard 26-pin
BDM header defines pin 24 as PSTCLK. A common practice is to place TCLK on pin 6 of this header.
JP904 is available to control the routing of the multiplexed TCLK_PSTCLK signal to the 26-pin debug
header (J24) as shown below.
Table 10. Debug Mode Selection
JP903 Setting Debug Mode
Shunt on 1-2 JTAG
Shunt on 2-3 BDM
Table 11. TCLK/PSTCLK Routing Control
JP904 Setting TCLK_PSTCLK Routing
Shunt on 1-2 TCLK/PSTCLK on J24[24]1
1This setting is required if an external BDM control interface is
used. If the on-board USB Multilink is used, this jumper setting
is ignored.
Shunt on 2-3 TCLK/PSTCLK on J24[6]2
2This pin was previously specified by Freescale as Developer
Reserved. External BDM control cables may be able to make
use of this pin for JTAG instructions. There is a 10-kΩ
pull-down resistor on the TCK_PSTCLK signal when this
setting is selected.