Freescale Semiconductor MCF5206eLITE User manual

MCF5206eLITE
Evaluation Board
User’s Manual
Rev. 2
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DISCLAIMER
The information in this manual has been carefully examined and is believed to be entirely reliable. However, no
responsibility is assumed for inaccuracies. Furthermore, Motorola reserves the right to make changes to any
product(s) herein to improve reliability, function, or design. The M5206eLITE board is not intended for use in
life and/or property critical applications. Here, such applications are defined to be any situation in which any
failure, malfunction, or unintended operation of the board could, directly, or indirectly, threaten life, result in
personal injury, or cause damage to property. Although every effort has been made to make the supplied software
and its documentation as accurate and functional as possible, Motorola Inc. will not assume responsibility for any
damagesincurredorgeneratedbythisproduct. Motoroladoesnotassumeanyliabilityarisingoutoftheapplication
or use of any product or circuit described herein, neither does it convey any license under its patent rights, if any,
or the rights of others.
WARNING
THIS BOARD GENERATES, USES, AND CAN RADIATE RADIO
FREQUENCY ENERGY AND, IF NOT INSTALLED PROPERLY,
MAYCAUSE INTERFERENCETORADIO COMMUNICATIONS.
AS TEMPORARILY PERMITTED BY REGULATION, IT HAS
NOT BEEN TESTED FOR COMPLIANCE WITH THE LIMITS
FORCLASSACOMPUTINGDEVICES PURSUANTTOSUBPART
J OF PART 15 OF FCC RULES, WHICH ARE DESIGNED TO
PROVIDE REASONABLE PROTECTION AGAINST SUCH
INTERFERENCE. OPERATION OF THIS PRODUCT IN A
RESIDENTIAL AREA IS LIKELY TO CAUSE INTERFERENCE,
INWHICHCASE THEUSER,ATHIS/HEROWNEXPENSE, WILL
BE REQUIRED TO CORRECT THE INTERFERENCE.
Motorola is a registered trademark of Motorola Inc.
IBM PC and IBM AT are registered trademarks of IBM Corp.
All other trademark names mentioned in this manual are the registered trademark of their respective owners.
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TABLE OF CONTENTS
CHAPTER 1 1-1
1.1 INTRODUCTION .................................................................................................................................. 7
1.2 GENERAL HARDWARE DESCRIPTION ...........................................................................................7
1.3 SYSTEM MEMORY ..............................................................................................................................8
1.4 SERIAL COMMUNICATION CHANNELS ......................................................................................... 8
1.5 PARALLEL I/O PORTS ......................................................................................................................... 8
1.6 PROGRAMMABLE TIMER/COUNTER ............................................................................................. 8
1.7 SYSTEM CONFIGURATION ............................................................................................................... 8
1.8 INSTALLATION AND SETUP .............................................................................................................9
1.8.1. Unpacking..........................................................................................................................................9
1.8.2. Preparing the Board for Use .............................................................................................................9
1.8.3. Providing Power to the Board ...........................................................................................................9
1.8.4. Selecting Terminal Baud Rate ......................................................................................................... 10
1.8.5. The Terminal Character Format ..................................................................................................... 10
1.8.6. Connecting the Terminal.................................................................................................................. 10
1.8.7. Using a Personal Computer as a Terminal ..................................................................................... 10
1.9 SYSTEM POWER-UP AND INITIAL OPERATION ......................................................................... 12
1.10 M5206eLITE JUMPER SETUP .................................................................................................................. 12
1.10.1. Jumper JP2 - This jumper selects between -CS0 to Flash or off-board connector J1 .................... 12
1.10.2. Jumper JP1 – DRAM SIMM voltage selection – 5V or 3.3V...........................................................12
1.10.3. Jumper JP3 - This jumper selects between BDM & JTAG operation of the MCF5206e ................ 13
1.10.4. Jumper JP4 - This jumper selects between 3.3V or 5V supply to the BDM cable........................... 13
1.10.5. Jumper JP5 - This jumper allows current measurements of the MCF5206e to be taken ................ 13
1.11 USING THE BDM................................................................................................................................13
CHAPTER 2 2-1
2.1 WHAT IS dBUG? ................................................................................................................................. 14
2.2 OPERATIONAL PROCEDURE .......................................................................................................... 15
2.2.1. System Power-up ............................................................................................................................. 15
2.2.2. System Initialization ........................................................................................................................ 16
2.2.2.1. Hard RESET Button. .................................................................................................................................. 16
2.2.2.2. Software Reset Command. ......................................................................................................................... 16
2.2.2.3. USER Program. .......................................................................................................................................... 16
2.2.3. System Operation............................................................................................................................. 17
2.3 TERMINAL CONTROL CHARACTERS........................................................................................... 17
2.4 dBUG COMMAND SET...................................................................................................................... 18
2.4.1. AS - Assemble AS ...................................................................................................................... 18
2.4.2. BC - Compare Blocks of Memory BC....................................................................................... 20
2.4.3. BF - Block of Memory Fill BF.................................................................................................. 20
2.4.4. BM - Block Move BM ............................................................................................................... 21
2.4.5. BR - Breakpoint BR .................................................................................................................. 22
2.4.6. BS - Block Search BS ................................................................................................................ 23
2.4.7. DATA - Data Conversion DATA............................................................................................... 24
2.4.8. DI - Disassemble DI ................................................................................................................. 24
2.4.9. DL - Download Serial DL ........................................................................................................ 25
2.4.10. Go - Execute GO ...................................................................................................................... 25
2.4.11. GT - Execute Until a Temporary Breakpoint GT...................................................................... 26
2.4.12. HELP - Help HE ....................................................................................................................... 26
2.4.13. IRD - Internal Registers Display IRD ...................................................................................... 26
2.4.14. IRM - Internal Registers MODIFY IRM .................................................................................. 27
2.4.15. MD - Memory Display MD ...................................................................................................... 27
2.4.16. MM - Memory Modify MM .................................................................................................... 28
2.4.17. RD - Register Display RD ........................................................................................................ 28
2.4.18. RM - Register Modify RM ........................................................................................................ 29
2.4.19. RESET - Reset the board and dBUG RESET ........................................................................... 29
2.4.20. SET - Set Configuration SET.................................................................................................... 30
2.4.21. SHOW - Show Configuration SHOW.......................................................................................30
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2.4.22. STEP - Step Over ST ................................................................................................................ 31
2.4.23. SYMBOL - Symbol Name Management SYMBOL .................................................................. 31
2.4.24. TRACE - Trace Into TR ............................................................................................................ 32
2.4.25. UPDBUG - Update the dBUG Image UPDBUG ..................................................................... 32
2.4.26. UPUSER - Update User Code In Flash UPUSER ................................................................... 33
2.5 TRAP #15 FUNCTIONS ............................................................................................................................ 34
2.5.1. OUT_CHAR..................................................................................................................................... 34
2.5.2. IN_CHAR......................................................................................................................................... 35
2.5.3. CHAR_PRESENT ............................................................................................................................ 36
2.5.4. EXIT_TO_dBUG ............................................................................................................................. 36
CHAPTER 3 3-1
3.1 THE PROCESSOR AND SUPPORT LOGIC...................................................................................... 37
3.1.1. The Processor .................................................................................................................................. 37
3.1.2. The Reset Logic ............................................................................................................................... 37
3.1.3. The -HIZ Signal ...............................................................................................................................37
3.1.4. The Clock Circuitry .........................................................................................................................38
3.1.5. Watchdog Timer (BUS MONITOR) ................................................................................................. 38
3.1.6. Interrupt Sources ............................................................................................................................. 38
3.1.7. Internal SRAM ................................................................................................................................. 38
3.1.8. The MCF5206e Registers and Memory Map .................................................................................. 38
3.1.9. Reset Vector Mapping ...................................................................................................................... 39
3.1.10 -TA Generation ................................................................................................................................ 39
3.1.11 Wait State Generator .......................................................................................................................40
3.2 THE ASYNCHRONOUS DRAM SIMM ............................................................................................ 40
3.3 FLASH ROM ........................................................................................................................................ 40
3.3.1. JP2 Jumper and User’s Program .................................................................................................... 40
3.4 THE SERIAL COMMUNICATION CHANNELS ..............................................................................40
3.4.1. The MCF5206e UARTs.................................................................................................................... 40
3.4.2. Motorola Bus (M-Bus) Module........................................................................................................ 41
3.5 THE PARALLEL I/O PORT................................................................................................................. 41
3.6 THE CONNECTORS AND THE EXPANSION BUS......................................................................... 41
3.6.1. The Terminal Connector J9 ............................................................................................................. 41
3.6.2. The Auxiliary Serial Communication Connector P2 .......................................................................41
3.6.3. The M-Bus/I2C Connector J5........................................................................................................... 42
3.6.4. Processor Expansion Bus J1 & J2................................................................................................... 42
3.6.5. The Debug Connector J3 ................................................................................................................. 45
3.6.6. The 5V Tolerant GPIO Connector J10 ............................................................................................ 46
3.6.7 The GPIO Open Collector Driver Connector J11 ........................................................................... 46
3.6.8. Asynchronous DRAM SIMM Connections CN1 ..............................................................................47
APPENDIX A PALLV16V8 CODE – PALASM4...................................................................................................... 49
APPENDIX B SCHEMATICS .................................................................................................................................... 51
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TABLES
TABLE 1 – JP2, CS0 SELECT ................................................................................................................................................ 12
TABLE 2 – JP1, DRAM SIMM VOLTAGE SELECTION ........................................................................................................... 12
TABLE 3 – JP3, BDM OR JTAG OPERATION ......................................................................................................................... 13
TABLE 4 – JP4, 3.3V OR 5V SUPPLY FOR THE BDM I/F ........................................................................................................ 13
TABLE 5 – JP5, CURRENT MEASUREMENT OF THE MCF5206e ................................................................................................ 13
TABLE 6 - dBUG COMMANDS .............................................................................................................................................. 18
TABLE 7 - THE M5206eLITE MEMORY MAP ......................................................................................................................... 39
TABLE 8 - THE J9 (TERMINAL) CONNECTOR PIN ASSIGNMENT .................................................................................................. 41
TABLE 9 - THE J4 CONNECTOR PIN ASSIGNMENT ..................................................................................................................... 42
TABLE 10 - THE J5 CONNECTOR PIN ASSIGNMENT ................................................................................................................... 42
TABLE 11 - THE J1 CONNECTOR PIN ASSIGNMENT ................................................................................................................... 43
TABLE 12 - THE J2 CONNECTOR PIN ASSIGNMENT ................................................................................................................... 44
TABLE 13 - THE J3 CONNECTOR PIN ASSIGNMENT ................................................................................................................... 45
TABLE 14 - THE J10 CONNECTOR PIN ASSIGNMENT ................................................................................................................. 46
TABLE 15 - THE J11 CONNECTOR PIN ASSIGNMENT ................................................................................................................. 46
TABLE 16 - THE CN1 CONNECTOR PIN ASSIGNMENT ............................................................................................................... 47
FIGURES
FIGURE 1 BLOCK DIAGRAM OF THE BOARD ............................................................................................................................... 7
FIGURE 2 PIN ASSIGNMENT FOR J4 (TERMINAL) CONNECTOR. ................................................................................................... 10
FIGURE 3 SYSTEM CONFIGURATION ........................................................................................................................................ 11
FIGURE 4 JUMPER AND CONNECTOR PLACEMENT ...................................................................................................................... 11
FIGURE 5 FLOW DIAGRAM OF dBUG OPERATIONAL MODE. .................................................................................................... 15
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INTRODUCTION TO THE M5206eLITE BOARD
1.1 INTRODUCTION
The M5206eLITE is a versatile single board computer based on MCF5206e ColdFire® Processor. It may be used
as a powerful microprocessor based controller in a variety of applications. With the addition of a terminal, it
serves as a complete microcomputer system for development/evaluation, training and educational use. To have a
fully functional system, all that is required is an RS-232 terminal (or a PC with terminal emulation software) and
a regulated 5V power supply.
It is possible to expand the memory and I/O capabilities of this board by connecting additional hardware via the
MicroprocessorExpansionBus connectors, although it maybenecessary to add bus bufferstoaccomodateadditional
bus loading.
Furthermore, provisions have been made on the printed circuit board (PCB) to permit configuration of the board
in a way which best suits an application. Options available are: up to 32M bytes of ADRAM (FPM or EDO – not
fitted), 1M byte (256Kx32) FSRAM, Timers, general purpose I/O, an MBus(I2C) slave device (real-time clock)
and 1M byte (512Kx16) of Flash EEPROM. All of the processor’s signals are also available via connectors J1 and
J2 for expansion purposes.
1.2 GENERAL HARDWARE DESCRIPTION
The M5206eLITE board provides FSRAM, Flash ROM, RS232 and all the built-in I/O functions of the MCF5206e
for learning and evaluating the attributes of the MCF5206e. The MCF5206e is a member of the ColdFire® family
of processors. It is a 32-bit processor with up to 32 bits of addressing and 32 lines of data. The processor has eight
32-bit data registers, eight 32-bit address registers, a 32-bit program counter and a 16-bit status register.
The MCF5206e has a System Integration Module referred to as SIM. The module incorporates many of the
functions needed for system design. These include programmable chip-select logic, system protection logic,
general purpose I/O and interrupt controller logic. The chip-select logic can select up to eight memory banks or
peripherals in addition to two banks of ADRAMs. The chip-select logic also allows a programmable number of
wait-states to allow the use of slower access memory (refer to MCF5206e User’s Manual by Motorola for detailed
information about configuration of the SIM - system integration module.) The M5206eLITE board only uses
three of the available chip selects to access the Flash EEPROM, FSRAM and the extra GPIO. The on-chip
ADRAM controller can be used to control one ADRAM SIMM module of up to 32M bytes of ADRAM (the
ADRAM SIMM is not fitted to the board, but can easily be added by the user), both -RAS lines and all four –CAS
lines are used. All other functions of the SIM are available to the user.
A hardware watchdog timer (Bus Monitor) circuit is included in the SIM that monitors the bus activities. If a
bus cycle is not terminated within a programmable time, the watchdog timer will assert an internal transfer
error signal to terminate the bus cycle. A block diagram of the board is shown in Figure 1.
Figure 1 Block Diagram of the board
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1.3 SYSTEM MEMORY
There is one on board Flash EEPROM (U4), which is configured in hardware to be 16-bits wide. The M5206eLITE
comes with the AM29LV800BB Flash EEPROM programmed with debugger/monitor firmware(dBUG). The
AM29LV800BB Flash EEPROM is 8Mbits giving a total of 1M byte (512Kx16) of Flash memory. This version
of dBUG monitor only supports AM29LV800BB Flash EEPROM.
There is one 72-pin SIMM socket for ADRAM (ADRAM SIMM not fitted).
The MCF5206e processor has 8K bytes organized as 2048x32 bits of internal SRAM.
The internal cache of the MCF5206e is a non-blocking 4k-Byte Direct-Mapped Instruction Cache. The ROM
Monitor currently does not utilize the cache, but programs downloaded with the ROM Monitor can use the cache.
1.4 SERIAL COMMUNICATION CHANNELS
The MCF5206e has 2 UART’s with independent baud rate generators. The signals of channel one are passed
through external Driver/Receivers to make the channel compatible with RS-232. UART1 is used by the debugger
for the user to access with a terminal. The UART1 channel is the “TERMINAL” channel used by the debugger for
communication with external terminal/PC. The “TERMINAL’ baud rate is set at 19200. The signals of channel
two are passed directly to connector J4, where they can be used for 5V serial communications.
The MCF5206e also incorporates the M-Bus module, which is compatible with the MBus(I2C) standard. Connected
to the MBus(I2C) bus as a slave device, is a Dallas Semiconductor real time clock and NVRAM (64 bytes) device,
U17 – DS1307Z. At manufacture this device is programmed with the time and date which is battery backed up
(BT1). This can be read back or written, using the M5206eLITE MBus(I2C) sample code provided on the ColdFire
web site – http://www.motorola.com/ColdFire/.
1.5 PARALLEL I/O PORTS
The MCF5206e processor offers one 8-bit general-purpose parallel I/O port. Each pin can be individually
programmed as input or output. The parallel port bits PP(3:0) are multiplexed with PST(3:0) and PP(7:4) are
multiplexed with DDATA(3:0). The Pin Assignment Register (PAR) controls both nibbles of the parallel port.
After reset, all pins are configured as PST and DDATA pins to allow real time trace and debug. Apart from the on-
chip GPIO there are two memory mapped bus transceivers (U14 & U15) controlled via chip select 3. Transceiver
U14 is configured for output only and drives a 7-segment LED display, which provides status information about
the board. One line of U14 (A7) also drives the direction control signal of transceiver U15. This allows the
developer to use U15 for input or output. Input is limited to 5V signals via connector J10 on the board. Output
however can be either 3.3V at connector J10, or a much higher voltage supplied by external hardware on pin 9 of
J11. Connector J11 is driven by an open collector device, U16 – ULN2803A, allowing high drive I/O.
1.6 PROGRAMMABLE TIMER/COUNTER
The MCF5206e has two built in general-purpose 16-bit timer/counters. These timers are available to the user. The
signals for the timers are available on the J1 and J2 connectors. The signals for timer/counter 0 are multiplexed
withtheDMArequest signals DREQ0 (TIN1) and DREQ1 (TOUT1).The functionality of these pins isprogrammed
via the PAR register (Pin Assignment Register) during initialization of the processor.However, timer 0 is available
to the user as an internal counter/timer, e.g. for an RTOS system clock.
1.7 SYSTEM CONFIGURATION
The M5206eLITE board requires the following items for minimum system configuration (Figure 3):
1. The M5206eLITE board (provided).
2. Regulated power supply, 5V with minimum of 1.5 Amps.
3. RS-232C compatible terminal or a PC with terminal emulation software.
4. Serial communication cable (not provided).
5. Macraigor BDM cable (part of the Mentor toolkit provided with the board).
Refer to next sections for the initial setup.
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1.8 INSTALLATION AND SETUP
The following sections describe all the steps needed to prepare the board for operation. Please read the following
sections carefully before using the board. When the board is set up for the first time, ensure that all jumpers are in
the default locations. The standard configuration does not require any modifications. After the board is setup in its
standard configuration, you may use the BDM cable by following the instructions provided in the following
sections.
1.8.1. Unpacking
Unpack the computer board from its shipping box. Save the box for storing or reshipping. Refer to the following
list and verify that all the items are present. You should have received:
• M5206eLITE Single Board Computer
• M5206eLITE User’s Manual, this documentation
• One Macraigor BDM cable (part of the Mentor toolkit)
• MCF5206e User’s Manual
• ColdFire Programmer’s Reference Manual
• Motorola Literature CDROM
• Getting Started Documentation
From participating Third Party Tool Developers - faxback
trial forms & trial software on CD
• Mentor Graphics - Microtec Product Division - BDM
cable, Trial Compiler & “XRAY4” Debugger
• Software Development Systems - Trial
“SingleStep” Debugging Software
• Noral Micrologics - Faxback trial form for a BDM
based debugging cable & a mouse mat
• Diab Data - Trial compiler tool chain
• Embedded Support Tools (EST) - Faxback trial
form for debugging hardware & “VisionClick”
software
• WindRiver Systems - trial compiler toolchain &
RTOS
• Green Hills Software - Trial compiler toolchain &
debugging suite
• Accelerated Technology - Trial “Nucleus+” RTOS
WARNING
AVOID TOUCHING THE MOS DEVICES. STATIC DISCHARGE CAN AND
WILL DAMAGE THESE DEVICES.
Once you verified that all the items are present, remove the board from its protective jacket. Check the board for
any visible damage. Ensure that there are no broken, damaged, or missing parts. If you have not received all the
items listed above or they are damaged, please contact Williams Electronic Design immediately
([email protected]). Each board carries a 12 months return to manufacturer warranty – whether the
board is repaired or replaced is at the manufacturers discretion.
1.8.2. Preparing the Board for Use
The board as shipped is ready to be connected to a terminal and a power supply without any need for modification.
However, follow the steps below to ensure proper operation from the first time you apply the power. Figure 4
shows the placement of the jumpers and the connectors, which you need to refer to in the following sections. The
steps to be taken are:
a. Connecting the power supply.
b. Connecting the terminal.
1.8.3. Providing Power to the Board
Connector J8 is a screw terminal connector. The board accepts 5V DC (regulated) at 1.5 Amps via this connector.
Power supplied to the processor passes through jumper JP5. This does not include resistors used to pull-up signals
attached to the processor. Jumper JP5 can be removed and with the use of a current meter, can be used to perform
power analysis of the MCF5206e.
Contact No. Voltage
1 +5V
2 Ground
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1.8.4. Selecting Terminal Baud Rate
The serial channel of MCF5206e that is used for serial communication has a built in timer used by the ROM
MONITOR to generate the baud rate used to communicate with a terminal. It can be programmed to a number of
baud rates. After the power-up or a manual RESET, the ROM Monitor firmware configures the channel for 19200
baud. After the ROM Monitor is running, the SET command may be issued to choose any baud rate supported by
the ROM Monitor. Refer to Chapter 2 for the discussion of this command.
1.8.5. The Terminal Character Format
The character format of the communication channel is fixed at power-up or RESET of the board. The character
format is 8 bits per character, no parity, and one stop bit. You need to ensure that your terminal or PC is set to this
format.
1.8.6. Connecting the Terminal
The board is now ready to be connected to a terminal. Use an RS-232 serial cable to connect the PC to the
M5206eLITE. The cable should have a 9-pin female D-sub connector at one end and a 9-pin male D-sub connector
at the other end. Connect the 9-pin male connector to the J9 connector on the M5206eLITE. Connect the 9-pin
female connector to one of the available serial communication channels normally referred to as COM1 (COM2,
etc.) on the IBM PC or compatible. Depending on the kind of serial connector on the back of your PC, the
connector on your PC may be a male 25-pin or 9-pin. You may need to obtain a 9-pin-to-25-pin adapter to make
the connection. If you need to build an adapter, refer to Figure 2 that shows the pin assignment for the 9-pin
connector on the board.
1.8.7. Using a Personal Computer as a Terminal
You may use your personal computer as a terminal provided you also have a terminal emulation software such as
PROCOMM, KERMIT, QMODEM, Windows 95 Hyper Terminal or similar packages. Then connect as described
in 1.8.6 Connecting the Terminal.
Once the connection to the PC is made, you are ready to power-up the PC and run the terminal emulation software.
When you are in the terminal mode, you need to select the baud rate and the character format for the channel.
Most terminal emulation software packages provide a command known as “Alt-p” (press the p key while pressing
the Alt key) to choose the baud rate and character format. Make sure you select 8 bits, no parity, one stop bit, see
section 1.8.5 The Terminal Character Format. Then, select the baud rate as 19200. Now you are ready to apply
power to the board.
Figure 2 Pin assignment for J4 (Terminal) connector.
1.Data Carrier Detect, Output (shorted to pin 6).
2. Receive Data, Output from board (receive refers to terminal side).
3. Transmit Data, Input to board (transmit refers to terminal side).
4. Data Terminal Ready, input (not connected – could be shorted to pins 1 & 6).
5. Signal Ground.
6. Data Set Ready, Output (shorted to pin 1).
7. Request to Send, input.
8. Clear to send, output
9. Not connected.
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Figure 3 System Configuration
Figure 4 Jumper and connector placement
/
MBus
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1.9 SYSTEM POWER-UP AND INITIAL OPERATION
When the cables are connected, power may be applied to the board. After power is applied the dBUG monitor
program initializes the board, then displays the power-up message on the terminal. The amount of memory
present will also be displayed.
Hard Reset
FSRAM Size: 1M
Copyright 1997-1999 Motorola, Inc. All Rights Reserved.
ColdFire® MCF5206e EVS Debugger Vx.x.x (xxx 199x xx:xx:xx:)
Enter ‘help’ for help.
dBUG>
The board is now ready for operation under the control of the debugger as described in Chapters 2. If you do
not get the above response, perform the following checks:
1. Make sure that the power supply is set to the correct voltage and current levels and is
properly connected to the board.
2. Check that the terminal and board are set for the same character format and baud.
3. Press the black RESET (S1) button to ensure that the board has been initialized
properly.
If you are not receiving the proper response, your board may have been damaged. Contact Williams Electronic
Design ([email protected]) for further help.
1.10 M5206eLITE Jumper Setup
The jumpers on the board are discussed in Chapter 3. However, a brief discussion of the jumper settings
follows:
1.10.1. Jumper JP2 - This jumper selects between -CS0 to Flash or off-board connector J1
Table 1 – JP2, -CS0 select
JP2 Function
1 and 2 Flash ROM U4 (default)
2 and 3 Header (J1)
1.10.2. Jumper JP1 – ADRAM SIMM voltage selection – 5V or 3.3V
This jumper allows the selection of either 5V or 3.3V supply to the ADRAM SIMM. The default is 5V.
Table 2 – JP1, ADRAM SIMM Voltage Selection
JP1 Function
1 and 2 5V supply (default)
2 and 3 3.3V supply
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1.10.3. Jumper JP3 - This jumper selects between BDM & JTAG operation of the MCF5206e
Table 3 – JP3, -BDM or JTAG Operation
JP3 Function
1 and 2 BDM operation (default)
2 and 3 JTAG operation
1.10.4. Jumper JP4 - This jumper selects between 3.3V or 5V supply to the BDM cable
As the Macraigor BDM cable, supplied as part of this evaluation kit, is a 3.3V cable, 3.3V is the default setting.
Table 4 – JP4, -3.3V or 5V supply for the BDM I/F
JP4 Function
1 and 2 5V supply
2 and 3 3.3V supply (default)
1.10.5. Jumper JP5 - This jumper allows MCF5206e current consumption to be measured
With the jumper fitted, current is supplied to the MCF5206e processor as normal. With the jumper removed, a
current meter can be connected to pins 1 & 2 of the jumper to measure the current required by the MCF5206e.
Table 5 – JP5, -Current measurement of the MCF5206e
JP3 Function
1 and 2 Jumper fitted (default)
1.11 USING THE BDM
TheMCF5206ehasabuilt in debug mechanism referred to as BDM (Background Debug Mode). The M5206eLITE
board has the necessary connector, J3, to facilitate this connection.
In order to use BDM, simply connect the 26-pin IDC header to the J3 connector. No special setting is needed.
Refer to the BDM section of the MCF5206e User’s Manual for additional instructions.
IMPORTANT: There is no key to protect the BDM cable from being rotated and plugged in incorrectly. To
prevent hooking up the BDM cable incorrectly, the position of pin 1 is clearly marked on the board and is denoted
by a red strip on the cable.
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CHAPTER 2
USING THE MONITOR/DEBUG FIRMWARE
The M5206eLITE Computer Board has a resident firmware package that provides a self-contained programming
and operating environment. The firmware, named dBUG, provides the user with monitor/debug, disassembly,
program download, and I/O control functions. This Chapter is a description of the dBUG package, including the
user interface and command structure.
2.1 WHAT IS dBUG?
dBUG is a resident firmware package for the ColdFire® family Computer Boards. The firmware (stored in one
512Kx16FlashROMdevice)provides a self-contained programming and operating environment. The user interacts
with dBUG through pre-defined commands that are entered via an RS232 terminal.
The user interface to dBUG is the command line. A number of features have been implemented to achieve an easy
and intuitive command line interface.
dBUG assumes that an 80x24 character dumb-terminal is utilized to connect to the debugger. For serial
communications, dBUG requires eight data bits, no parity, and one stop bit, 8N1. The baud rate is 19200 baud
which can be changed after power-up.
The command line prompt is “dBUG> “. Any dBUG command may be entered from this prompt. dBUG does not
allow command lines to exceed 80 characters. Wherever possible, dBUG displays data in 80 columns or less.
dBUG echoes each character as it is typed, eliminating the need for any “local echo” on the terminal side.
In general, dBUG is not case sensitive. Commands may be entered either in upper or lower case, depending upon
the user’s equipment and preference. Only symbol names require that the exact case be used.
Most commands can be recognized by using an abbreviated name. For instance, entering “h” is the same as
entering “help”. Thus, it is not necessary to type the entire command name.
The commands DI, GO, MD, STEP and TRACE are used repeatedly when debugging. Therefore dBUG allows
for repeated execution of these commands with minimal typing. After a command is entered, simply press
<RETURN> or <ENTER> to invoke the command again. The command is executed as if no command line
parameters were provided.
An additional function called the “TRAP 15 handler” allows the user program to utilize various routines within
dBUG. The TRAP 15 handler is discussed at the end of this chapter.
The operational mode of dBUG is demonstrated in Figure 5. After the system initialization, the board waits for a
command-line input from the user terminal. When a proper command is entered, the operation continues in one of
the two basic modes. If the command causes execution of the user program, the dBUG firmware may or may not
be re-entered, depending on the operation of the user’s code. In the alternate case, the command will be executed
under control of the dBUG firmware, and after command completion, the system returns to command entry mode.
During command execution, additional user input may be required depending on the command function.
For commands that accept an optional <width> to modify the memory access size, the valid values are:
.B 8-bit (byte) access
.W 16-bit (word) access
.L 32-bit (long) access
When no <width> option is provided, the default width is .W, 16-bit.
The core ColdFire® register set is maintained by dBUG. These are listed below:
A0-A7
D0-D7
PC
SR
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AllcontrolregistersonColdFire®arereadableonlyvia the supervisor-programming model, and thus not accessible
via dBUG. User code may change these registers, but caution must be exercised as changes may render dBUG
useless.
A reference to “SP” actually refers to “A7”.
2.2 OPERATIONAL PROCEDURE
System power-up and initial operation are described in detail in Chapter 1. This information is repeated here for
convenience and to prevent possible damage.
2.2.1. System Power-up
a. Be sure the power supply is connected properly prior to power-up.
b. Make sure the terminal is connected to TERMINAL (J9) connector.
c. Turn power on to the board.
Figure 5 Flow Diagram of dBUG Operational Mode.
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2.2.2. System Initialization
The act of powering up the board will initialize the system. The processor is reset and dBUG is invoked.
dBUG performs the following configurations of internal resources during the initialization. The instruction cache
is invalidated and disabled. The Vector Base Register, VBR, points to the Flash. However, a copy of the exception
table is made at address $30000000 in FSRAM. To take over an exception vector, the user places the address of
the exception handler in the appropriate vector in the vector table located at 0x30000000, and then points the
VBR to 0x30000000.
The Software Watchdog Timer is disabled, Bus Monitor enabled, and internal timers are placed in a stop condition.
Interrupt controller registers initialized with unique interrupt level/priority pairs.
After initialization, the terminal will display:
Hard Reset
FSRAM Size: 1M
Copyright 1997-1999 Motorola, Inc. All Rights Reserved.
ColdFire® MCF5206e EVS Debugger Vx.x.x (xxx 199x xx:xx:xx:)
Enter ‘help’ for help.
dBUG>
If you did not get this response check the setup. Refer to Section 1.9 SYSTEM POWER-UP AND INITIAL
OPERATION. Note, the date ‘xxx 199x xx:xx:xx’ may vary in different revisions.
Other means can be used to re-initialize the M5206eLITE Computer Board firmware. These means are discussed
in the following paragraphs.
2.2.2.1. Hard RESET Button.
Hard RESET is the black push button switch (S1) located in the corner of the board. Depressing this switch causes
all processes to terminate, resets the MCF5206e processor and board logic and restarts the dBUG firmware.
Pressing the RESET button would be the appropriate action if all else fails.
2.2.2.2. Software Reset Command.
dBUG does have a command that causes the dBUG to restart as if a hardware reset was invoked. The command
is “RESET”.
2.2.2.3. USER Program.
The user can return control of the system to the firmware by recalling dBUG via his/her program. Instructions can
be inserted into the user program to call dBUG via the TRAP 15 handler.
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2.2.3. System Operation
After system initialization, the terminal will display:
Hard Reset
FSRAM Size: 1M
Copyright 1997-1999 Motorola, Inc. All Rights Reserved.
ColdFire® MCF5206e EVS Debugger Vx.x.x (xxx 199x xx:xx:xx:)
Enter ‘help’ for help.
dBUG>
and waits for a command.
The user can call any of the commands supported by the firmware. A standard input routine controls the system
while the user types a line of input. Command processing begins only after the line has been entered and followed
by a carriage-return.
NOTES
1. The user memory is located at addresses $30020000-$300FFFFF, $300FFFFF is the
maximum FSRAM address of the memory installed on the board. When first learning
the system, the user should limit his/her activities to this area of the memory map.
Address range $30000000-$3001FFFF is used by dBUG.
2. If a command causes the system to access an unused address (i.e., no memory or
peripheral devices are mapped at that address), a bus trap error will occur. This results
in the terminal printing out a trap error message and the contents of all the MCF5206e
core registers. Control is returned to the dBUG monitor.
2.3 TERMINAL CONTROL CHARACTERS
The command line editor remembers the last five commands, in a history buffer, which were issued. They can be
recalled and then executed using control keys.
Several keys are used as a command line edit and control functions. It is best to be familiar with these functions
before exercising the system. These functions include:
a. RETURN (carriage- return) - will enter the command line and causes processing to begin.
b. Delete (Backspace) key or CTRL-H - will delete the last character entered on the terminal.
c. CTRL-D - Go down in the command history buffer, you may modify then press enter key.
d. CTRL-U - Go up in the command history buffer, you may modify then press enter key.
e. CTRL-R - Recall and execute the last command entered, does not need the enter key to be pressed.
For characters requiring the control key (CTRL) , the CTRL should be pushed and held down and then the other
key (H,D,U or R) should be pressed.
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2.4 dBUG COMMAND SET
Table 6 lists the dBUG commands. Each of the individual commands is described in the following pages.
Table 6 - dBUG Commands
COMMAND DESCRIPTION SYNTAX PAGE
MNEMONIC
AS ASSEMBLE AS <addr> <instruction> 18
BC BLOCK COMPARE BC<FIRST><SECOND><LENGTH> 20
BF BLOCK FILL BF<WIDTH> BEGIN END DATA 20
BM BLOCK MOVE BM BEGIN END DEST 21
BS BLOCK SEARCH BS <WIDTH> BEGIN END DATA 22
BR BREAKPOINT BR ADDR <-R> <-C COUNT> <-T TRIGGER> 23
DATA DATA CONVERT DATA VALUE 24
DI DISASSEMBLE DI <ADDR> 24
DL DOWNLOAD SERIAL DL <OFFSET> 25
GO EXECUTE GO <ADDR> 25
GT Go TILL BREAKPOINT GT <ADDR> 26
HELP HELP HELP <COMMAND> 26
IRD INTERNAL REGISTER DISPLAY IRD <MODULE.REGISTER> 26
IRM INTERNAL REGISTER MODIFY IRM <MODULE.REGISTER> <DATA> 27
MD MEMORY DISPLAY MD <WIDTH> <BEGIN> <END> 27
MM MEMORY MODIFY MM <WIDTH> ADDR <DATA> 28
RD REGISTER DISPLAY RD <REG> 28
RM REGISTER MODIFY RM REG DATA 29
RESET RESET RESET 29
SET SET CONFIGURATIONS SET OPTION <VALUE> 30
SHOW SHOW CONFIGURATIONS SHOW OPTION 30
STEP STEP (OVER) STEP 31
SYMBOL SYMBOL MANAGEMENT SYMBOL <SYMB> <-A SYMB VALUE> <-R SYMB> <-C | L | S> 31
TRACE TRACE(INTO) TRACE <NUM> 32
UPDBUG UPDATE DBUG UPDBUG 32
UPUSER UPDATE USER FLASH UPUSER 33
VERSION SHOW VERSION VERSION 33
2.4.1. AS - Assemble AS
Usage: AS <addr> <instruction>
The AS command assembles instructions. The value for addr may be an absolute address specified as a
hexadecimal value, or a symbol name. Instruction may be any valid instruction for the target processor.
The assembler keeps track of the address where the last instruction’s opcode was written. If no address is
provided to the AS command and the AS command has not been used since system reset, then AS defaults to
the beginning address of user-space for the target board.
If no instruction is passed to the AS command, then AS prompts with the address where opcode will be written,
and continues to assemble instructions until the user terminates the AS command by inputting a period, “.”.
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The inline assembler permits the use of case-sensitive symbols defined by equate statements and labels which
are stored in the symbol table. The syntax for defining symbols and labels is as follows:
Symbol equ value
Symbol: equ value
Symbol .equ value
Symbol: .equ value
Label: instruction
Label:
Constants and operands may be input in several different bases:
0x followed by hexadecimal constant
$ followed by hexadecimal constant
@ followed by octal constant
% followed by binary constant
digit decimal constant
The assembler also supports the different syntax’s capable for the indexed, displacement and immediate
addressing modes:
(12,An) or 12(An)
(4,PC,Xn) or 4(PC,Xn)
(0x1234).L or 0x1234.L
Examples:
To assemble one ‘move’ instructions at the next assemble address, the command is:
as move.l #0x25,d0
To assemble multiple lines at 0x30112000, the command is:
as 12000
then:
0x30112000: start: nop
0x30112002: nop
0x30112004: lsr.l #1,d0
0x30112006: cmp #4,d0
0x30112008: beq start
0x3011200A:
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