Fujitsu FR Family User manual

FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
FR Family
32-BIT MICROCONTROLLER
INSTRUCTION MANUAL
CM71-00101-4E

FUJITSU LIMITED
FR Family
32-BIT MICROCONTROLLER
INSTRUCTION MANUAL
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Be sure to refer to the “Check Sheet” for the latest cautions on development.

i
PREFACE
■Objectives and intended reader
The FR family CPU core features proprietary Fujitsu architecture and is designed for controller
applications using 32-bit RISC based computing. The architecture is optimized for use in microcontroller
CPU cores for built-in control applications where high-speed control is required.
This manual is written for engineers involved in the development of products using the FR family of
microcontrollers. It is designed specifically for programmers working in assembly language for use with
FR family assemblers, and describes the various instructions used with FR family. Be to read the entire
manual carefully.
Note that the use or non-use of coprocessors, as well as coprocessor specifications depends on the functions
of individual FR family products.
For information about coprocessor specifications, users should consult the coprocessor section of the
product documentation. Also, for the rules of assembly language grammar and the use of assembler
programs, refer to the "FR Family Assembler Manual".
FR, which is an abbreviation of FUJITSU RISC controller, is a product of Fujitsu Limited.

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■Organization of this manual
This manual consists of the following 7 chapters and 1 appendix:
CHAPTER 1 FR FAMILY OVERVIEW
This chapter describes the features of the FR FAMILY CPU core, and provides sample
configurations.
CHAPTER 2 MEMORY ARCHITECTURE
This chapter describes memory space in the FR family CPU. Memory architecture includes the
allocation of memory space as well as methods used to access memory.
CHAPTER 3 REGISTER DESCRIPTIONS
This chapter describes the registers used in the FR family CPU.
CHAPTER 4 RESET AND "EIT" PROCESSING
This chapter describes reset and "EIT" processing in the FR family CPU. A reset is a means of
forcibly terminating the currently executing process, initializing the entire device, and restarting
the program from the beginning. "EIT" processing, in contrast, terminates the currently
executing process and saves restart information to memory, then transfers control to a
predetermined processing program. "EIT" processing programs can return to the prior program
by use of the "RETI" instruction. "EIT" processing operates in essentially the same manner for
exceptions, interrupts and traps, with the following minor differences.
CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU
This chapter presents precautionary information related to the use of the FR family CPU.
CHAPTER 6 INSTRUCTION OVERVIEW
This chapter presents an overview of the instructions used with the FR family CPU. All FR
family CPU instructions are in 16-bit fixed length format, except for immediate data transfer
instructions which may exceed 16 bits in length. This format enables the creation of compact
object code and smoother pipeline processing.
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS
This chapter presents each of the execution instructions used by the FR family assembler, in
reference format. The execution instructions used by the FR family CPU are classified as
follows.
APPENDIX
The appendix section includes lists of CPU instructions used in the FR family, as well as instruction map
diagrams.

iii
Copyright ©1997-2006 FUJITSU LIMITED All rights reserved.
• The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented solely
for the purpose of reference to show examples of operations and uses of FUJITSU semiconductor device; FUJITSU does
not warrant proper operation of the device with respect to use based on such information. When you develop equipment
incorporating the device based on such information, you must assume any responsibility arising out of such use of the
information. FUJITSU assumes no liability for any damages whatsoever arising out of the use of the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as
license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of
FUJITSU or any third party or does FUJITSU warrant non-infringement of any third-party's intellectual property right or
other right by using such information. FUJITSU assumes no liability for any infringement of the intellectual property rights
or other rights of third parties which would result from the use of information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use
requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that FUJITSU will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such
failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
• If any products described in this document represent goods or technologies subject to certain restrictions on export under
the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for
export of those products from Japan.

iv

v
CONTENTS
CHAPTER 1 FR FAMILY OVERVIEW .............................................................................. 1
1.1 Features of the FR Family CPU Core ................................................................................................. 2
1.2 Sample Configuration of an FR Family Device ................................................................................... 3
1.3 Sample Configuration of the FR Family CPU ..................................................................................... 4
CHAPTER 2 MEMORY ARCHITECTURE ........................................................................ 5
2.1 FR Family Memory Space .................................................................................................................. 6
2.1.1 Direct Address Area ...................................................................................................................... 7
2.1.2 Vector Table Area .......................................................................................................................... 8
2.2 Bit Order and Byte Order .................................................................................................................. 10
2.3 Word Alignment ................................................................................................................................ 11
CHAPTER 3 REGISTER DESCRIPTIONS ...................................................................... 13
3.1 FR Family Register Configuration ..................................................................................................... 14
3.2 General-purpose Registers ............................................................................................................... 15
3.3 Dedicated Registers ......................................................................................................................... 17
3.3.1 Program Counter (PC) ................................................................................................................. 18
3.3.2 Program Status (PS) ................................................................................................................... 19
3.3.3 Table Base Register (TBR) ......................................................................................................... 23
3.3.4 Return Pointer (RP) ..................................................................................................................... 25
3.3.5 System Stack Pointer (SSP), User Stack Pointer (USP) ............................................................. 27
3.3.6 Multiplication/Division Register (MD) ........................................................................................... 29
CHAPTER 4 RESET AND "EIT" PROCESSING ............................................................ 31
4.1 Reset Processing .............................................................................................................................. 33
4.2 Basic Operations in "EIT" Processing ............................................................................................... 34
4.3 Interrupts ........................................................................................................................................... 37
4.3.1 External Interrupts ....................................................................................................................... 38
4.3.2 Non-maskable Interrupts (NMI) ................................................................................................... 40
4.4 Exception Processing ....................................................................................................................... 42
4.4.1 Undefined Instruction Exceptions ................................................................................................ 43
4.5 Traps ................................................................................................................................................. 44
4.5.1 "INT" Instructions ......................................................................................................................... 45
4.5.2 "INTE" Instruction ........................................................................................................................ 46
4.5.3 Step Trace Traps ......................................................................................................................... 47
4.5.4 Coprocessor Not Found Traps .................................................................................................... 48
4.5.5 Coprocessor Error Trap ............................................................................................................... 49
4.6 Priority Levels ................................................................................................................................... 51
CHAPTER 5 PRECAUTIONARY INFORMATION FOR THE FR FAMILY CPU ............. 53
5.1 Pipeline Operation ............................................................................................................................ 54
5.2 Pipeline Operation and Interrupt Processing .................................................................................... 55
5.3 Register Hazards .............................................................................................................................. 56

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5.4 Delayed Branching Processing ......................................................................................................... 58
5.4.1 Processing Non-delayed Branching Instructions ......................................................................... 60
5.4.2 Processing Delayed Branching Instructions ................................................................................ 61
CHAPTER 6 INSTRUCTION OVERVIEW ....................................................................... 63
6.1 Instruction Formats ........................................................................................................................... 64
6.2 Instruction Notation Formats ............................................................................................................. 66
CHAPTER 7 DETAILED EXECUTION INSTRUCTIONS ................................................ 67
7.1 ADD (Add Word Data of Source Register to Destination Register) .................................................. 72
7.2 ADD (Add 4-bit Immediate Data to Destination Register) ................................................................. 73
7.3 ADD2 (Add 4-bit Immediate Data to Destination Register) ............................................................... 74
7.4 ADDC (Add Word Data of Source Register and Carry Bit to Destination Register) ......................... 75
7.5 ADDN (Add Word Data of Source Register to Destination Register) ............................................... 76
7.6 ADDN (Add Immediate Data to Destination Register) ...................................................................... 77
7.7 ADDN2 (Add Immediate Data to Destination Register) .................................................................... 78
7.8 SUB (Subtract Word Data in Source Register from Destination Register) ....................................... 79
7.9 SUBC (Subtract Word Data in Source Register and Carry Bit from Destination Register) ............... 80
7.10 SUBN (Subtract Word Data in Source Register from Destination Register) ..................................... 81
7.11 CMP (Compare Word Data in Source Register and Destination Register) ...................................... 82
7.12 CMP (Compare Immediate Data of Source Register and Destination Register) .............................. 83
7.13 CMP2 (Compare Immediate Data and Destination Register) ........................................................... 84
7.14 AND (And Word Data of Source Register to Destination Register) .................................................. 85
7.15 AND (And Word Data of Source Register to Data in Memory) ......................................................... 86
7.16 ANDH (And Half-word Data of Source Register to Data in Memory) ................................................ 88
7.17 ANDB (And Byte Data of Source Register to Data in Memory) ........................................................ 90
7.18 OR (Or Word Data of Source Register to Destination Register) ....................................................... 92
7.19 OR (Or Word Data of Source Register to Data in Memory) .............................................................. 93
7.20 ORH (Or Half-word Data of Source Register to Data in Memory) .................................................... 95
7.21 ORB (Or Byte Data of Source Register to Data in Memory) ............................................................. 97
7.22 EOR (Exclusive Or Word Data of Source Register to Destination Register) .................................... 99
7.23 EOR (Exclusive Or Word Data of Source Register to Data in Memory) ......................................... 100
7.24 EORH (Exclusive Or Half-word Data of Source Register to Data in Memory) ................................ 102
7.25 EORB (Exclusive Or Byte Data of Source Register to Data in Memory) ........................................ 104
7.26 BANDL (And 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) ................................ 106
7.27 BANDH (And 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) ............................... 108
7.28 BORL (Or 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) ..................................... 110
7.29 BORH (Or 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) ................................... 112
7.30 BEORL (Eor 4-bit Immediate Data to Lower 4 Bits of Byte Data in Memory) ................................. 114
7.31 BEORH (Eor 4-bit Immediate Data to Higher 4 Bits of Byte Data in Memory) ............................... 116
7.32 BTSTL (Test Lower 4 Bits of Byte Data in Memory) ....................................................................... 118
7.33 BTSTH (Test Higher 4 Bits of Byte Data in Memory) ..................................................................... 119
7.34 MUL (Multiply Word Data) .............................................................................................................. 120
7.35 MULU (Multiply Unsigned Word Data) ............................................................................................ 122
7.36 MULH (Multiply Half-word Data) ..................................................................................................... 124
7.37 MULUH (Multiply Unsigned Half-word Data) .................................................................................. 126
7.38 DIV0S (Initial Setting Up for Signed Division) ................................................................................. 128

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7.39 DIV0U (Initial Setting Up for Unsigned Division) ............................................................................. 130
7.40 DIV1 (Main Process of Division) ..................................................................................................... 132
7.41 DIV2 (Correction when Remainder is 0) ......................................................................................... 134
7.42 DIV3 (Correction when Remainder is 0) ......................................................................................... 136
7.43 DIV4S (Correction Answer for Signed Division) ............................................................................. 137
7.44 LSL (Logical Shift to the Left Direction) .......................................................................................... 138
7.45 LSL (Logical Shift to the Left Direction) .......................................................................................... 139
7.46 LSL2 (Logical Shift to the Left Direction) ........................................................................................ 140
7.47 LSR (Logical Shift to the Right Direction) ....................................................................................... 141
7.48 LSR (Logical Shift to the Right Direction) ....................................................................................... 142
7.49 LSR2 (Logical Shift to the Right Direction) ..................................................................................... 143
7.50 ASR (Arithmetic Shift to the Right Direction) .................................................................................. 144
7.51 ASR (Arithmetic Shift to the Right Direction) .................................................................................. 145
7.52 ASR2 (Arithmetic Shift to the Right Direction) ................................................................................ 146
7.53 LDI:32 (Load Immediate 32-bit Data to Destination Register) ........................................................ 147
7.54 LDI:20 (Load Immediate 20-bit Data to Destination Register) ........................................................ 148
7.55 LDI:8 (Load Immediate 8-bit Data to Destination Register) ............................................................ 149
7.56 LD (Load Word Data in Memory to Register) ................................................................................. 150
7.57 LD (Load Word Data in Memory to Register) ................................................................................. 151
7.58 LD (Load Word Data in Memory to Register) ................................................................................. 152
7.59 LD (Load Word Data in Memory to Register) ................................................................................. 153
7.60 LD (Load Word Data in Memory to Register) ................................................................................. 154
7.61 LD (Load Word Data in Memory to Register) ................................................................................. 155
7.62 LD (Load Word Data in Memory to Program Status Register) ....................................................... 157
7.63 LDUH (Load Half-word Data in Memory to Register) ..................................................................... 159
7.64 LDUH (Load Half-word Data in Memory to Register) ..................................................................... 160
7.65 LDUH (Load Half-word Data in Memory to Register) ..................................................................... 161
7.66 LDUB (Load Byte Data in Memory to Register) .............................................................................. 162
7.67 LDUB (Load Byte Data in Memory to Register) .............................................................................. 163
7.68 LDUB (Load Byte Data in Memory to Register) .............................................................................. 164
7.69 ST (Store Word Data in Register to Memory) ................................................................................. 165
7.70 ST (Store Word Data in Register to Memory) ................................................................................. 166
7.71 ST (Store Word Data in Register to Memory) ................................................................................. 167
7.72 ST (Store Word Data in Register to Memory) ................................................................................. 168
7.73 ST (Store Word Data in Register to Memory) ................................................................................. 169
7.74 ST (Store Word Data in Register to Memory) ................................................................................. 170
7.75 ST (Store Word Data in Program Status Register to Memory) ....................................................... 171
7.76 STH (Store Half-word Data in Register to Memory) ....................................................................... 172
7.77 STH (Store Half-word Data in Register to Memory) ....................................................................... 173
7.78 STH (Store Half-word Data in Register to Memory) ....................................................................... 174
7.79 STB (Store Byte Data in Register to Memory) ................................................................................ 175
7.80 STB (Store Byte Data in Register to Memory) ................................................................................ 176
7.81 STB (Store Byte Data in Register to Memory) ................................................................................ 177
7.82 MOV (Move Word Data in Source Register to Destination Register) ............................................. 178
7.83 MOV (Move Word Data in Source Register to Destination Register) ............................................. 179
7.84 MOV (Move Word Data in Program Status Register to Destination Register) ................................ 180
7.85 MOV (Move Word Data in Source Register to Destination Register) ............................................. 181

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7.86 MOV (Move Word Data in Source Register to Program Status Register) ...................................... 182
7.87 JMP (Jump) .................................................................................................................................... 183
7.88 CALL (Call Subroutine) ................................................................................................................... 184
7.89 CALL (Call Subroutine) ................................................................................................................... 185
7.90 RET (Return from Subroutine) ........................................................................................................ 186
7.91 INT (Software Interrupt) .................................................................................................................. 187
7.92 INTE (Software Interrupt for Emulator) ........................................................................................... 189
7.93 RETI (Return from Interrupt) ........................................................................................................... 191
7.94 Bcc (Branch Relative if Condition Satisfied) ................................................................................... 193
7.95 JMP:D (Jump) ................................................................................................................................. 195
7.96 CALL:D (Call Subroutine) ............................................................................................................... 196
7.97 CALL:D (Call Subroutine) ............................................................................................................... 198
7.98 RET:D (Return from Subroutine) .................................................................................................... 199
7.99 Bcc:D (Branch Relative if Condition Satisfied) ................................................................................ 200
7.100 DMOV (Move Word Data from Direct Address to Register) ........................................................... 202
7.101 DMOV (Move Word Data from Register to Direct Address) ........................................................... 203
7.102 DMOV (Move Word Data from Direct Address to Post Increment Register Indirect Address) ....... 204
7.103 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address) ....... 206
7.104 DMOV (Move Word Data from Direct Address to Pre-decrement Register Indirect Address) ........ 208
7.105 DMOV (Move Word Data from Post Increment Register Indirect Address to Direct Address) ....... 210
7.106 DMOVH (Move Half-word Data from Direct Address to Register) .................................................. 212
7.107 DMOVH (Move Half-word Data from Register to Direct Address) .................................................. 213
7.108 DMOVH (Move Half-word Data from Direct Address to Post Increment Register Indirect Address)
.......................................................................................................................................................... 214
7.109 DMOVH (Move Half-word Data from Post Increment Register Indirect Address to Direct Address)
.......................................................................................................................................................... 216
7.110 DMOVB (Move Byte Data from Direct Address to Register) .......................................................... 218
7.111 DMOVB (Move Byte Data from Register to Direct Address) .......................................................... 219
7.112 DMOVB (Move Byte Data from Direct Address to Post Increment Register Indirect Address) ...... 220
7.113 DMOVB (Move Byte Data from Post Increment Register Indirect Address to Direct Address) ...... 222
7.114 LDRES (Load Word Data in Memory to Resource) ........................................................................ 224
7.115 STRES (Store Word Data in Resource to Memory) ....................................................................... 225
7.116 COPOP (Coprocessor Operation) .................................................................................................. 226
7.117 COPLD (Load 32-bit Data from Register to Coprocessor Register) ............................................... 228
7.118 COPST (Store 32-bit Data from Coprocessor Register to Register) .............................................. 230
7.119 COPSV (Save 32-bit Data from Coprocessor Register to Register) ............................................... 232
7.120 NOP (No Operation) ....................................................................................................................... 234
7.121 ANDCCR (And Condition Code Register and Immediate Data) ..................................................... 235
7.122 ORCCR (Or Condition Code Register and Immediate Data) .......................................................... 236
7.123 STILM (Set Immediate Data to Interrupt Level Mask Register) ...................................................... 237
7.124 ADDSP (Add Stack Pointer and Immediate Data) .......................................................................... 238
7.125 EXTSB (Sign Extend from Byte Data to Word Data) ...................................................................... 239
7.126 EXTUB (Unsign Extend from Byte Data to Word Data) .................................................................. 240
7.127 EXTSH (Sign Extend from Byte Data to Word Data) ...................................................................... 241
7.128 EXTUH (Unsigned Extend from Byte Data to Word Data) .............................................................. 242
7.129 LDM0 (Load Multiple Registers) ..................................................................................................... 243
7.130 LDM1 (Load Multiple Registers) ..................................................................................................... 245
7.131 STM0 (Store Multiple Registers) ..................................................................................................... 247

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7.132 STM1 (Store Multiple Registers) ..................................................................................................... 249
7.133 ENTER (Enter Function) ................................................................................................................. 251
7.134 LEAVE (Leave Function) ................................................................................................................ 253
7.135 XCHB (Exchange Byte Data) .......................................................................................................... 254
APPENDIX ......................................................................................................................... 257
APPENDIX A Instruction Lists .................................................................................................................... 258
A.1 Symbols Used in Instruction Lists .................................................................................................. 259
A.2 Instruction Lists ............................................................................................................................. 261
APPENDIX B Instruction Maps ................................................................................................................... 270
B.1 Instruction Map ............................................................................................................................... 271
B.2 "E" Format ...................................................................................................................................... 272
INDEX................................................................................................................................... 273

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xi
Main changes in this edition
Page Changes (For details, refer to main body.)
4Figure 1.3-1 Sample Configuration of the FR Family CPU is changed.
(The figure is changed.)
62 ■Examples of Programing Delayed Branching Instructions is added.

xii

1
CHAPTER 1
FR FAMILY OVERVIEW
This chapter describes the features of the FR FAMILY
CPU core, and provides sample configurations.
1.1 Features of the FR Family CPU Core
1.2 Sample Configuration of an FR Family Device
1.3 Sample Configuration of the FR Family CPU

2
CHAPTER 1 FR FAMILY OVERVIEW
1.1 Features of the FR Family CPU Core
The FR family CPU core features proprietary Fujitsu architecture and is designed for
controller applications using 32-bit "RISC" based computing. The architecture is
optimized for use in microcontroller CPU cores for built-in control applications where
high-speed control is required.
■Features of the FR Family CPU Core
• General-purpose register architecture
• Linear space for 32-bit (4 Gbyte) addressing
• 16-bit fixed instruction length (excluding immediate data, coprocessor instructions)
• 5-stage pipeline configuration for basic instructions, one-instruction one-cycle execution
• 32-bit by 32-bit computation enables completion of multiplication instructions within five cycles
• Stepwise division instructions enable 32-bit/ 32-bit division
• Direct addressing instructions for peripheral circuit access
• Coprocessor instructions for direct designation of peripheral accelerator
• High speed interrupt processing complete within 6 cycles

3
CHAPTER 1 FR FAMILY OVERVIEW
1.2 Sample Configuration of an FR Family Device
FR family devices have block configuration with bus connections between individual
modules. This enables module connections to be altered as necessary to accommodate
a wide variety of functional configurations.
Figure 1.2-1shows an example of the configuration of an FR family device.
■Sample Configuration of an FR Family Device
Figure 1.2-1 Sample Configuration of an FR Family Device
FR family CPU Low speed
peripherals
Low speed
peripherals
Low speed
peripherals
Low speed
peripherals
Internal bus interface
Integrated bus
User bus interface General-purpose port
Mandatory: Standard in all models
Option: Not included in some models
Peripheral bus
Instruction bus
Instruction cache
Data bus
High speed
peripherals
Data cache
ROM
DMAC
RAM

4
CHAPTER 1 FR FAMILY OVERVIEW
1.3 Sample Configuration of the FR Family CPU
The FR family CPU core features a block configuration organized around general-
purpose registers, with dedicated registers, "ALU" units, multipliers and other features
included for each specific application.
Figure 1.3-1shows a sample configuration of an FR family CPU.
■Sample Configuration of the FR Family CPU
Figure 1.3-1 Sample Configuration of the FR Family CPU
Instruction
data
Instruction
sequencer
Instruction decoder
Bypass
interlock
Wait cancel
control
Exception
processing
Interrupt
NMI
Wait bus
control
Internal bus
Internal bus
Internal bus
Data
Data address
Instruction
address
Multiplier
32 x 8
bits
ALU
Barrel
shifter
Bypass
Register
file
PC
adder
/inc
PC
Pipeline
control