Fujitsu FR Family FR60 Lite User manual

FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
FR60
32-BIT MICROCONTROLLER
MB91301 Series
HARDWARE MANUAL
CM71-10114-4E

FUJITSU LIMITED
FR60
32-BIT MICROCONTROLLER
MB91301 Series
HARDWARE MANUAL
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Be sure to refer to the “Check Sheet” for the latest cautions on development.

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PREFACE
■Objectives and Intended Reader
Thank you for using Fujitsu semiconductor products.
The MB91301 series is a standard microcontroller that has a 32-bit high-performance RISC
CPU as well as built-in I/O resources and bus control mechanisms for embedded controller that
requires high-performance and high-speed CPU processing. Although the MB91301 series
basically uses external bus access to support a vast address space accessed by a 32-bit CPU,
it has a 4 Kbytes instruction cache memory and 4 Kbytes RAM (for data) to increase the speed
at which the CPU executes instructions.
The MB91301 series is most suitable for embedded applications, such as digital video cameras,
navigation systems, and DVD players, that require a high level of CPU processing power.
The MB91301 series is one of the FR60 of microcontrollers, which are based on the FR30/40 of
CPUs. It has enhanced bus access and is optimized for high-speed use.
This manual is intended for engineers who will develop products using the MB91301 series and
describes the functions and operations of the MB91301 series. Read this manual thoroughly.
For more information on instructions, see the "Instructions Manual".
Note: FR, which is an abbreviation of FUJITSU RISC controller, is a product of FUJITSU
LIMITED.
■Trademarks
The company names and brand names herein are the trademarks or registered trademarks of
their respective owners.
■License
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to
use, these components in an I2C system provided that the system conforms to the I2C Standard
Specification as defined by Philips.

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■Structure of This Manual
This manual consists of the following 20 chapters and an appendix.
CHAPTER 1 OVERVIEW
This chapter provides basic information required to understand the MB91301 series, and
covers features, a block diagram, and functions.
CHAPTER 2 HANDLING THE DEVICE
This chapter provides precautions on handling the MB91301 series.
CHAPTER 3 CPU AND CONTROL UNITS
This chapter provides basic information required to understand the functions of the MB91301
series. It covers architecture, specifications, and instructions.
CHAPTER 4 EXTERNAL BUS INTERFACE
The external bus interface controller controls the interfaces with the internal bus for chips
and with external memory and I/O devices.
This chapter explains each function of the external bus interface and its operation.
CHAPTER 5 I/O PORT
This chapter describes the I/O ports and the configuration and functions of registers.
CHAPTER 6 16-BIT RELOAD TIMER
This chapter describes the 16-bit reload timer, the configuration and functions of registers,
and 16-bit reload timer operation.
CHAPTER 7 PPG TIMER
This chapter describes the U-TIMER, the configuration and functions of registers, and U-
TIMER operation.
CHAPTER 8 U-TIMER
This chapter describes the external interrupt and NMI controller, the configuration and
functions of registers, and operation of the external interrupt and NMI controller.
CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER
This chapter describes the functions and operation of the delayed interrupt module.
CHAPTER 10 DELAYED INTERUPT MODULE
This chapter describes the interrupt controller, the configuration and functions of registers,
and interrupt controller operation. It also presents an example of using the hold request
cancellation request function.
CHAPTER 11 INTERRUPT CONTROLLER
This chapter describes the A/D converter, the configuration and functions of registers, and A/
D converter operation.
CHAPTER 12 A/D CONVERTER
This chapter describes the UART, the configuration and functions of registers, and UART
operation.
CHAPTER 13 UART
This chapter describes the I2C interface, the configuration and functions of registers, and I2C
interface operation.

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CHAPTER 14 DMA CONTROLLER (DMAC)
This chapter describes the DMA controller (DMAC), the configuration and functions of
registers, and DMAC operation.
CHAPTER 15 BIT SEARCH MODULE
This chapter describes the bit search module, the configuration and functions of registers,
and bit search module operation.
CHAPTER 16 I2C INTERFACE
This chapter describes the bit search module, the configuration and functions of registers,
and bit search module operation.
CHAPTER 17 16-BIT FREE RUN TIMER
This chapter describes the bit search module, the configuration and functions of registers,
and bit search module operation.
CHAPTER 18 INPUT CAPTURE
This chapter describes the bit search module, the configuration and functions of registers,
and bit search module operation.
CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL
INTEGRATED MODEL))
This chapter describes the bit search module, the configuration and functions of registers,
and bit search module operation.
CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE
This chapter describes the bit search module, the configuration and functions of registers,
and bit search module operation.
APPENDIX
This appendix consists of the following parts: I/O map, interrupt vector, pin states in the CPU
state, notes on using a little endian area, and instruction lists. The appendix contains
detailed information that could not be included in the main text and reference material for
programming.

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Copyright ©2004-2007 FUJITSU LIMITED All rights reserved.
• The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented
solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device;
Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you
develop equipment incorporating the device based on such information, you must assume any responsibility arising
out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of
the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed
as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other
right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party' s intellectual property
right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for general
use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but
are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers
that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to
death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft
flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy,
fire protection, and prevention of over-current levels and other abnormal operating conditions.
• If any products described in this document represent goods or technologies subject to certain restrictions on export
under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will
be required for export of those products from Japan.

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How to Read This Manual
■Terms Used in This Manual
The following defines principal terms used in this manual.
Term Meaning
I-bus 32 bit bus for internal instructions. In the FR family, which is based on an internal
Harvard architecture, independent buses are used for instructions and data. A
bus converter is connected to the I-bus.
D-bus Internal 32-bit data bus. An internal resource is connected to the D-bus.
F-bus Internal instructions and data are multiplexed on a Princeton bus.
The F-bus is connected to the I-bus and D-bus via a switch. The F-bus is
connected to built-in resources such as ROM and RAM.
X-bus External interface bus.
The X-bus is connected to the external interface module.
Data and instructions are multiplexed on an external bus.
R-bus Internal 16-bit data bus. The R-bus is connected to the F-bus via an adapter. An
I-O, clock generator, and interrupt controller are connected to the R-bus.
Since addresses and data are multiplexed on an R-bus that is 16 bits wide, more
than one cycle is required for the CPU to access these resources.
E-unit Execution unit for operations.
CLKP System clock. Clock generated by the clock generator for each of the internal
resources connected to the R-bus. This clock has the same frequency as the
source oscillation at its maximum, but becomes a 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7,
...1/16 (or 1/2, 1/4, 1/6, ...1/32) frequency clock as determined by the divide-by
rate specified by the B3 to B0 bits in the clock generator DIVR0 register.
CLKB System clock. Operating clock for the CPU and each of the other resources
connected to a bus other than the R-bus and X-bus.
This clock has the same frequency as the source oscillation at its maximum, but
becomes a 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, ..., 1/16 (or 1/2, 1/4, 1/6, ..., 1/32)
frequency clock as determined by the divided-by rate specified by the P3 to P0
bits in the clock generator DIVR0 register.
CLKT System clock. Operating clock for the external resources connected to the X-bus.
This clock has the same frequency as the source oscillation at its maximum, but
becomes a 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, ..., 1/16 (or 1/2, 1/4, 1/6, ..., 1/32)
frequency clock as determined by the divided-by rate specified by the T3 to T0
bits in the clock generator DIVR1 register.

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CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................... 1
1.1 Features of the MB91301 Series ........................................................................................................ 2
1.2 Block Diagram .................................................................................................................................... 7
1.3 Package Dimensions .......................................................................................................................... 8
1.4 Pin Layout ......................................................................................................................................... 11
1.5 Pin No. Table .................................................................................................................................... 13
1.6 List of Pin Functions ......................................................................................................................... 15
1.7 I/O Circuit Types ............................................................................................................................... 26
CHAPTER 2 HANDLING THE DEVICE .......................................................................... 31
2.1 Precautions on Handling the Device ................................................................................................. 32
2.2 Precautions on Handling Power Supplies ......................................................................................... 39
CHAPTER 3 CPU AND CONTROL UNITS ..................................................................... 41
3.1 Memory Space .................................................................................................................................. 42
3.2 Internal Architecture .......................................................................................................................... 45
3.3 Instruction Cache .............................................................................................................................. 50
3.3.1 Configuration of the Instruction Cache ........................................................................................ 51
3.3.2 Configuration of the Control Registers ........................................................................................ 54
3.3.3 Instruction Cache Statuses and Settings ..................................................................................... 58
3.3.4 Setting up the Instruction Cache before Use ............................................................................... 60
3.4 Dedicated Registers ......................................................................................................................... 63
3.4.1 Program Status (PS) Register ..................................................................................................... 66
3.5 General-Purpose Registers .............................................................................................................. 70
3.6 Data Structure ................................................................................................................................... 71
3.7 Word Alignment ................................................................................................................................ 72
3.8 Memory Map ..................................................................................................................................... 73
3.9 Branch Instructions ........................................................................................................................... 74
3.9.1 Operation of Branch Instructions with Delay Slot ........................................................................ 75
3.9.2 Operation of Branch Instruction without Delay Slot ..................................................................... 78
3.10 EIT (Exception, Interrupt, and Trap) ................................................................................................. 79
3.10.1 EIT Interrupt Levels ..................................................................................................................... 80
3.10.2 Interrupt Control Register (ICR) ................................................................................................... 82
3.10.3 System Stack Pointer (SSP) ........................................................................................................ 83
3.10.4 Table Base Register (TBR) ......................................................................................................... 84
3.10.5 Multiple EIT Processing ............................................................................................................... 88
3.10.6 EIT Operations ............................................................................................................................ 90
3.11 Reset (Device Initialization) .............................................................................................................. 94
3.11.1 Reset Levels ................................................................................................................................ 95
3.11.2 Reset Sources ............................................................................................................................. 96
3.11.3 Reset Sequence .......................................................................................................................... 98
3.11.4 Oscillation Stabilization Wait Time .............................................................................................. 99
3.11.5 Reset Operation Modes ............................................................................................................. 101

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3.12 Clock Generation Control ............................................................................................................... 103
3.12.1 PLL Controls .............................................................................................................................. 104
3.12.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time .................................................... 105
3.12.3 Clock Distribution ....................................................................................................................... 106
3.12.4 Clock Division ............................................................................................................................ 108
3.12.5 Block Diagram of Clock Generation Controller .......................................................................... 109
3.12.6 Register of Clock Generation Controller .................................................................................... 110
3.12.7 Peripheral Circuits of Clock Controller ....................................................................................... 125
3.12.8 Smooth Startup and Stop of Clock ............................................................................................ 128
3.13 Device State Control ....................................................................................................................... 131
3.13.1 Device States and State Transitions ......................................................................................... 133
3.13.2 Low-power Modes ..................................................................................................................... 136
3.14 Operating Modes ............................................................................................................................ 140
CHAPTER 4 EXTERNAL BUS INTERFACE ................................................................ 143
4.1 Overview of the External Bus Interface .......................................................................................... 144
4.2 External Bus Interface Registers .................................................................................................... 149
4.2.1 Area Select Registers 0 to 7(ASR0 to ASR7) ............................................................................ 150
4.2.2 Area Configuration Registers 0 to 7 (ACR0 to ACR7) ............................................................... 152
4.2.3 Area Wait Register (AWR0 to AWR7) ....................................................................................... 158
4.2.4 Memory setting register (MCRA for SDRAM/FCRAM auto-precharge OFF mode) ................... 167
4.2.5 Memory setting register (MCRB for FCRAM auto-precharge ON mode) .................................. 169
4.2.6 I/O Wait Registers for DMAC (IOWR0, IOWR1) ........................................................................ 170
4.2.7 Chip Select Enable Register (CSER) ........................................................................................ 172
4.2.8 Cache Enable Register (CHER) ................................................................................................ 174
4.2.9 Pin/Timing Control Register (TCR) ............................................................................................ 175
4.2.10 Refresh Control Register (RCR) ................................................................................................ 177
4.3 Setting Example of the Chip Select Area ........................................................................................ 181
4.4 Endian and Bus Access .................................................................................................................. 182
4.4.1 Big Endian Bus Access ............................................................................................................. 184
4.4.2 Little Endian Bus Access ........................................................................................................... 191
4.4.3 Comparison of Big Endian and Little Endian External Access .................................................. 196
4.5 Operation of the Ordinary Bus Interface ......................................................................................... 202
4.5.1 Basic Timing .............................................................................................................................. 203
4.5.2 Operation of WRn + Byte Control Type ..................................................................................... 204
4.5.3 Read -> Write Operation ............................................................................................................ 206
4.5.4 Write -> Write Operation ............................................................................................................ 207
4.5.5 Auto-Wait Cycle ......................................................................................................................... 208
4.5.6 External Wait Cycle ................................................................................................................... 209
4.5.7 Synchronous Write Enable Output ............................................................................................ 210
4.5.8 CSn Delay Setting ..................................................................................................................... 212
4.5.9 CSn -> RD/WRn Setup and RD/WRn -> CSn Hold Setting ....................................................... 213
4.5.10 DMA Fly-By Transfer (I/O -> Memory) ....................................................................................... 214
4.5.11 DMA Fly-By Transfer (Memory -> I/O) ....................................................................................... 215
4.6 Burst Access Operation .................................................................................................................. 216
4.7 Address/data Multiplex Interface .................................................................................................... 218
4.8 Prefetch Operation .......................................................................................................................... 221

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4.9 SDRAM/FCRAM Interface Operation ............................................................................................. 224
4.9.1 Self Refresh ............................................................................................................................... 228
4.9.2 Power-on Sequence .................................................................................................................. 229
4.9.3 Connecting SDRAM/FCRAM to Many Areas ............................................................................ 230
4.9.4 Address Multiplexing Format ..................................................................................................... 231
4.9.5 Memory Connection Example ................................................................................................... 232
4.10 DMA Access Operation .................................................................................................................. 236
4.10.1 DMA Fly-By Transfer (I/O -> Memory) ....................................................................................... 237
4.10.2 DMA Fly-By Transfer (Memory -> I/O) ....................................................................................... 239
4.10.3 DMA Fly-By Transfer (I/O -> SDRAM/FCRAM) ......................................................................... 241
4.10.4 DMA Fly-By Transfer (SDRAM/FCRAM -> I/O) ......................................................................... 243
4.10.5 2-Cycle Transfer (Internal RAM -> External I/O, RAM) ............................................................. 247
4.10.6 2-Cycle Transfer (External -> I/O) ............................................................................................. 248
4.10.7 2-Cycle Transfer (I/O -> External) ............................................................................................. 249
4.10.8 2-Cycle Transfer (I/O -> SDRAM/FCRAM) ................................................................................ 250
4.10.9 2-Cycle Transfer (SDRAM/FCRAM -> I/O) ................................................................................ 251
4.11 Bus Arbitration ................................................................................................................................ 252
4.12 Procedure for Setting a Register .................................................................................................... 254
4.13 Notes on Using the External Bus Interface ..................................................................................... 255
CHAPTER 5 I/O PORT .................................................................................................. 257
5.1 Overview of the I/O Port ................................................................................................................. 258
5.2 I/O Port Registers ........................................................................................................................... 260
CHAPTER 6 16-BIT RELOAD TIMER ........................................................................... 269
6.1 Overview of the 16-bit Reload Timer .............................................................................................. 270
6.2 16-bit Reload Timer Registers ........................................................................................................ 271
6.2.1 Control Status Register (TMCSR) ............................................................................................. 272
6.2.2 16-bit Timer Register (TMR:TMR2 to TMR0) ............................................................................ 275
6.2.3 16-bit Reload Register (TMRLR:TMRLR2 to TMRLR0) ............................................................ 276
6.3 16-bit Reload Timer Operation ....................................................................................................... 277
6.4 Operating States of the Counter ..................................................................................................... 279
6.5 Precautions on Using the 16-bit Reload Timer ............................................................................... 280
CHAPTER 7 PPG TIMER .............................................................................................. 281
7.1 Overview of PPG Timer .................................................................................................................. 282
7.2 Block Diagram of PPG Timer .......................................................................................................... 283
7.3 Registers of PPG Timer .................................................................................................................. 285
7.3.1 Control Status Registers (PCNH:PCNH3 to PCNH0, PCNL:PCNL3 to PCNL0) ....................... 286
7.3.2 PPG Cycle Set Register (PCSR:PCSR3 to PCSR0) ................................................................. 290
7.3.3 PPG Duty Set Register (PDUT:PDUT3 to PDUT0) ................................................................... 291
7.3.4 PPG Timer Register (PTMR:PTMR3 to PTMR0) ....................................................................... 292
7.3.5 General Control Register 10 (GCN10) ...................................................................................... 293
7.3.6 General Control Register 20 (GCN20) ...................................................................................... 296
7.4 PPG Operation ............................................................................................................................... 297
7.5 One-shot Operation ........................................................................................................................ 299
7.6 PPG Timer Interrupt Source and Timing Chart ............................................................................... 301

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7.7 Activating Multiple Channels by Using the General Control Register ............................................. 303
7.8 Notes on Use of the PPG Timer ..................................................................................................... 305
CHAPTER 8 U-TIMER ................................................................................................... 307
8.1 Overview of the U-TIMER ............................................................................................................... 308
8.2 U-TIMER Registers ......................................................................................................................... 309
8.3 U-TIMER Operation ........................................................................................................................ 313
CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER ............................... 315
9.1 Overview of the External Interrupt and NMI Controller ................................................................... 316
9.2 External Interrupt and NMI Controller Registers ............................................................................. 317
9.2.1 Interrupt Enable Register (ENIR) ............................................................................................... 318
9.2.2 External Interrupt Request Register (EIRR) .............................................................................. 319
9.2.3 External Interrupt Request Level Setting Register (ELVR) ........................................................ 320
9.3 Operation of the External Interrupt and NMI Controller .................................................................. 321
CHAPTER 10 DELAYED INTERUPT MODULE ............................................................. 325
10.1 Overview of the Delayed Interrupt Module ..................................................................................... 326
10.2 Delayed Interrupt Module Registers ............................................................................................... 327
10.3 Operation of the Delayed Interrupt Module ..................................................................................... 328
CHAPTER 11 INTERRUPT CONTROLLER ................................................................... 329
11.1 Overview of the Interrupt Controller ................................................................................................ 330
11.2 Interrupt Controller Registers .......................................................................................................... 332
11.2.1 Interrupt Control Register (ICR) ................................................................................................. 334
11.2.2 Hold Request Cancellation Request Level Setting Register (HRCL) ........................................ 336
11.3 Interrupt Controller Operation ......................................................................................................... 337
11.4 Example of Using the Hold Request Cancellation Request Function (HRCR) ............................... 343
CHAPTER 12 A/D CONVERTER .................................................................................... 345
12.1 Overview of the A/D Converter ....................................................................................................... 346
12.2 A/D Converter Registers ................................................................................................................. 348
12.2.1 Control Status Register (ADCS) ................................................................................................ 349
12.2.2 Data Register (ADCR) ............................................................................................................... 354
12.2.3 Conversion result register (ADCR0 to ADCR3) ......................................................................... 355
12.3 A/D Converter Operation ................................................................................................................ 356
12.4 Precautions on the Using A/D Converter ........................................................................................ 358
CHAPTER 13 UART ........................................................................................................ 359
13.1 Overview of the UART .................................................................................................................... 360
13.2 UART Registers .............................................................................................................................. 362
13.2.1 Serial Mode Register (SMR) ...................................................................................................... 363
13.2.2 Serial Control Register (SCR) ................................................................................................... 365
13.2.3 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) ................................... 368
13.2.4 Serial Status Register (SSR) ..................................................................................................... 369
13.3 UART Operation ............................................................................................................................. 373
13.3.1 Asynchronous (Start-stop Synchronization) Mode .................................................................... 374

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13.3.2 CLK Synchronous Mode ............................................................................................................ 375
13.3.3 Occurrence of Interrupts and Timing for Setting Flags .............................................................. 377
13.4 Example of Using the UART ........................................................................................................... 380
13.5 Example of Setting Baud Rates and U-TIMER Reload Values ...................................................... 382
CHAPTER 14 DMA CONTROLLER (DMAC) .................................................................. 383
14.1 Overview of the DMA Controller (DMAC) ....................................................................................... 384
14.2 DMA Controller (DMAC) Registers ................................................................................................. 386
14.2.1 Control/Status Registers A (DMACA0 to DMACA4) .................................................................. 388
14.2.2 Control/Status Registers B (DMACB0 to DMACB4) .................................................................. 393
14.2.3 Transfer Source/Transfer Destination Address Setting Registers
(DMASA0 to DMASA4/DMADA0 to DMADA4) .......................................................................... 400
14.2.4 DMAC All-Channel Control Register (DMACR) ......................................................................... 402
14.2.5 Other Functions ......................................................................................................................... 404
14.3 DMA Controller (DMAC) Operation ................................................................................................ 405
14.3.1 Setting a Transfer Request ........................................................................................................ 408
14.3.2 Transfer Sequence .................................................................................................................... 410
14.3.3 General Aspects of DMA Transfer ............................................................................................. 414
14.3.4 Addressing Mode ....................................................................................................................... 416
14.3.5 Data Types ................................................................................................................................ 417
14.3.6 Transfer Count Control .............................................................................................................. 418
14.3.7 CPU Control .............................................................................................................................. 419
14.3.8 Hold Arbitration .......................................................................................................................... 420
14.3.9 Operation from Starting to End/Stopping ................................................................................... 421
14.3.10 DMAC Interrupt Control ............................................................................................................. 425
14.3.11 Channel Selection and Control .................................................................................................. 426
14.3.12 Supplement on External Pin and Internal Operation Timing ..................................................... 428
14.4 Operation Flowcharts ...................................................................................................................... 432
14.5 Data Bus ......................................................................................................................................... 435
14.6 DMA External Interface ................................................................................................................... 438
14.6.1 Input Timing of the DREQx Pin ................................................................................................. 439
14.6.2 FR30 Compatible Mode of DACK .............................................................................................. 441
CHAPTER 15 BIT SEARCH MODULE ........................................................................... 443
15.1 Overview of the Bit Search Module ................................................................................................ 444
15.2 Bit Search Module Registers .......................................................................................................... 445
15.3 Bit Search Module Operation .......................................................................................................... 447
CHAPTER 16 I2C INTERFACE ....................................................................................... 449
16.1 Overview of the I2C Interface .......................................................................................................... 450
16.2 I2C Interface Registers ................................................................................................................... 451
16.3 Block Diagram of I2C Interface ....................................................................................................... 453
16.4 Detailed on Registers of the I2C Interface ...................................................................................... 454
16.5 I2C Interface Operation ................................................................................................................... 468
16.6 Operation Flowcharts ...................................................................................................................... 473

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CHAPTER 17 16-BIT FREE RUN TIMER ....................................................................... 477
17.1 Overview of 16-bit Free Run Timer ................................................................................................. 478
17.2 Registers of the 16-bit Free Run Timer .......................................................................................... 479
17.3 Block Diagram of the 16-bit Free Run Timer .................................................................................. 480
17.4 Details on Registers of the 16-bit Free Run Timer ......................................................................... 481
17.5 Operation of the 16-bit Free Run Timer .......................................................................................... 485
17.6 Precautions on Using the 16-bit Free Run Timer ........................................................................... 487
CHAPTER 18 INPUT CAPTURE ..................................................................................... 489
18.1 Overview of Input Capture .............................................................................................................. 490
18.2 Input Capture Registers .................................................................................................................. 491
18.3 Block Diagram of Input Capture ...................................................................................................... 492
18.4 Details on Registers of Input Capture ............................................................................................. 493
18.5 Operation of Input Capture ............................................................................................................. 495
CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A
(IPL INTEGRATED MODEL)) .................................................................. 497
19.1 Overview of the Program Loader Mode .......................................................................................... 498
19.2 Setting the Program Loader ............................................................................................................ 499
19.3 Operations in the Program Loader Mode ....................................................................................... 500
19.4 Example of Using the Program Loader Mode to Write to Flash Memory ....................................... 511
CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE .............. 515
20.1 Overview ......................................................................................................................................... 516
20.2 Memory Map ................................................................................................................................... 517
20.3 Specifications for REALOS/FR Embedded in MB91302A-010 ....................................................... 518
20.4 Section Allocation ........................................................................................................................... 520
20.5 Startup Routine ............................................................................................................................... 521
20.6 Initial Settings for SOFTUNE Workbench and REALOS/FR .......................................................... 522
20.7 Mode Pins, Mode Vectors, and Reset Vectors ............................................................................... 530
20.8 Chip Evaluation System .................................................................................................................. 534
APPENDIX ......................................................................................................................... 535
APPENDIX A I/O MAP ............................................................................................................................... 536
APPENDIX B INTERRUPT VECTOR ........................................................................................................ 548
APPENDIX C PIN STATE IN EACH CPU STATE ...................................................................................... 552
APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA .................................................................... 564
D.1 C Compiler (fcc911) ....................................................................................................................... 565
D.2 Assembler (fasm911) ..................................................................................................................... 568
D.3 Linker (flnk911) .............................................................................................................................. 570
D.4 Debugger (sim911, eml911, mon911) ............................................................................................ 571
APPENDIX E INSTRUCTION LISTS ......................................................................................................... 572
E.1 How to Read the Instruction Lists .................................................................................................. 573
E.2 FR Family Instruction Lists ............................................................................................................. 578
INDEX................................................................................................................................... 597

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Main changes in this edition
Page Changes (For details, refer to main body.)
-Part number is deleted.
(MB91301, MB91V301)
2Table is changed in ■Features of the MB91301 Series.
(MB91301 is changed.)
6 MB91301 and MB91V301are deleted in ■Product Line-up is changed.
7 Figure 1.2-1 Block Diagram is changed.
8Summary is changed in 1.3 Package Dimensions. (The MB91301 series is available in one type of package. →The MB91301 series is available in three
types of package.)
12 Figure 1.4-2 Pin Layout of the MB91302A is changed.
(FPT-144P-M08 is added.)
13 Pin Name is changed in Table 1.5-1 MB91V301A Pin No. Table (Package: PGA-179C-A03) (1 / 2).
No.49(LABA →LBA)
17 Pin name and Function are changed in the Pin No. 42 of Table 1.6-1 List of Pin Function (except for Power Supply, and GND Pins) (3 / 10).
(SWR →SWE)
32
■Quartz Oscillation Circuit is changed.
(Added the description; Please ask the crystal maker to evaluate the oscillational characteristics of the
crystal and this device.)
33 ❍Notes on during operation of PLL clock mode is changed.
34
❍Low-power consumption mode is changed.
(Deleted the description; In addition, please set I flag, ILM, and ICR to diverge to the interruption handler
that is the return factor after the standby returns.)
(1) is changed in ❍Low-power consumption mode.
43 Figure 3.1-1 Memory Map is changed.
(Figure is renewed.)
60 ❍Initialization is changed.
(ldi #0x000003C7, r0 →ldi #0x000003E7, r0)
85, 87
Table 3.10-4 Vector Table is changed.
(Instruction break exception →Reserved for system)
(Operand break trap →Reserved for system)
(Deleted the description; * : Reserved for system (MB91301, MB91V301))
97
■Watchdog Reset is changed.
(Unless A5H/5AHis written to the watchdog reset postpone register (WPR) →Unless A5H/5AHis writ-
ten to the timebase counter clear register (CTBR))

xiv
103
■Clock Generation Control is changed.
(The followings sentences are added. The following section describes the generation and control of each
clock. For detailed information about the registers and flags described below, see "3.12.5 Block Diagram
of Clock Generation Controller" and "3.12.6 Register of Clock Generation Controller".
The symbol "φ", which is shown in Table 3.12-4, Table 3.12-9, Table 3.12-13, Table 3.12-16, Table 3.12-
20, Table 3.12-21 and Table 3.12-22, indicates the basic clock that is achieved by dividing the source clock
by two or performing PLL oscillation. Therefore, the system base clock is the clock which is generated
where the above base clock is generated.)
109 Figure 3.12-1 Block Diagram of Clock Generation Controller is changed.
( [Watchdog controller] is changed.)
112 Note is added.
114 Table 3.12-9 Oscillation Stabilization Wait Settings is changed. (CS1 →OS1)
(CS0 →OS0)
116 [bit9] SYNCR (SYNChronous Reset enable) is changed.
117
■Time Base Counter Clear Register (CTBR) is changed.
(The followings sentences are added. The bits are automatically cleared when the CPU is not in operation
in such cases as stop/sleep mode and DMA transfer. Therefore, if the above conditions occur, the watchdog
reset is delayed automatically. However, it will not be delayed, if a request to hold an external bus (BRQ)
has been accepted. For this reason, select the sleep mode before entering a hold request (BRQ), when
intending to hold the external bus for a long period.)
(119) ■Watchdog Reset Postpone Register (WPR) is deleted.
125
[Postponing a watchdog reset] is changed.
(Once the watchdog timer is started, the program must write {A5H} and {5AH} in this order to the watch-
dog reset postpone register (WPR). →Once the watchdog timer is started, the program must write "A5H"
and "5AH" in this order to the time base counter clear register (CTBR).)
136 [Sleep mode transition] is added.
137 ❍Synchronous standby operations is changed.
(❍Normal and synchronous standby operations →❍Synchronous standby operations)
138 ■Stop Mode is changed.
([Stop mode transition] is added.)
141 Table 3.14-1 Mode Settings is changed.
(The description in * is deleted.)
142
Table 3.14-2 Function of internal ROM enable is changed.
(The description in *1 is deleted.)
Table 3.14-3 Settings of the Initial Bus Width is changed.
(Only for MB91302A and MB91V301A is deleted.)
151
■Functions of Bits in the Area Select Registers (ASR0 to ASR7) is changed.
(The area select registers (ASR0 to ASR7) specify the start address of each chip select area (CS0 to CS7).
is added.)
(ASR0 to 7 registers. →ACR0 to ACR7 registers.)
153 Figure 4.2-2 Configuration of Area Configuration Registers 0 to 7 (ACR0 to ACR7) is changed.
(Note is added.)
181
❍Example of setting ASRs and ASZ3 to ASZ0 is changed.
(10000000H→0FFFFFFFH)
(00200000H→001FFFFFH)
Page Changes (For details, refer to main body.)

xv
205
■Operation Timing of the WRn + Byte Control Type is changed.
(•For write access, data output to D31-16 starts at the timing at which WRn is asserted. →•For write
access, data output to D31 to D00 starts at the timing at which WR0 is asserted.)
254 ■Procedure for Setting a Register is changed.
(Added the description; Set ACR after setting ASR if ASR and ACR are accessed by halfword.)
260 ■Configuration of the Port Data Registers (PDR) is changed.
(Note:MB91301 and MB91V301 do not have PFR61 register. is deleted.)
262
Figure 5.2-3 Configuration of the Pull-up Resistor Control Registers (PCR) is changed.
(PCRG and PCRJ are deleted.)
■Configuration of the Pull-up Resistor Control Registers (PCR) is changed.
(PCR0-PCR2, PCR6, PCR8-PCRB, PCRG, PCRH and PCRJ control the pull-up resistor of the corre-
sponding I/O port. →PCR0 to PCR2, PCR6, PCR8 to PCRB, and PCRH control the pull-up resistor of the
corresponding I/O port.)
(Note:MB91302A and MB91V301A do not have PCRG register and PCRJ register. is deleted.)
270 Figure 6.1-1 Block Diagram of the 16-bit Reload Timer is changed.
(16-bit down counter(TMR) UF →16-bit timer register (TMR) UF)
309 Note is added.
313 Note is added.
321
■Operating Procedure for an External Interrupt is changed.
(Added the description; 1) Set the general-purpose I/O port served dual use as the pin for the external inter-
rupt input to input port.)
322
■External Interrupt Request Level is changed.
(Added the description; If the request input level is a level setting, the pulse width must be at least 3
machine cycles. Also, as long as the interrupt input pin retains the active level, the interrupt request is con-
tinuously made to the interrupt controller, even if the source register is cleared.)
323 ■Notes on Returning from STOP State Using External Interrupt is added.
324 ■Return Operation from STOP State is added.
352 Notes is changed in the [bit7, bit6] MD1, MD0 (A/D converter MoDe set).
353
Notes are changed in the [bit2, bit1, bit0]ANE2, ANE1, ANE0 (ANalog End channel set) Setting of A/D
conversion end channel.
(The followings sentences are added. After setting the start channel to the A/D conversion start channel
selection bit (ANS2, ANS1, ANS0), please set neither the A/D conversion mode selection bit (MD1,
MD0) nor the A/D conversion end channel selection bit (ANE2, ANE1, ANE0) by the read-modify-write
type instruction.
The last conversion channel is read from the ANS2, ANS1, ANS0 bits until the A/D conversion operating
starts. Therefore, when the MD1, MD0 bits and ANE2, ANE1, ANE0 bits are set by the read-modify-write
type instruction after setting the start channel to the ANS2, ANS1, ANS0 bits, the value of ANE2, ANE1,
ANE0 bits may be re-written.)
356 ■Single-shot Conversion Mode is changed.
(Note is added.)
358
■Precautions on Using the A/D Converter is changed.
(If STS1 and STS0 are set, set ATG=1 input and reload timer (channel 2)=0 output. →If STS1 and STS0
are set, set ATG=1 input and reload timer (channel 1)=0 output.)
(❍Restart of the A/D conversion is added.)
360 ■Features of the UART is changed.
(Deleted the description; •The DMAC interrupt source is cleared if the DRCL register is written to.)
Page Changes (For details, refer to main body.)

xvi
The vertical lines marked in the left side of the page show the changes.
362 "Figure 13.2-1 Configuration of UART Registers" and "Figure 13.2-2 UART Registers" are changed.
(DRCL is deleted.)
(372) 13.2.5 DRCL Register is deleted.
385 Figure 14.1-1 Block Diagram of the DMA Controller (DMAC) is changed. (DSAD 2-stage register →DMASA 2-stage register)
(DDAD 2-stage register →DMADA 2-stage register)
386 Figure 14.2-1 DMA Controller (DMAC) Registers is changed.
(All-channel control register (DMACR) →DMAC all-channel control register (DMACR))
388 [bit31] DENB (Dma ENaBle): DMA operation enable bit is changed.
(PUAS bit →PAUS bit)
391 Notes is changed in the [bit28 to bit24] IS4 to IS0 (Input Select): Transfer source selection.
394
[bit25] SADM (Source-ADdr. count-Mode select) : Transfer source address count mode specification is
changed.
(make the address count width (SAAZ and DASZ) equal to 0. →make the address count width (SASZ and
DASZ) equal to "0".)
411 ■Demand Transfer 2-Cycle Transfer is changed.
(Select the level with IS[3:0] of DMACA. →Select the level with IS[4:0] of DMACA.)
428 to 430 ■Negate Timing of the DREQ Pin Input when a Demand Transfer Request is Stopped is changed.
453 Figure 16.3-1 Block Diagram of the I2C Interface is changed.
(FNSB →ENSB)
457 [bit12] MSS (Master Slave Select) is changed.
(Note is added.)
468
❍START Condition is changed.
(not (IBCR MSS=1) is deleted.)
Notes is changed.
((DBL=1:IDAR or EN=0:ICCR) →(DBL=1: IDBL or EN=0: ICCR))
503 ❍Main program flowchart is changed.
(* About setting UART0 →* About setting UART1)
511 19.4 Example of Using the Program Loader Mode to Write to Flash Memory is changed.
(■Allocation of Flash Memory is added.)
537, 538, 543 Register DRCL0, DRCL1, DRCL2, WPR in Table A-1 I/O Map is renewed.
547
Table A-1 I/O Map is changed.
(The followings sentence is added. *2: No register in 000420Hand 000423Hin MB91302A and
MB91V301A.)
(The followings sentence is added. *4: Reserved register. Access is disabled.)
548 Table B-1 Interrupt Vectors (1 / 4) is changed. (Instruction break exception →Reserved for system)
(Operand break trap →Reserved for system)
553 to 555 Table C-1 Pin States in External Bus 32-Bit Mode is changed.
Page Changes (For details, refer to main body.)