Fujitsu FR Family FR60 Lite User manual

FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
FR60
32-BIT MICROCONTROLLER
MB91301 Series
HARDWARE MANUAL
CM71-10114-4E

FUJITSU LIMITED
FR60
32-BIT MICROCONTROLLER
MB91301 Series
HARDWARE MANUAL
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.
Be sure to refer to the “Check Sheet” for the latest cautions on development.

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PREFACE
■Objectives and Intended Reader
Thank you for using Fujitsu semiconductor products.
The MB91301 series is a standard microcontroller that has a 32-bit high-performance RISC
CPU as well as built-in I/O resources and bus control mechanisms for embedded controller that
requires high-performance and high-speed CPU processing. Although the MB91301 series
basically uses external bus access to support a vast address space accessed by a 32-bit CPU,
it has a 4 Kbytes instruction cache memory and 4 Kbytes RAM (for data) to increase the speed
at which the CPU executes instructions.
The MB91301 series is most suitable for embedded applications, such as digital video cameras,
navigation systems, and DVD players, that require a high level of CPU processing power.
The MB91301 series is one of the FR60 of microcontrollers, which are based on the FR30/40 of
CPUs. It has enhanced bus access and is optimized for high-speed use.
This manual is intended for engineers who will develop products using the MB91301 series and
describes the functions and operations of the MB91301 series. Read this manual thoroughly.
For more information on instructions, see the "Instructions Manual".
Note: FR, which is an abbreviation of FUJITSU RISC controller, is a product of FUJITSU
LIMITED.
■Trademarks
The company names and brand names herein are the trademarks or registered trademarks of
their respective owners.
■License
Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to
use, these components in an I2C system provided that the system conforms to the I2C Standard
Specification as defined by Philips.

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■Structure of This Manual
This manual consists of the following 20 chapters and an appendix.
CHAPTER 1 OVERVIEW
This chapter provides basic information required to understand the MB91301 series, and
covers features, a block diagram, and functions.
CHAPTER 2 HANDLING THE DEVICE
This chapter provides precautions on handling the MB91301 series.
CHAPTER 3 CPU AND CONTROL UNITS
This chapter provides basic information required to understand the functions of the MB91301
series. It covers architecture, specifications, and instructions.
CHAPTER 4 EXTERNAL BUS INTERFACE
The external bus interface controller controls the interfaces with the internal bus for chips
and with external memory and I/O devices.
This chapter explains each function of the external bus interface and its operation.
CHAPTER 5 I/O PORT
This chapter describes the I/O ports and the configuration and functions of registers.
CHAPTER 6 16-BIT RELOAD TIMER
This chapter describes the 16-bit reload timer, the configuration and functions of registers,
and 16-bit reload timer operation.
CHAPTER 7 PPG TIMER
This chapter describes the U-TIMER, the configuration and functions of registers, and U-
TIMER operation.
CHAPTER 8 U-TIMER
This chapter describes the external interrupt and NMI controller, the configuration and
functions of registers, and operation of the external interrupt and NMI controller.
CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER
This chapter describes the functions and operation of the delayed interrupt module.
CHAPTER 10 DELAYED INTERUPT MODULE
This chapter describes the interrupt controller, the configuration and functions of registers,
and interrupt controller operation. It also presents an example of using the hold request
cancellation request function.
CHAPTER 11 INTERRUPT CONTROLLER
This chapter describes the A/D converter, the configuration and functions of registers, and A/
D converter operation.
CHAPTER 12 A/D CONVERTER
This chapter describes the UART, the configuration and functions of registers, and UART
operation.
CHAPTER 13 UART
This chapter describes the I2C interface, the configuration and functions of registers, and I2C
interface operation.

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CHAPTER 14 DMA CONTROLLER (DMAC)
This chapter describes the DMA controller (DMAC), the configuration and functions of
registers, and DMAC operation.
CHAPTER 15 BIT SEARCH MODULE
This chapter describes the bit search module, the configuration and functions of registers,
and bit search module operation.
CHAPTER 16 I2C INTERFACE
This chapter describes the bit search module, the configuration and functions of registers,
and bit search module operation.
CHAPTER 17 16-BIT FREE RUN TIMER
This chapter describes the bit search module, the configuration and functions of registers,
and bit search module operation.
CHAPTER 18 INPUT CAPTURE
This chapter describes the bit search module, the configuration and functions of registers,
and bit search module operation.
CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL
INTEGRATED MODEL))
This chapter describes the bit search module, the configuration and functions of registers,
and bit search module operation.
CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE
This chapter describes the bit search module, the configuration and functions of registers,
and bit search module operation.
APPENDIX
This appendix consists of the following parts: I/O map, interrupt vector, pin states in the CPU
state, notes on using a little endian area, and instruction lists. The appendix contains
detailed information that could not be included in the main text and reference material for
programming.

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Copyright ©2004-2007 FUJITSU LIMITED All rights reserved.
• The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales representatives before ordering.
• The information, such as descriptions of function and application circuit examples, in this document are presented
solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device;
Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you
develop equipment incorporating the device based on such information, you must assume any responsibility arising
out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of
the information.
• Any information in this document, including descriptions of function and schematic diagrams, shall not be construed
as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other
right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party' s intellectual property
right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result from the use of information contained herein.
• The products described in this document are designed, developed and manufactured as contemplated for general
use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but
are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers
that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to
death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft
flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon
system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in
connection with above-mentioned uses of the products.
• Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy,
fire protection, and prevention of over-current levels and other abnormal operating conditions.
• If any products described in this document represent goods or technologies subject to certain restrictions on export
under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will
be required for export of those products from Japan.

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How to Read This Manual
■Terms Used in This Manual
The following defines principal terms used in this manual.
Term Meaning
I-bus 32 bit bus for internal instructions. In the FR family, which is based on an internal
Harvard architecture, independent buses are used for instructions and data. A
bus converter is connected to the I-bus.
D-bus Internal 32-bit data bus. An internal resource is connected to the D-bus.
F-bus Internal instructions and data are multiplexed on a Princeton bus.
The F-bus is connected to the I-bus and D-bus via a switch. The F-bus is
connected to built-in resources such as ROM and RAM.
X-bus External interface bus.
The X-bus is connected to the external interface module.
Data and instructions are multiplexed on an external bus.
R-bus Internal 16-bit data bus. The R-bus is connected to the F-bus via an adapter. An
I-O, clock generator, and interrupt controller are connected to the R-bus.
Since addresses and data are multiplexed on an R-bus that is 16 bits wide, more
than one cycle is required for the CPU to access these resources.
E-unit Execution unit for operations.
CLKP System clock. Clock generated by the clock generator for each of the internal
resources connected to the R-bus. This clock has the same frequency as the
source oscillation at its maximum, but becomes a 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7,
...1/16 (or 1/2, 1/4, 1/6, ...1/32) frequency clock as determined by the divide-by
rate specified by the B3 to B0 bits in the clock generator DIVR0 register.
CLKB System clock. Operating clock for the CPU and each of the other resources
connected to a bus other than the R-bus and X-bus.
This clock has the same frequency as the source oscillation at its maximum, but
becomes a 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, ..., 1/16 (or 1/2, 1/4, 1/6, ..., 1/32)
frequency clock as determined by the divided-by rate specified by the P3 to P0
bits in the clock generator DIVR0 register.
CLKT System clock. Operating clock for the external resources connected to the X-bus.
This clock has the same frequency as the source oscillation at its maximum, but
becomes a 1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7, ..., 1/16 (or 1/2, 1/4, 1/6, ..., 1/32)
frequency clock as determined by the divided-by rate specified by the T3 to T0
bits in the clock generator DIVR1 register.

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