Fujitsu F2MC-8L MB89620 Series User manual

FUJITSU SEMICONDUCTOR
CONTROLLER MANUAL
F2MC-8L
8-BIT MICROCONTROLLER
MB89620SERIES
HARDWARE MANUAL
CM25-10101-4E

MB89620 series
PREFACE
nObjective and Intended Readership of This Manual
The MB89620 series has been developed as a general-purpose version of the F 2MC*-8L family
consisting of proprietary 8-bit, single-chip microcontrollers. The MB89620 series is applicable to
a wide range of applications from consumer products to industrial equipment, including portable
devices.
This manual describes the functions and operation of the MB89620 series and is aimed at
engineers using the MB89620 series of microcontrollers to develop actual products. See the
F2MCR-8L MB89600 Series Programming Manual for details on the MB89620 instruction set.
*: F2MC stands for FUJITSU Flexible Microcontroller.
nConfiguration of This Manual
This manual consists of the following 14 chapters:
Chapter 1Overview
Provides an overview of the features and functions of the MB89620 series.
Chapter 2Handling Devices
Describes points to note when using the MB89620 series.
Chapter 3CPU
Describes the functions of the MB89620 series CPU.
Chapter 4I/O Ports
Describes the functions and operation of the MB89620 series I/O ports.
Chapter 5Timebase Timer
Describes the functions and operation of the MB89620 series timebase timer.
Chapter 6Watchdog Timer
Describes the functions and operation of the MB89620 series watchdog timer.
Chapter 78-bit PWM Timer
Describes the functions and operation of the MB89620 series 8-bit PWM timer.
Chapter 8Pulse Width Count Timer
Describes the functions and operation of the MB89620 series pulse width count timer.

MB89620 series
Chapter 916-bit Timer/Counter
Describes the functions and operation of the Mb89620 series 16-bit timer/counter.
Chapter 108-bit Serial I/O (Serial I/O-1 and Serial I/O-2)
Describes the functions and operation of the MB89620 series 8-bit serial I/O.
Chapter 11Buzzer Output
Describes the functions and operation of the MB89620 series buzzer output.
Chapter 12External Interrupt Circuit (Edge)
Describes the functions and operation of the MB89620 series external interrupt circuit.
Chapter 13A/D Converter
Describes the functions and operation of the MB89620 series A/D converter.
Chapter 14Clock Monitor Function
Describes the functions and operation of the MB89620 series clock monitor.
The appendixes include the I/O map, mask options, instruction summary, instruction list, and
instruction map.

MB89620 series
© 1996 FUJITSU LIMITED Printed in Japan
1. The products described in this manual and the specifications thereof may be changed without prior
notice. To obtain up-to-date information and/or specifications, contact your Fujitsu sales
representative or Fujitsu authorized dealer.
2. Fujitsu will not be liable for infringement of copyright, industrial property right, or other rights of a third
party caused by the use of information or drawings described in this manual.
3. The contents of this manual may not be transferred or copied without the express permission of
Fujitsu.
4. The products contained in this document are not intended for use with equipments which require
extremely high reliability such as aerospace equipments, undersea repeaters, nuclear control
systems or medical equipments for life support.
5. Some of the products described in this manual may be strategic materials (or special technology) as
defined by the Foreign Exchange and Foreign Trade Control Law. In such cases, the products or
portions thereof must not be exported without permission as defined under the Law.

MB89620 series
READING THIS MANUAL
nPage Layout
In this manual, an entire section is presented on a single page or spread whenever possible.
The reader can thus view a section without having to flip pages.
The content of each section is summarized immediately below the title. You can obtain a rough
overview of this product by reading through these summaries.
Also, higher level section headings are given in lower sections so that you can know to which
section the text you are currently reading belongs.
nFinding information
In addition to the standard table of contents and index, the following methods are available to
find information in a particular section when required.
lRegister index
Information can be looked up in the register index by register name, by bit name, and by their
respective abbreviations.
lSub-heading index
The sub-headings in each section (lines that start with n) are collected together in the sub-
heading index. The sub-heading index provides a means of looking up information at a finer
level of detail than the table of contents.
nNaming Conventions for Register Name and Pin Name
lExamples for description of register name and bit name
By writing “1” to the sleep bit (STBC:SLP) in the standby control register...
Disable the interrupt request output (TBTC:TBIE =“0”) from the timebase timer.
Interrupt is accepted if the interrupt is enabled (CCR:I=“1”).
lNotations for shared pins
P25/SCK pin
The terminal contain the common pins which are programmably switched for different purposes.
The shared pins are described with each function name delimited by “/”.
Bit name Register name abbreviation Bit name abbreviation Register name
Bit name abbreviation
Set data
Register name abbreviation
Register name abbreviation
Bit name abbreviation
Current status

MB89620 series
nSpread Layout and Naming Conventions
Sub-heading
Section summary Section title
Higher level section Table title
Figure title
Chapter title Series title
Check
Points requiring check and prohibited items.
Always read checks.
Note
Provides useful information for reference.
Reference
Indicates an item or
manual that should be referenced.

MB89620 series
nDevelopment Tools and Other Resources Required for Development
The following items are required for developing using the MB89620 series.
Contact FUJITSU sales staff for the required development tools and other resources.
lManuals required for development
Checklist
❑•F2MC-8L MB89620 Series Data Sheet
(Provides electrical characteristics and various characteristic examples for the device.)
❑•F2MC-8L MB89600 Series Programming Manual
(Describes the F2MC-8L series instruction set.)
∗•F2MC-8L MB89600 Series C Compiler Manual
(Only required when developing in C.)
(Describes program development in C and how to run the compiler.)
∗•F2MC-8L MB89600 Series Assembler Manual
(Describes program development in assembly language.)
∗•F2MC-8L MB89600 Series Support System Manual
(Describes how to run the macro assembler, linker, and library manager.)
∗•F2MC-8L MB89600 Series Software Simulator Manual
(Only required when performing evaluation using the simulator.)
(Describes how to operate the software simulator.)
Manuals marked with ∗are provided with the products.
In addition, manuals for products such as development tools are provided with the product.
lSoftware required for development
Checklist
❑•C compiler (Only required when developing in C.)
❑•Assembler, linker, librarian
❑•Software simulator (Only required when performing evaluation using the simulator.)
❑•Emulator/debugger (Only required when performing evaluation using the MB2140A
series.)
The model number for each software package differs depending on the operating system.
See the F2MC development tools catalog or product guide for details.
lItems required for evaluation using one-time PROM or EPROM microcontrollers (when
performing your own PROM or EPROM programming)
Checklist
❑•One of: MB89P625, MB89P627, MB89P629, MB89W625, or MB89W627
❑•ROM programmer (a programmer able to program an MBM27C256A)
See the data sheet for details of recommended programmers.
❑•Package conversion adaptor for writing (available from Sun Hayato Co., Ltd.)
lDevelopment tools
Checklist
❑•MB89PV620 (Piggyback/evaluation device)
❑•Evaluation tools
Check with the supplier when using a third party development environment.
lReference material
•F2MC development tools catalog
•Microcomputer product guide
Package Socket Model
DIP-64P-M01 (1.778 mm pitch)
DIP-64C-A06 (1.778 mm pitch) ROM-64SD-28DP-8L
FPT-64P-M06 (1.00 mm pitch) ROM-64QF-28DP-8L
FPT-64P-M09 (0.65 mm pitch) ROM-64QF2-28DP-8L
(Main unit) (Pod) (Probe)
MB2141A + MB2144-505 For +DIP products : MB21144-201
For +QFP products : MB21144-202




MB89620 series
1
2
3
4
5
6
7
8
9
10
11
12
13
14
APPENDIX
INDEX
OVERVIEW
HANDLING DEVICES
CPU
I/O PORTS
TIMEBASE TIMER
WATCHDOG TIMER
8-BIT PWM TIMER
PULSE WIDTH COUNT TIMER (PWC)
16-BIT TIMER/COUNTER
8-BIT SERIAL I/O(SERIAL I/O-1 AND SERIAL I/O-2)
BUZZER OUTPUT
EXTERNAL INTERRUPT CIRCUIT (EDGE)
A/D CONVERTER
CLOCK MONITOR FUNCTION
APPENDIX
INDEX

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vi MB89620 series

vii MB89620 series
FIGURES
CHAPTER 1 OVERVIEW ....................................................................................................... 1
Figure 1.4 MB89620 Series Block Diagram................................................................................................ 8
Figure 1.5a DIP-64P-M01, DIP-64C-A06, and MDP-64C-P02 Pin Assignment .......................................10
Figure 1.5b FPT-64P-M03 and FPT-64P-M09 Pin Assignment ............................................................... 11
Figure 1.5c FPT-64P-M06 and MQP-64C-P01 Pin Assignment............................................................... 12
Figure 1.6a DIP-64P-M01 Package Dimensions ......................................................................................14
Figure 1.6b DIP-64C-A06 Package Dimensions ...................................................................................... 15
Figure 1.6c FPT-64P-M03 Package Dimensions ..................................................................................... 16
Figure 1.6d FPT-64P-M06 Package Dimensions ..................................................................................... 17
Figure 1.6e FPT-64P-M09 Package Dimensions ..................................................................................... 18
Figure 1.6f MDP-64C-P02 Package Dimensions ..................................................................................... 19
Figure 1.6g MQP-64C-P01 Package Dimensions .................................................................................... 20
CHAPTER 3 CPU ................................................................................................................. 31
Figure 3.1 Memory Map............................................................................................................................ 33
Figure 3.1.2a Storing 16-bit Data in Memory ............................................................................................35
Figure 3.1.2b Byte Order of 16-bit Data in an Instruction ......................................................................... 35
Figure 3.2 Dedicated Register Configuration........................................................................................... 36
Figure 3.2.1a Structure of Condition Code Register .................................................................................38
Figure 3.2.1b Change of Carry Flag by Shift Instruction........................................................................... 38
Figure 3.2.2a Structure of Register Bank Pointer .....................................................................................40
Figure 3.2.2b Rule for Conversion of Actual Addresses of General-Purpose Register Area ................... 40
Figure 3.3 Register Bank Structure .......................................................................................................... 42
Figure 3.4.1 Structure of Interrupt Level Setting Registers....................................................................... 45
Figure 3.4.2 Interrupt Processing ............................................................................................................. 46
Figure 3.4.3 Example of Multiple Interrupts .............................................................................................. 48
Figure 3.4.4 Interrupt Processing Time .................................................................................................... 49
Figure 3.4.5 Stack Operation at Start of Interrupt Processing .................................................................. 50
Figure 3.4.6 Stack Area for Interrupt Processing...................................................................................... 51
Figure 3.5.1 Block Diagram of External Reset Pin ................................................................................... 53
Figure 3.5.2 Reset Operation Flowchart................................................................................................... 54
Figure 3.6 Clock Supply Map.................................................................................................................... 59
Figure 3.6.1a Connection Example for Crystal or Ceramic Resonator ..................................................... 60
Figure 3.6.1b Connection Example for External Clock ............................................................................. 60
Figure 3.6.2 Block Diagram of Clock Controller........................................................................................ 62
Figure 3.6.3 Operation of an Oscillator after Starting Oscillation .............................................................. 64

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MB89620 series
Figure 3.7.3 Standby Control Register (STBC)........................................................................................ 70
Figure 3.7.4a State Transition Diagram for Products with Power-on Reset ............................................ 72
Figure 3.7.4b State Transition Diagram for Products without Power-on Reset ....................................... 72
Figure 3.8 Memory Map in Each Mode.................................................................................................... 77
Figure 3.8.1a Mode Data Structure .......................................................................................................... 78
Figure 3.8.1b Memory Access Selection Operation................................................................................. 79
Figure 3.8.3 External Bus Pin Control Register (BCTR) .......................................................................... 81
Figure 3.8.4a External Bus Operation (Bus Cycle) .................................................................................. 82
Figure 3.8.4b Example of Connecting External Memory and Peripheral Function .................................. 83
Figure 3.8.5a Ready Operation ................................................................................................................ 84
Figure 3.8.5b Ready Signal Generator .................................................................................................... 84
Figure 3.8.5c Ready Signal Generation Timing ....................................................................................... 85
Figure 3.8.6 Hold Operation..................................................................................................................... 86
CHAPTER 4 I/O PORTS ...................................................................................................... 87
Figure 4.2 Block Diagram of Port 0 and 1 Pin (Single-chip Mode) .......................................................... 91
Figure 4.3 Block Diagram of Port 2 Pin (Single-chip Mode) .................................................................... 95
Figure 4.4 Block Diagram of Port 3 Pin.................................................................................................... 99
Figure 4.5 Block Diagram of Port 4 Pin.................................................................................................. 105
Figure 4.6 Block Diagram of Port 5 Pin.................................................................................................. 109
Figure 4.7 Block Diagram of Port 6 Pin.................................................................................................. 112
Figure 4.8 Connection Example for an Eight Segment LED .................................................................. 116
CHAPTER 5 TIMEBASE TIMER ........................................................................................ 117
Figure 5.2 Block Diagram of Timebase Timer ....................................................................................... 119
Figure 5.3 Timebase Timer Control Register (TBTC) ............................................................................ 120
Figure 5.5a Interval Timer Function Settings ......................................................................................... 124
Figure 5.5b Timebase Timer Operation ................................................................................................. 125
Figure 5.6 Effect on Buzzer Output of Clearing Timebase Timer .......................................................... 126
CHAPTER 6 WATCHDOG TIMER ..................................................................................... 129
Figure 6.2 Block Diagram of Watchdog Timer ....................................................................................... 131
Figure 6.3 Watchdog Timer Control Register (WDTC) .......................................................................... 132
Figure 6.4 Watchdog Timer Clear and Interval Time (For a 10 MHz source oscillation) ....................... 133
CHAPTER 7 8-BIT PWM TIMER ....................................................................................... 137
Figure 7.1 Example D/A Converter Configuration Using PWM Output and Low Pass Filter ................. 139
Figure 7.2 Block Diagram of 8-bit PWM Timer ...................................................................................... 140
Figure 7.3a Block Diagram of 8-bit PWM Timer Pin .............................................................................. 142
Figure 7.3b 8-bit PWM Timer Registers................................................................................................. 143
Figure 7.3.1 PWM Control Register (CNTR).......................................................................................... 144
Figure 7.3.2 PWM Compare Register (COMR) ..................................................................................... 146

ix MB89620 series
Figure 7.5a Interval Timer Function Settings ..........................................................................................148
Figure 7.5b Operation of 8-bit PWM Timer............................................................................................. 148
Figure 7.6a PWM Timer Function Settings .............................................................................................149
Figure 7.6b Example of PWM Waveform Output (PTO Pin)................................................................... 149
Figure 7.7a Counter Operation during Standby Modes or Operation Halt
(For Interval Timer Function) ............................................................................................... 150
Figure 7.7b Operation during Standby Modes or Operation Halt (For PWM Timer Function) ................ 151
Figure 7.8 Error on Starting Counter Operation...................................................................................... 152
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) ......................................................... 157
Figure 8.2 Block Diagram of Pulse Width Count Timer .......................................................................... 160
Figure 8.3a Block Diagram of Pulse Width Count Timer Pins ................................................................162
Figure 8.3b Pulse Width Count Timer Registers .................................................................................... 163
Figure 8.3.1 PWC Pulse Width Control Register 1 (PCR1) .................................................................... 164
Figure 8.3.2 PWC Pulse Width Control Register 2 (PCR2) .................................................................... 166
Figure 8.3.3 PWC Reload Buffer Register (RLBR) ................................................................................. 168
Figure 8.5a Interval Timer Function (Reload Timer Mode) Settings .......................................................170
Figure 8.5b Operation in Reload Timer Mode ........................................................................................ 170
Figure 8.5c Interval Timer Function (One-shot Timer Mode) Settings .................................................... 171
Figure 8.5d Operation in One-shot Timer Mode ..................................................................................... 171
Figure 8.6a Pulse Width Measurement Function Settings.......................................................................172
Figure 8.6b Example of “H” Width Measurement Using Pulse Width Measurement Function ............... 172
Figure 8.6c Measuring Long Pulse Widths ............................................................................................. 173
Figure 8.7 Counter Operation during Standby Modes or Operation Halt ................................................ 174
Figure 8.8 Error on Starting Counter Operation...................................................................................... 175
CHAPTER 9 16-BIT TIMER/COUNTER .............................................................................. 179
Figure 9.2 Block Diagram of 16-bit Timer/Counter ................................................................................. 182
Figure 9.3a Block Diagram of 16-bit Timer/Counter Pin .........................................................................184
Figure 9.3b 16-bit Timer/Counter Registers ........................................................................................... 185
Figure 9.3.1 16-bit Timer Control Register (TMCR)................................................................................ 186
Figure 9.3.2 16-bit Timer Count Register (TCR)..................................................................................... 188
Figure 9.5a Interval Timer Function Settings ..........................................................................................190
Figure 9.5b Operation of Interval Timer .................................................................................................. 190
Figure 9.6a Counter Function Settings ...................................................................................................191
Figure 9.6b Operation of 16-bit Counter ................................................................................................. 191
Figure 9.7 Counter Operation during Standby Modes or Operation Halt ................................................ 192
Figure 9.8 Error on Starting Counter Operation...................................................................................... 193
CHAPTER 10 8-BIT SERIAL I/O (SERIAL I/O-1 AND SERIAL I/O-2) ............................... 197
Figure 10.2 Block Diagram of 8-bit Serial I/O ......................................................................................... 200

x
MB89620 series
Figure 10.3a Block Diagram of 8-bit Serial I/O-1 Pins ........................................................................... 203
Figure 10.3b 8-bit Serial I/O-1 Registers ............................................................................................... 203
Figure 10.3.1 Serial 1 Mode Register (SMR1)....................................................................................... 204
Figure 10.3.2 Serial 1 Data Register (SDR1)......................................................................................... 206
Figure 10.4a Block Diagram of 8-bit Serial I/O-2 Pins ........................................................................... 209
Figure 10.4b 8-bit Serial I/O-2 Registers ............................................................................................... 209
Figure 10.4.1 Serial 2 Mode Register (SMR2) ....................................................................................... 210
Figure 10.4.2 Serial 2 Data Register (SDR2)......................................................................................... 212
Figure 10.6a Serial Output Settings (When Using Internal Shift Clock) ................................................. 214
Figure 10.6b Serial Output Settings (When Using External Shift Clock) ............................................... 214
Figure 10.6c 8-bit Serial Output Operation ............................................................................................ 215
Figure 10.7a Serial Input Settings (When Using Internal Shift Clock) ................................................... 216
Figure 10.7b Serial Input Settings (When Using External Shift Clock) .................................................. 216
Figure 10.7c 8-bit Serial Input Operation ............................................................................................... 217
Figure 10.8a Operation in Sleep Mode (Internal Shift Clock) ................................................................ 218
Figure 10.8b Operation in Stop Mode (Internal Shift Clock) .................................................................. 218
Figure 10.8c Operation During Halt (Internal Shift Clock)...................................................................... 218
Figure 10.8d Operation in Sleep Mode (External Shift Clock) ............................................................... 219
Figure 10.8e Operation in Stop Mode (External Shift Clock) ................................................................. 219
Figure 10.8f Operation during Halt (External Shift Clock) ...................................................................... 219
Figure 10.9 Idle State of Shift Clock ...................................................................................................... 220
Figure 10.10a Connection Example for 8-bit Serial I/O (Interface between Two MB89620s) ............... 221
Figure 10.10b Bidirectional Serial I/O Operation ................................................................................... 221
CHAPTER 11 BUZZER OUTPUT ...................................................................................... 225
Figure 11.2 Block Diagram of Buzzer Output ........................................................................................ 227
Figure 11.3a Block Diagram of P44/BZ Pin ........................................................................................... 228
Figure 11.3b Buzzer Output Register .................................................................................................... 228
Figure 11.4 Buzzer Register (BZCR) ..................................................................................................... 229
CHAPTER 12 EXTERNAL INTERRUPT CIRCUIT (EDGE) ............................................... 231
Figure 12.2 Block Diagram of External Interrupt Circuit......................................................................... 233
Figure 12.3a Block Diagram of External Interrupt Circuit Pins ............................................................... 234
Figure 12.3b External Interrupt Circuit Registers ................................................................................... 235
Figure 12.3.1 External Interrupt 1 Control Register (EIC1) .................................................................... 236
Figure 12.3.2 External Interrupt 2 Control Register (EIC2) .................................................................... 238
Figure 12.5a External Interrupt Circuit Settings ..................................................................................... 241
Figure 12.5b External Interrupt (INT1) Operation .................................................................................. 241
CHAPTER 13 A/D CONVERTER ....................................................................................... 243
Figure 13.2 Block Diagram of A/D Converter......................................................................................... 246

xi MB89620 series
Figure 13.3a Block Diagram of P30/ADST Pin .......................................................................................248
Figure 13.3b Block Diagram of P57/AN7 to P50/AN0 Pins .................................................................... 249
Figure 13.3c A/D Converter Registers.................................................................................................... 249
Figure 13.3.1 A/D Control Register 1 (ADC1)......................................................................................... 250
Figure 13.3.2 A/D Control Register 2 (ADC2)......................................................................................... 252
Figure 13.3.3 A/D Data Register (ADCD) ............................................................................................... 254
Figure 13.5a A/D Conversion Function (Software Activation) Settings ..................................................256
Figure 13.5b A/D Conversion Function (Continuous Activation) Settings .............................................. 256
Figure 13.5c Sense Function (Software Activation) Settings.................................................................. 257
Figure 13.5d Sense Function (Continuous Activation) Settings ............................................................. 257
Figure 13.6 Analog Input Equivalent Circuit ........................................................................................... 258
CHAPTER 14 CLOCK MONITOR FUNCTION .................................................................... 263
Figure 14.2 Block Diagram of Clock Monitor Function ........................................................................... 265
Figure 14.3 Block Diagram of P30/ADST/CLKO Pin .............................................................................. 266
Figure 14.4 Clock Output Control Register (CLKE) ................................................................................ 267
APPENDIX ............................................................................................................................ 269
Figure B.1a Direct Addressing................................................................................................................ 274
Figure B.1b Extended Addressing .......................................................................................................... 274
Figure B.1c Bit Direct Addressing........................................................................................................... 274
Figure B.1d Index Addressing ................................................................................................................ 275
Figure B.1e Pointer Addressing.............................................................................................................. 275
Figure B.1f General-Purpose Register Addressing ................................................................................ 275
Figure B.1g Immediate Addressing ........................................................................................................ 275
Figure B.1h Vector Addressing............................................................................................................... 276
Figure B.1i Relative Addressing ............................................................................................................. 276
Figure B.1j Inherent Addressing ............................................................................................................. 276
Figure B.2a JMP @A.............................................................................................................................. 277
Figure B.2b MOVW A, PC ...................................................................................................................... 277
Figure B.2c MULU A............................................................................................................................... 277
Figure B.2d DIVU A ................................................................................................................................ 278
Figure B.2e XCHW A,PC........................................................................................................................ 278
Figure B.2f Example Using XCHW A,PC................................................................................................ 278
Figure B.2g Execution Example of CALLV #3 ........................................................................................ 279
Figure Da Memory Map in EPROM Mode (MB89P625) .........................................................................289
Figure Db Memory Map in EPROM Mode (MB89P627, MB89P629) .....................................................289
Figure Dc Screening Procedure ............................................................................................................. 293
Figure D.2 Memory Map of Piggyback/Evaluation Device ...................................................................... 295

xii
MB89620 series

xvi MB89620 series

xv
MB89620 series
Table 10.3.1 Serial 1 Mode Register (SMR1) Bits .................................................................................. 205
Table 10.4.1 Serial 2 Mode Register (SMR2) Bits .................................................................................. 211
Table 10.5 Register and Vector Table for 8-bit Serial I/O Interrupts ....................................................... 213
CHAPTER 11 BUZZER OUTPUT ...................................................................................... 225
Table 11.1 Output Frequency ................................................................................................................. 226
Table 11.4 Buzzer Register (BZCR) Bits ................................................................................................ 229
CHAPTER 12 EXTERNAL INTERRUPT CIRCUIT (EDGE) ............................................... 231
Table 12.3 External Interrupt Circuit Pins ............................................................................................... 234
Table 12.3.1 External Interrupt Control Register 1 (EIC1) Bits ............................................................... 237
Table 12.3.2 External Interrupt 2 Control Register (EIC2) Bits ............................................................... 239
Table 12.4 Register and Vector Table for External Interrupt Circuit Interrupts ....................................... 240
CHAPTER 13 A/D CONVERTER ....................................................................................... 243
Table 13.3.1 A/D Control Register 1 (ADC1) Bits ................................................................................... 251
Table 13.3.2 A/D Control Register 2 (ADC2) Bits ................................................................................... 253
Table 13.3.3 Example of ADCD Register Setting for Sense Function .................................................... 254
Table 13.4 Register and Vector Table for A/D Converter Interrupt ......................................................... 255
CHAPTER 14 CLOCK MONITOR FUNCTION ................................................................... 263
Table 14.4 Clock Output Control Register (CLKE) Bits .......................................................................... 267
APPENDIX ............................................................................................................................ 269
Table A I/O Map................................................................................................................................ ...... 270
Table Ba Instruction List Symbols .......................................................................................................... 272
Table Bb Instruction List Columns .......................................................................................................... 273
Table B.1 Vector Table Addresses corresponding to “vct” .....................................................................276
Table B.3a Transfer Instructions............................................................................................................. 280
Table B.3b Arithmetic Operation Instructions ......................................................................................... 281
Table B.3c Branch Instructions............................................................................................................... 282
Table B.3d Other Instructions ................................................................................................................. 282
Table B.4 F2MC-8L Instruction Map ........................................................................................................ 283
Table B.5 Bus Operation for Bit Manipulation Instructions .....................................................................284
Table Ca Mask Options .......................................................................................................................... 285
Table Cb Ordering Information ............................................................................................................... 286
Table Da EPROM Programmer Socket Adaptor .................................................................................... 287
Table Db OTPROM Option Bit Map (MB89P625, MB89W625) .............................................................. 290
Table Dc OTPROM Option Bit Map (MB89P627, MB89W627) .............................................................. 291
Table Dd OTPROM Option Bit Map (MB89P629) .................................................................................. 292
Table D.2 Programming Socket Adapter ................................................................................................ 294
Table Ea Pin States in Each Mode (Single-chip Mode) .......................................................................... 295
Table Eb Pin States in Each Mode (External ROM Mode or Internal ROM/External Bus Mode) ........... 296

xiv MB89620 series
Table 4.4.2 Port 3 Pin State................................................................................................................... 103
Table 4.5a Port 4 Pin ............................................................................................................................. 104
Table 4.5b Correspondence between Pin and Register for Port 4 ........................................................ 105
Table 4.5.1 Port 4 Register Function ..................................................................................................... 106
Table 4.5.2 Port 4 Pin State................................................................................................................... 107
Table 4.6a Port 5 Pin ............................................................................................................................. 108
Table 4.6b Correspondence between Pin and Register for Port 5 ........................................................ 109
Table 4.6.1 Port 5 Register Function ..................................................................................................... 110
Table 4.6.2 Port 5 Pin State................................................................................................................... 111
Table 4.7a Port 6 Pin ............................................................................................................................. 112
Table 4.7b Correspondence between Pin and Register for Port 6 ........................................................ 113
Table 4.7.1 Port 6 Register Function ..................................................................................................... 114
Table 4.7.2 Port 6 Pin State................................................................................................................... 115
CHAPTER 5 TIMEBASE TIMER ........................................................................................ 117
Table 5.1a Timebase Timer Interval Time ............................................................................................. 118
Table 5.1b Clock Supplied by Timebase Timer ..................................................................................... 118
Table 5.3 Timebase Timer Control Register (TBTC) Bits ...................................................................... 121
Table 5.4 Register and Vector Table for Timebase Timer Interrupt ....................................................... 122
CHAPTER 6 WATCHDOG TIMER ..................................................................................... 129
Table 6.1 Watchdog Timer Interval Time (for a 10 MHz source oscillation) .......................................... 130
Table 6.3 Watchdog Timer Control Register (WDTC) Bits .................................................................... 132
CHAPTER 7 8-BIT PWM TIMER ....................................................................................... 137
Table 7.1a Interval Time and Square Wave Output Range ................................................................... 138
Table 7.1b Available PWM Wave Cycle for PWM Timer Function ........................................................ 139
Table 7.3.1 PWM Control Register (CNTR) Bits .................................................................................... 145
Table 7.4 Register and Vector Table for 8-bit PWM Timer Interrupt ...................................................... 147
CHAPTER 8 PULSE WIDTH COUNT TIMER (PWC) ........................................................ 157
Table 8.1a Interval Time and Square Wave Output Range ................................................................... 158
Table 8.1b Available Pulse Width Measured by Pulse Width Measurement Function .......................... 159
Table 8.3.1 PWC Pulse Width Control Register 1 (PCR1) Bits ............................................................. 165
Table 8.3.2 PWC Pulse Width Control Register 2 (PCR2) Bits ............................................................. 167
Table 8.4 Register and Vector Table for Pulse Width Count Timer Interrupt ......................................... 169
CHAPTER 9 16-BIT TIMER/COUNTER ............................................................................ 179
Table 9.1a Interval Time Range............................................................................................................. 180
Table 9.3.1 16-bit timer Control Register (TMCR) Bits .......................................................................... 187
Table 9.4 Register and Vector Table for 16-bit Timer/Counter Interrupt ................................................ 189
CHAPTER 10 8-BIT SERIAL I/O (SERIAL I/O-1 AND SERIAL I/O-2) .............................. 197
Table 10.1 Shift Clock Cycle and Transfer Speed ................................................................................. 198