Fujitsu MB90420/5 (A) Series User manual

FUJITSU SEMICONDUCTOR
MICROCONTROLLER
MB90420/5 (A) SERIES
F2MC-16LX FAMILY
16-BIT MICROCONTROLLERS
HARDWARE MANUAL

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MB90420/5 (A) SERIES
F2MC-16LX FAMILY
16-BIT MICROCONTROLLERS
HARDWARE MANUAL
Version/Revision: V1.0
Translation: V1.4 August 2000
©2000 FUJITSU LIMITED Printed in Japan
1. Circuit diagrams utilizing Fujitsu products are included as a mean of illustrating typical
semiconductor applications. Complete information sufficient for construction proposes is
not necessarily given.
2. The information contained in this document has been carefully checked and is believed to
be reliable. However, Fujitsu assumes no responsibility for inaccuracies.
3. The information contained in this document does not convey any license under the copy
right, patent right to trademarks claimed and owned by Fujitsu.
4. Fujitsu reserved the right to change products or specifications without notice.
5. No part of this publication may be copied or reproduced in any form or by any means, or
transferred to any third party without prior written consent of Fujitsu.
6. The products described in this document are not intended for use in equipment requiring
high reliability, such as marine relays and medical life-support systems. For such
applications, contact your Fujitsu sales representative.
7. If the products and technologies described in this document are controlled by the Foreign
Exchange and Foreign Trade Control Act established in Japan, their export is subject to
prior approval based on the said act.

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CONTENTS
Chapter 1 General ................................................................................................................1-1
1.1 Overview of Product.................................................................................................................. 1-3
1.2 Features...................................................................................................................................... 1-4
1.3 Block Diagram............................................................................................................................ 1-6
1.4 Package Dimension................................................................................................................... 1-7
1.5 Pin Assignment.......................................................................................................................... 1-9
1.6 Pin Description......................................................................................................................... 1-11
1.7 I/O Circuits................................................................................................................................ 1-14
1.8 Notes on Handling Devices..................................................................................................... 1-16
Chapter 2 CPU......................................................................................................................2-1
2.1 CPU.............................................................................................................................................. 2-3
2.2 Memory Space............................................................................................................................ 2-4
2.3 Memory Map............................................................................................................................... 2-6
2.4 Addressing ................................................................................................................................. 2-7
2.4.1 Linear Type Addressing................................................................................................. 2-8
2.4.2 Bank Type Addressing................................................................................................... 2-9
2.5 Allocation of Multi-byte Length Data on Memory................................................................. 2-11
2.6 Register..................................................................................................................................... 2-13
2.7 Dedicated Registers ................................................................................................................ 2-14
2.7.1 Accumulator (A)............................................................................................................2-16
2.7.2 Stack Pointer (USP, SSP)............................................................................................. 2-19
2.7.3 Processor Status (PS).................................................................................................. 2-21
2.7.4 Condition Code Register (PS: CCR).......................................................................... 2-22
2.7.5 Register Bank Pointer (PS: RP) ................................................................................. 2-23
2.7.6 Interrupt Level Mask Register (PS: ILM) ................................................................... 2-24
2.7.7 Program Counter (PC).................................................................................................. 2-25
2.7.8 Direct Page Register (DPR) ......................................................................................... 2-26
2.7.9 Bank Register (PCB, DTB, USB, SSB, and ADB) ...................................................... 2-27
2.8 General-purpose Register....................................................................................................... 2-28
2.9 Prefix Codes............................................................................................................................. 2-30
2.9.1 Bank Select Prefix (PCB, DTB, ADB, and SPB)......................................................... 2-31
2.9.2 Common Register Bank Prefix (CMR)........................................................................ 2-32
2.9.3 Flag Change Inhibit Prefix (NCC)................................................................................ 2-33
2.9.4 Restrictions on Prefix Code ........................................................................................ 2-34
Chapter 3 Reset....................................................................................................................3-1
3.1 Overview of Reset...................................................................................................................... 3-3
3.2 Reset Factors and Oscillation Stabilization Wait Time.......................................................... 3-5
3.3 External Reset Pin ..................................................................................................................... 3-7
3.4 Reset Operation ......................................................................................................................... 3-8
3.5 Reset Factor Bit ....................................................................................................................... 3-10
3.6 State of Each Pin at Reset....................................................................................................... 3-12

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Chapter 4 Clock....................................................................................................................4-1
4.1 Overview of Clock.......................................................................................................................4-3
4.2 Block Diagram of Clock Generation Section...........................................................................4-5
4.3 Clock Select Register (CKSCR).................................................................................................4-7
4.4 Clock Mode..................................................................................................................................4-9
4.5 Oscillation Stabilization Wait Time.........................................................................................4-12
4.6 Connection of Oscillator and External Clock ........................................................................4-13
Chapter 5 Low-Power Consumption Mode.........................................................................5-1
5.1 Overview of Low-power Consumption Mode ..........................................................................5-3
5.2 Block Diagram of Low-power Consumption Controller .........................................................5-5
5.3 Low-power Consumption Mode Control Register (LPMCR) ..................................................5-7
5.4 CPU Intermittent Operation Mode...........................................................................................5-10
5.5 Standby Mode...........................................................................................................................5-11
5.5.1 Sleep Mode ....................................................................................................................5-12
5.5.2 Time-base Timer Mode .................................................................................................5-14
5.5.3 Timer Mode ....................................................................................................................5-15
5.5.4 Stop Mode......................................................................................................................5-17
5.6 State Transition Diagram.........................................................................................................5-19
5.7 Pin State in Standby Mode, at Reset ......................................................................................5-21
5.8 Precautions at Using Low-power Consumption Mode.........................................................5-22
Chapter 6 Interrupt...............................................................................................................6-1
6.1 Overview of Interrupt..................................................................................................................6-3
6.2 Interrupt Factor and Interrupt Vector .......................................................................................6-5
6.3 Interrupt Control Registers and Resources.............................................................................6-7
6.3.1 Interrupt Control Register (ICR00 to ICR15).................................................................6-8
6.3.2 Function of Interrupt Control Register........................................................................6-10
6.4 Hardware Interrupt....................................................................................................................6-13
6.4.1 Operation of Hardware Interrupt..................................................................................6-15
6.4.2 Processing at Interrupt Operation...............................................................................6-17
6.4.3 Use Procedure for Hardware Interrupt........................................................................6-18
6.4.4 Multiple Interrupts.........................................................................................................6-19
6.4.5 Hardware Interrupt Handling Time..............................................................................6-20
6.5 Software Interrupt.....................................................................................................................6-21
6.6 EI2OS Interrupt..........................................................................................................................6-23
6.6.1 EI2OS Descriptor (ISD)..................................................................................................6-25
6.6.2 Each Register of EI2OS Descriptor (ISD) ....................................................................6-26
6.6.3 EI2OS Operation ............................................................................................................6-29
6.6.4 Use Procedure for EI2OS..............................................................................................6-30
6.6.5 EI2OS Handling Time.....................................................................................................6-31
6.7 Exception Handling Interrupt ..................................................................................................6-33
6.8 Stack Operation for Interrupt Handling..................................................................................6-34
6.9 Program Example for Interrupt Handling...............................................................................6-36

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Chapter 7 Mode Setting.......................................................................................................7-1
7.1 Mode Setting .............................................................................................................................. 7-3
7.2 Mode Pins (MD2 to MD0)........................................................................................................... 7-4
7.3 Mode Data................................................................................................................................... 7-5
Chapter 8 I/O Port.................................................................................................................8-1
8.1 Overview of I/O Port................................................................................................................... 8-3
8.2 Registers and Assignment of Pins Serving as External Pins............................................... 8-5
8.3 Port 0........................................................................................................................................... 8-6
8.3.1 Registers for Port 0 (PDR0, DDR0) ............................................................................... 8-8
8.3.2 Operation of Port 0......................................................................................................... 8-9
8.4 Port 1......................................................................................................................................... 8-11
8.4.1 Registers for Port 1 (PDR1, DDR1) ............................................................................. 8-13
8.4.2 Operation of Port 1....................................................................................................... 8-14
8.5 Port 3......................................................................................................................................... 8-16
8.5.1 Registers for Port 3 (PDR3, DDR3) ............................................................................. 8-18
8.5.2 Operation of Port 3....................................................................................................... 8-19
8.6 Port 4......................................................................................................................................... 8-21
8.6.1 Registers for Port 4 (PDR4, DDR4) ............................................................................. 8-23
8.6.2 Operation of Port 4....................................................................................................... 8-24
8.7 Port 5......................................................................................................................................... 8-26
8.7.1 Registers for Port 5 (PDR5, DDR5) ............................................................................. 8-28
8.7.2 Operation of Port 5....................................................................................................... 8-29
8.8 Port 6......................................................................................................................................... 8-31
8.8.1 Registers for Port 6 (PDR6, DDR6) ............................................................................. 8-33
8.8.2 Operation of Port 6....................................................................................................... 8-34
8.9 Port 7......................................................................................................................................... 8-36
8.9.1 Registers for Port 7 (PDR7, DDR7) ............................................................................. 8-38
8.9.2 Operation of Port 7....................................................................................................... 8-39
8.10 Port 8..................................................................................................................................... 8-41
8.10.1 Registers for Port 8 (PDR8, DDR8) ............................................................................. 8-43
8.10.2 Operation of Port 8.......................................................................................................8-44
8.11 Port 9..................................................................................................................................... 8-46
8.11.1 Registers for Port 9 (PDR9, DDR9) ............................................................................. 8-48
8.11.2 Operation of Port 9.......................................................................................................8-49
8.12 Program Example Using I/O Ports ..................................................................................... 8-51
Chapter 9 Watchdog Timer/Time-base Timer/Watch Timer (Sub-Clock)..........................9-1
9.1 Overview of Watchdog Timer, Time-base Timer, and Watch Timer ..................................... 9-3
9.2 Block Diagram of Watchdog Timer, Time-base Timer, and Watch Timer............................ 9-4
9.3 List of Watchdog Timer, Time-base Timer, and Watch Timer Registers ............................. 9-5
9.3.1 Watchdog Timer Control Register (WDTC).................................................................. 9-6
9.3.2 Time-base Timer Control Register (TBTC) .................................................................. 9-8
9.3.3 Watch timer control register (WTC).............................................................................. 9-9

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9.4 Operation of Watchdog Timer, Time-base Timer, and Watch Timer...................................9-11
9.4.1 Operation of Watchdog Timer......................................................................................9-12
9.4.2 Operation of Time-base Timer .....................................................................................9-14
9.4.3 Operation of Watch Timer ............................................................................................9-16
9.5 Precautions at Using Watchdog Timer and Time-base Timer .............................................9-17
9.6 Program Examples of Watchdog Timer and Time-base Timer............................................9-19
Chapter 10 16-bit Reload Timer.........................................................................................10-1
10.1 Overview of 16-bit Reload Timer.........................................................................................10-3
10.2 Configuration of 16-bit Reload Timer .................................................................................10-5
10.3 Pins of 16-bit Reload Timer .................................................................................................10-7
10.4 Registers for 16-bit Reload Timer.......................................................................................10-8
10.4.1 Timer Control Status Register (upper) (TMCSR0/1H) ............................................10-9
10.4.2 Timer Control Status Register (lower) (TMCSR0/1L) ...........................................10-11
10.4.3 16-bit Timer Register (TMR0/1)...............................................................................10-13
10.4.4 16-bit Reload Register (TMRLR0/1L, TMRLR0/1H)...............................................10-14
10.5 Interrupt of 16-bit Reload Timer........................................................................................10-15
10.6 Operation of 16-bit Reload Timer......................................................................................10-16
10.6.1 Internal Clock Mode (Reload Mode).......................................................................10-18
10.6.2 Internal Clock Mode (One-shot Mode)...................................................................10-20
10.6.3 Event Count Mode ...................................................................................................10-22
10.7 Precautions at Using 16-bit Reload Timer .......................................................................10-24
10.8 Program Example of 16-bit Reload Timer ........................................................................10-25
Chapter 11 Input Capture ..................................................................................................11-1
11.1 Overview of Input Capture...................................................................................................11-3
11.2 Block Diagram of Input Capture..........................................................................................11-4
11.3 List of Input Capture Registers...........................................................................................11-5
11.3.1 Detailed Explanation of Registers for Input Capture .............................................11-7
11.3.2 Detailed Explanation of Registers for 16-bit Free-run Timer ................................11-9
11.4 Explanation of Operation...................................................................................................11-13
11.4.1 16-bit Input Capture.................................................................................................11-14
11.4.2 16-bit Free-run Timer...............................................................................................11-15
Chapter 12 UART................................................................................................................12-1
12.1 Overview of UART.................................................................................................................12-3
12.2 Configuration of UART.........................................................................................................12-5
12.3 Pin of UART...........................................................................................................................12-8
12.4 Registers for UART...............................................................................................................12-9
12.4.1 Control Register (SCR0/1).......................................................................................12-10
12.4.2 Mode Register (SMR0/1)..........................................................................................12-12
12.4.3 Status Register (SSR0/1).........................................................................................12-14
12.4.4 Input-Data Register (SIDR0/1) and Output-Data Register (SODR0/1).................12-16
12.4.5 Communication Prescaler Control Register (CDCR0/1)......................................12-17

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12.5 Interrupt of UART............................................................................................................... 12-18
12.5.1 Generation of Receive Interrupt and Timing of Flag Set .................................... 12-20
12.5.2 Generation of Transmit Interrupt and Timing of Flag Set................................... 12-21
12.6 Baud Rate of UART............................................................................................................ 12-22
12.6.1 Baud Rate by Dedicated Baud Rate Generator.................................................... 12-24
12.6.2 Baud Rate by Internal Timer (16-bit Reload Timer) ............................................. 12-26
12.6.3 Baud Rate by External Clock................................................................................. 12-27
12.7 Operation of UART............................................................................................................. 12-28
12.7.1 Operation in Asynchronous Mode (Operation Mode 0 or 1)............................... 12-29
12.7.2 Operation in Synchronous Mode (Operation Mode 2) ........................................ 12-31
12.7.3 Bidirectional Communication Function (Normal Mode) ..................................... 12-33
12.7.4 Master/Slave Mode Communication Function (Multiprocessor Mode)............. 12-35
12.8 Precautions at Using UART .............................................................................................. 12-38
12.9 Program Example of UART............................................................................................... 12-39
Chapter 13 PPG Timer .......................................................................................................13-1
13.1 Overview of PPG Timer ....................................................................................................... 13-3
13.2 Block Diagram of PPG Timer.............................................................................................. 13-4
13.3 Registers for PPG Timer...................................................................................................... 13-5
13.3.1 List of PPG Timer Registers..................................................................................... 13-5
13.3.2 Detailed Explanation of Registers for PPG Timer ................................................. 13-6
13.4 Operation of PPG Timer .................................................................................................... 13-10
13.4.1 PWM Operation ....................................................................................................... 13-10
13.4.2 One-shot Operation ................................................................................................ 13-11
13.4.3 Interrupt Factors and Timing................................................................................. 13-12
Chapter 14 LCD Controller/Driver .....................................................................................14-1
14.1 Overview of LCD Controller/Driver..................................................................................... 14-3
14.2 Configuration of LCD Controller/Driver............................................................................. 14-4
14.2.1 Internal Split Resistors of LCD Controller/Driver .................................................. 14-6
14.2.2 External Split Resistors for LCD Controller/Driver................................................ 14-8
14.3 LCD Controller/Driver Pins................................................................................................ 14-10
14.4 LCD Controller/Driver Registers....................................................................................... 14-12
14.4.1 LCDC Control Register Lower (LCRL).................................................................. 14-13
14.4.2 LCDC Control Register Higher (LCRH)................................................................. 14-15
14.5 LCD Controller/Driver Display RAM................................................................................. 14-16
14.6 Explanation of Operation of LCD Controller/Driver........................................................ 14-18
14.6.1 Output Waveform (1/2 duty) during Operation of LCD Controller/Driver.......... 14-19
14.6.2 Output Waveform (1/3 duty) during Operation of LCD Controller/Driver.......... 14-22
14.6.3 Output Waveform (1/4 duty) during Operation of LCD Controller/Driver.......... 14-25

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Chapter 15 Stepping Motor Controller..............................................................................15-1
15.1 Outline of Stepping Motor Controller .................................................................................15-3
15.2 Stepping Motor Controller Registers..................................................................................15-4
15.2.1 PWM Control Register...............................................................................................15-5
15.2.2 PWM1&2 Compare Registers ...................................................................................15-6
15.2.3 PWM 1&2 Select Registers .......................................................................................15-7
15.3 Explanation of Operation of Stepping Motor Controller...................................................15-8
15.4 Precautions at Using Stepping Motor Controller ............................................................15-10
Chapter 16 DTP/External Interrupt Circuit........................................................................16-1
16.1 Overview of DTP/External Interrupt Circuit........................................................................16-3
16.2 Configuration of DTP/External Interrupt Circuit................................................................16-5
16.3 Pins of DTP/External Interrupt Circuit................................................................................16-7
16.4 Registers for DTP/External Interrupt Circuit......................................................................16-8
16.4.1 DTP/Interrupt Factor Register (EIRR) ......................................................................16-8
16.4.2 DTP/Interrupt Enable Register (ENIR)......................................................................16-9
16.4.3 Request Level Setting Register (ELVR).................................................................16-10
16.5 Explanation of DTP/External Interrupt Circuit Operation...............................................16-12
16.5.1 External Interrupt Function.....................................................................................16-14
16.5.2 DTP Function............................................................................................................16-15
16.6 Precautions at Using DTP/External Interrupt Circuit......................................................16-16
16.7 Sample Programs for DTP/External Interrupt Circuit......................................................16-18
Chapter 17 Delayed Interrupt Generate Module...............................................................17-1
17.1 Overview of Delayed Interrupt Generate Module ..............................................................17-3
17.2 Operation of Delayed Interrupt Generate Module .............................................................17-4
Chapter 18 Timepiece Timer..............................................................................................18-1
18.1 Overview of Timepiece Timer..............................................................................................18-3
18.2 Timepiece Timer Registers..................................................................................................18-4
18.2.1 Timepiece Timer Control Register...........................................................................18-6
18.2.2 Sub-second Data Register........................................................................................18-7
18.2.3 Second/Minute/Hour Data Register..........................................................................18-8
Chapter 19 8-/10- bit A/D Converter..................................................................................19-1
19.1 Overview of 8-/10-bit A/D Converter ...................................................................................19-3
19.2 Configuration of 8-/10-bit A/D Converter............................................................................19-4
19.3 Pins of 8-/10-bit A/D Converter............................................................................................19-6
19.4 Registers for 8-/10-bit A/D Converter..................................................................................19-8
19.4.1 A/D Control Status Register Upper (ADCSH)..........................................................19-9
19.4.2 A/D Control Status Register Lower (ADCSL)........................................................19-11
19.4.3 A/D Data Register (ADCRH/ ADCRL) .....................................................................19-13
19.5 Interrupt of 8-/10-bit A/D Converter...................................................................................19-15

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19.6 Explanation of 8-/10-bit A/D Converter Operation.......................................................... 19-16
19.6.1 Conversion Using EI2OS........................................................................................ 19-19
19.6.2 A/D-converted Data Protection Function.............................................................. 19-20
19.7 Precautions at Using 8-/10-bit A/D Converter................................................................. 19-22
19.8 Sample Program 1 for 8-/10-bit A/D Converter (EI2OS Start in Single-shot Mode) ..... 19-23
19.9 Sample Program 2 for 8-/10-bit A/D Converter (EI2OS Start in Continuous Mode)..... 19-25
19.10 Sample Program 3 for 8-/10-bit A/D Converter (EI2OS Start in Stop Mode)................. 19-27
Chapter 20 Sound Generator.............................................................................................20-1
20.1 Overview of Sound Generator ............................................................................................ 20-3
20.2 Sound Generator Registers ................................................................................................ 20-4
20.2.1 Sound Control Register............................................................................................ 20-5
20.2.2 Frequency Data Register.......................................................................................... 20-7
20.2.3 Amplitude Data Register .......................................................................................... 20-8
20.2.4 Decrement Grade Register....................................................................................... 20-9
20.2.5 Tone Count Register................................................................................................. 20-9
Chapter 21 ROM Correction ..............................................................................................21-1
21.1 Overview of ROM Correction.............................................................................................. 21-3
21.2 Application Example of ROM Correction........................................................................... 21-6
21.2.1 Correction Example of Program Errors.................................................................. 21-7
21.2.2 Example of Correction Processing ......................................................................... 21-8
Chapter 22 ROM Mirror Function Select Module..............................................................22-1
22.1 Overview of ROM Mirror Function Select Module ............................................................ 22-3
22.2 ROM Mirror Function Select Register (ROMM)................................................................. 22-4
Chapter 23 Can Controller.................................................................................................23-1
23.1 Features of CAN Controller................................................................................................. 23-3
23.2 Block Diagram of CAN Controller ...................................................................................... 23-4
23.3 List of Overall Control Registers........................................................................................ 23-5
23.4 List of Message Buffers (ID Registers).............................................................................. 23-7
23.5 List of Message Buffers (DLC Registers and Data Registers) ........................................ 23-9
23.6 Classifying CAN Controller Registers ............................................................................. 23-11
23.6.1 Control Status Register (CSR)............................................................................... 23-12
23.6.2 Bus Operation Stop Bit (HALT = 1) ....................................................................... 23-14
23.6.3 Last Event Indicate Register (LEIR) ...................................................................... 23-15
23.6.4 Receive and Transmit Error Counters (RTEC)..................................................... 23-16
23.6.5 Bit Timing Register (BTR) ...................................................................................... 23-17
23.6.6 Message Buffer Valid Register (BVALR) .............................................................. 23-19
23.6.7 IDE register (IDER).................................................................................................. 23-19
23.6.8 Transmission Request Register (TREQR)............................................................ 23-20
23.6.9 Transmission RTR Register (TRTRR)................................................................... 23-20
23.6.10 Remote Frame Receiving Wait Register (RFWTR) .............................................. 23-21

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23.6.11 Transmission Cancel Register (TCANR)...............................................................23-21
23.6.12 Transmission Complete Register (TCR)................................................................23-22
23.6.13 Transmission Interrupt Enable Register (TIER)....................................................23-22
23.6.14 Reception Complete Register (RCR) .....................................................................23-23
23.6.15 Remote Request Receive Register (RRTRR) ........................................................23-23
23.6.16 Receive Overrun Register (ROVRR) ......................................................................23-24
23.6.17 Reception Interrupt Enable Register (RIER) .........................................................23-24
23.6.18 Acceptance Mask Select Register (AMSR) ...........................................................23-25
23.6.19 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) .....................................23-26
23.6.20 Message Buffers......................................................................................................23-27
23.6.21 ID Register x (x = 0 to 15) (IDRx) ............................................................................23-28
23.6.22 DLC Register x (x = 0 to 15) (DLCRx).....................................................................23-29
23.6.23 Data Register x (x = 0 to 15) (DTRx).......................................................................23-30
23.6.24 CAN WAKE UP Control Register (CWUCR) ..........................................................23-31
23.7 Transmission of CAN Controller.......................................................................................23-32
23.8 Reception of CAN Controller.............................................................................................23-34
23.9 Reception Flowchart for CAN Controller..........................................................................23-36
23.10 How to Use CAN Controller ...............................................................................................23-37
23.11 Procedure for Transmission by Message Buffer (x).......................................................23-38
23.12 Procedure for Reception by Message Buffer (x).............................................................23-40
23.13 Setting Configuration of Multi-level Message Buffer......................................................23-41
23.14 CAN WAKE UP Function....................................................................................................23-43
Chapter 24 Low Voltage and CPU Operation Detection Reset Circuit............................24-1
24.1 Overview of Low Voltage and CPU Operation Detection Reset Circuit..........................24-3
24.2 Configuration of Low Voltage and CPU Operation Detection Reset Circuit...................24-4
24.3 Register for Low Voltage and CPU Operation Detection Reset Circuit ..........................24-5
24.4 Operation of Low Voltage and CPU Operation Detection Reset Circuit .........................24-7
24.5 Cautions when Using Low Voltage and CPU Operation Detection Reset Circuit..........24-8
24.6 Sample Program for Low Voltage and CPU Operation Detection Reset Circuit............24-9
Chapter 25 1-Mbit Flash Memory ......................................................................................25-1
25.1 Overview of 1-Mbit Flash Memory.......................................................................................25-3
25.2 Block Diagram for Entire Flash Memory and Flash Memory Sector Configuration ......25-4
25.3 Program/Erase Mode............................................................................................................25-6
25.4 Flash Memory Control Status Register (FMCS).................................................................25-8
25.5 Start Automatic Algorithm of Flash Memory ...................................................................25-10
25.6 Check Execution State of Automatic Algorithm..............................................................25-11
25.6.1 Data Polling Flag (DQ7)...........................................................................................25-12
25.6.2 Toggle Bit Flag (DQ6)..............................................................................................25-13
25.6.3 Timing Limit Exceeding Flag (DQ5) .......................................................................25-14
25.6.4 Sector Erase Timer Flag (DQ3)...............................................................................25-15

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25.7 Details of Programming to and Erasing from Flash Memory........................................ 25-16
25.7.1 Read/reset State in Flash Memory ........................................................................ 25-16
25.7.2 Data Programming to Flash Memory.................................................................... 25-17
25.7.3 All Data Erasing from Flash Memory (Chip Erase).............................................. 25-19
25.7.4 Erasing any Data in Flash Memory (Sector Erase).............................................. 25-19
25.7.5 Sector Erasing Suspention.................................................................................... 25-21
25.7.6 Sector Erasing Resumption................................................................................... 25-21
25.8 Cautions when Using Flash Memory............................................................................... 25-22
25.9 Sample Program for 1-Mbit Flash Memory...................................................................... 25-23
Chapter 26 Examples of MB90F428/A Serial Write Connection......................................26-1
26.1 Basic Configuration of MB90F428/A Serial Write Connection........................................ 26-3
26.2 Example of Serial Write Connection (User Power Supply Used).................................... 26-5
26.3 Example of Serial Write Connection (Power Supplied from the Writer)......................... 26-7
26.4 Example of Minimum Connection to the Flash Microcontroller Programmer
(User Power Supply Used).................................................................................................. 26-9
26.5 Example of Minimum Connection to the Flash Microcontroller Programmer
(Power Supplied from the Writer)..................................................................................... 26-11

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Figures
Fig. 1.1 Block Diagram .................................................................................................................1-6
Fig. 1.2 Package Dimension (QFP100) .......................................................................................1-7
Fig. 1.3 Package Dimension (LQFP100) .....................................................................................1-8
Fig. 1.4 Pin Assignment (QFP100) ..............................................................................................1-9
Fig. 1.5 Pin Assignment (LQFP100)..........................................................................................1-10
Fig. 1.6 Example of using external clock .................................................................................1-17
Fig. 1.7 Power Input Pins (VCC/VSS) ...........................................................................................1-17
Fig. 1.8 Undefined-value Output Timing Chart........................................................................1-18
Fig. 2.1 Example of Relationships between F2MC-16LX System and Memory Map..............2-4
Fig. 2.2 Memory Map ....................................................................................................................2-6
Fig. 2.3 Memory Management in Linear and Bank Types.........................................................2-7
Fig. 2.4 Example of 24-bit Physical Direct Addressing in Linear Types.................................2-8
Fig. 2.5
Example of 32-bit Ggeneral-purpose Register Indirect Specification in Linear Type
........2-8
Fig. 2.6 Example of Bank Type Addressing.............................................................................2-10
Fig. 2.7 Storage of Multi-byte Data in RAM..............................................................................2-11
Fig. 2.8 Storage of Multi-byte Operand.....................................................................................2-11
Fig. 2.9 Storage of Multi-byte Length Data in Stack................................................................2-12
Fig. 2.10 Access to Multi-byte Length Data on Bank Boundary..............................................2-12
Fig. 2.11 Dedicated and General-purpose Registers ................................................................2-13
Fig. 2.12 Configuration of Dedicated Registers.........................................................................2-14
Fig. 2.13 Data Transfer to Accumulator......................................................................................2-16
Fig. 2.14 Example of Transfer between AL and AH of Accumulator (A)
(8-bit immediate value, zero-extended).......................................................................2-17
Fig. 2.15 Example of Transfer between AL and AH of Accumulator (A)
(8-bit immediate value, sign-extended).......................................................................2-17
Fig. 2.16 Example of 32-bit Data Transfer to Accumulator (A) (register indirect)..................2-18
Fig. 2.17 Example of Transfer between AL and AH of Accumulator (A)
(16-bit, register indirect)...............................................................................................2-18
Fig. 2.18 Stack Operation Instructions and Stack Pointers .....................................................2-20
Fig. 2.19 Configuration of Processor Status (PS) .....................................................................2-21
Fig. 2.20 Configuration of Condition Code Register (CCR)......................................................2-22
Fig. 2.21 Configuration of Register Bank Pointer (RP).............................................................2-23
Fig. 2.22 Physical Address Conversion Rules in General-purpose Register Area................2-23
Fig. 2.23 Configuration of Interrupt Level Mask Register (ILM)...............................................2-24
Fig. 2.24 Program Counter (PC) ..................................................................................................2-25
Fig. 2.25 Generation of Physical Address in Direct Page Register (DPR)..............................2-26
Fig. 2.26 Direct Page Register (DPR) Setting and Data Access Example...............................2-26
Fig. 2.27
Allocation and Configuration of General-Purpose Register Banks in Memory Space
....2-28
Fig. 2.28 Interrupt/hold Inhibition................................................................................................2-34
Fig. 2.29 Interrupt/hold Inhibition Instruction and Prefix Code ...............................................2-35
Fig. 2.30 Successive Prefix Codes..............................................................................................2-35

xiv
Fig. 3.1 Oscillation Stabilization Wait Time of Evaluation Products/Flash and
Mask Products at Power-on Reset ............................................................................... 3-5
Fig. 3.2 Oscillation Stabilization Wait Time of Evaluation Products/Flash and
Mask Products at Power-on Reset ............................................................................... 3-6
Fig. 3.3 Block Diagram of Internal Reset................................................................................... 3-7
Fig. 3.4 Block Diagram of External Reset Pin ........................................................................... 3-7
Fig. 3.5 Reset Operation Flow..................................................................................................... 3-8
Fig. 3.6 Transfer of Reset Vectors and Mode Data................................................................... 3-9
Fig. 3.7 Block Diagram of Reset Factor Bit ............................................................................. 3-10
Fig. 3.8 Configuration of Reset Factor Bit (Watchdog Timer Control Register).................. 3-11
Fig. 4.1 Clock Supply Map........................................................................................................... 4-4
Fig. 4.2 Block Diagram of Clock Generation Section............................................................... 4-5
Fig. 4.3 Configuration of Clock Select Register (CKSCR) ....................................................... 4-7
Fig. 4.3 Transition Diagram of Machine Clock Selection State............................................. 4-11
Fig. 4.5 Operation Immediately After Oscillation Started ...................................................... 4-12
Fig. 4.6 Connection of Crystal or Ceramic Oscillator............................................................. 4-13
Fig. 4.7 Connection of External Clock ..................................................................................... 4-13
Fig. 5.1 CPU Operating Mode and Current Consumption........................................................ 5-3
Fig. 5.2 Block Diagram of Low-power Consumption Controller ............................................. 5-5
Fig. 5.3 Configuration of Low-power Consumption Mode Control Register (LPMCR)......... 5-7
Fig. 5.4 Clock in CPU Intermittent Operation Mode ............................................................... 5-10
Fig. 5.5 Cancellation of Sleep Mode by Interrupt.................................................................... 5-13
Fig. 5.6 Cancellation of Timer Mode (External Reset)............................................................ 5-16
Fig. 5.7 Cancellation of Stop Mode (External Reset).............................................................. 5-18
Fig. 5.8 State Transition Diagram............................................................................................. 5-19
Fig. 6.1 General Flow of Interrupt Operation............................................................................. 6-4
Fig. 6.2 Interrupt Control Register (ICR00 to ICR15) at Writing .............................................. 6-8
Fig. 6.3 Interrupt Control Register (ICR00 to ICR15) at Reading............................................. 6-9
Fig. 6.4 Configuration of Interrupt Control Register (ICR)..................................................... 6-10
Fig. 6.5
Hardware Interrupt Request during Writing to the Resource Control Register Area
... 6-14
Fig. 6.6 Operation of Hardware Interrupt................................................................................. 6-16
Fig. 6.7 Flow of Handling Processing...................................................................................... 6-17
Fig. 6.8 Use Procedure for Hardware Interrupt....................................................................... 6-18
Fig. 6.9 Example of Multiple Interrupts.................................................................................... 6-19
Fig. 6.10 Interrupt Processing Time........................................................................................... 6-20
Fig. 6.11 Operation of Software Interrupt.................................................................................. 6-22
Fig. 6.12 Operation of EI2OS....................................................................................................... 6-24
Fig. 6.13 Configuration of EI2OS Descriptor (ISD) ................................................................... 6-25
Fig. 6.14 Configuration of Data Counter (DCT)......................................................................... 6-26
Fig. 6.15 Configuration of I/O Register Address Pointer (IOA) ............................................... 6-26
Fig. 6.16 Configuration of EI2OS Status Register (ISCS) ........................................................ 6-27
Fig. 6.17 Configuration of Buffer Address Pointer (BAP)........................................................ 6-28
Fig. 6.18 Operation Flow of EI2OS ............................................................................................. 6-29

xv
Fig. 6.19 Use Procedure for EI2OS .............................................................................................6-30
Fig. 6.20 Stack Operation at Starting Interrupt Handling .........................................................6-34
Fig. 6.21 Stack Area......................................................................................................................6-35
Fig. 7.1 Classification of Mode....................................................................................................7-3
Fig. 7.2 Configuration of Mode Data...........................................................................................7-5
Fig. 7.3
Relationship between Access Areas and Physical Addresses in Single-chip Mode
.7-6
Fig. 8.1 Block Diagram of Pins of Port 0 ....................................................................................8-7
Fig. 8.2 Block Diagram of Pins of Port 1 ..................................................................................8-12
Fig. 8.3 Block Diagram of Pins of Port 3 ..................................................................................8-17
Fig. 8.4 Block Diagram of Pins of Port 4 ..................................................................................8-22
Fig. 8.5 Block Diagram of Pins of Port 5 ..................................................................................8-27
Fig. 8.6 Block Diagram of Pins of Port 6 ..................................................................................8-32
Fig. 8.7 Block Diagram of Pins of Port 7 ..................................................................................8-37
Fig. 8.8 Block Diagram of Pins of Port 8 ..................................................................................8-42
Fig. 8.9 Block Diagram of Pins of Port 9 ..................................................................................8-47
Fig. 8.10 Eight-segment LED Connection Example ..................................................................8-51
Fig. 9.1 Block Diagram of Watchdog Timer, Time-base Timer, and Watch Timer .................9-4
Fig. 9.2 Watchdog Timer Control Register (WDTC) ..................................................................9-6
Fig. 9.3 Time-base Timer Control Register (TBTC) ...................................................................9-8
Fig. 9.4 Watch Timer Control Register .......................................................................................9-9
Fig. 9.5 Watchdog Timer Operation..........................................................................................9-12
Fig. 9.6 Clearing Timing and Watchdog Timer Interval Time.................................................9-13
Fig. 9.7 Operation of Time-base Timer.....................................................................................9-18
Fig. 10.1 Block Diagram of 16-bit Reload Timer........................................................................10-5
Fig. 10.2 Block Diagram of Pins of 16-bit Reload Timer...........................................................10-7
Fig. 10.3 Registers for 16-bit Reload Timer................................................................................10-8
Fig. 10.4 Timer Control Status Register (upper) (TMCSR0/1H)................................................10-9
Fig. 10.5 Timer Control Status Register (lower) (TMCSR0/1L)...............................................10-11
Fig. 10.6 16-bit Timer Register (TMR0/1)..................................................................................10-13
Fig. 10.7 16-bit Reload Register (TMRLR0/1L, TMRLR0/1H)...................................................10-14
Fig. 10.8 Setting of Internal Clock Mode ..................................................................................10-16
Fig. 10.9 Setting of Event Counter Mode..................................................................................10-16
Fig. 10.10 State Transition Diagram of Counter ........................................................................10-17
Fig. 10.11 Count Operation in Reload Mode (Operation of Software Trigger) .......................10-18
Fig. 10.12 Count Operation in Reload Mode (Operation of External Trigger) ........................10-19
Fig. 10.13
Count Operation in Reload Mode (Operation of Software Trigger and Gate Input)
....10-19
Fig. 10.14 Count Operation in One-shot Mode (Operation of Software Trigger)....................10-20
Fig. 10.15 Count Operation in One-shot Mode (Operation of External Trigger).....................10-21
Fig. 10.16 Count Operation in One-shot Mode (Operation of Software Gate Input)..............10-21
Fig. 10.17 Count Operation in Reload Mode (Operation of Event Count Mode) ....................10-22
Fig. 10.18 Count Operation in One-shot Mode (Operation of Event Count Mode).................10-23

xvi
Fig. 11.1 Block Diagram .............................................................................................................. 11-4
Fig. 11.2 Capture Timing Example for Input Capture ............................................................ 11-14
Fig. 11.3 Capture Timing for Input Signal ............................................................................... 11-14
Fig. 11.4 Clearing Counter by Overflow................................................................................... 11-15
Fig. 11.5 Clearing Counter when Value of 16-bit Free-run Timer Matches
Value of Compare Clear Register ............................................................................. 11-15
Fig. 11.6 Clearing Timing of 16-bit Free-run Timer................................................................. 11-16
Fig. 11.7 Count Timing of 16-bit Free-run Timer..................................................................... 11-16
Fig. 12.1 Block Diagram of UART............................................................................................... 12-6
Fig. 12.2 Block Diagram of Pins of UART.................................................................................. 12-8
Fig. 12.3 List of UART Registers ................................................................................................ 12-9
Fig. 12.4 Control Register (SCR0/1) ......................................................................................... 12-10
Fig. 12.5 Mode Register (SMR0/1) ............................................................................................ 12-12
Fig. 12.6 Status Register (SSR0/1) ........................................................................................... 12-14
Fig. 12.7 Input Data Register (SIDR0/1) ................................................................................... 12-16
Fig. 12.8 Output Data Register (SODR0/1)............................................................................... 12-16
Fig. 12.9 Reception and Timing of Flag Set ............................................................................ 12-20
Fig. 12.10 Transmission and Timing of Flag Set ...................................................................... 12-21
Fig. 12.11 UART Baud Rate Selector.......................................................................................... 12-23
Fig. 12.12 Baud Rate Selector by Internal Timer (16-bit Reload Timer) ................................. 12-26
Fig. 12.13 Baud Rate Selector by External Clock..................................................................... 12-27
Fig. 12.14 Format of Transfer Data (operation mode 0 or 1) ................................................... 12-29
Fig. 12.15 Transmit Data when Parity Enabled ......................................................................... 12-30
Fig. 12.16 Format of Transfer Data (operation mode 2)........................................................... 12-31
Fig. 12.17 Setting of Operation Mode 0 for UART1................................................................... 12-33
Fig. 12.18 Example of Bidirectional Communication Connection for UART1 ....................... 12-33
Fig. 12.19 Example of Bidirectional Communication Flow...................................................... 12-34
Fig. 12.20 Setting of Operation Mode 1 for UART1................................................................... 12-35
Fig. 12.21 Example of Master/Slave Mode Communication Connection for UART............... 12-35
Fig. 12.22 Flowchart of Master/Slave Mode Communications ................................................ 12-37
Fig. 13.1 Block Diagram of PPG Timer ...................................................................................... 13-4
Fig. 13.2 Timing of Disabling PWM Operation Restart .......................................................... 13-10
Fig. 13.3 Timing of Enabling PWM Operation Restart ........................................................... 13-10
Fig. 13.4 Timing of Disabling One-shot Operation Restart.................................................... 13-11
Fig. 13.5 Timing of Enabling One-shot Operation Restart..................................................... 13-11
Fig. 13.6 Interrupt Output Factors and Timing........................................................................ 13-12
Fig. 14.1 Block Diagram for LCD Controller/Driver .................................................................. 14-4
Fig. 14.2 Equivalent Circuit for Internal Split Resistors........................................................... 14-6
Fig. 14.3 State when Internal Split Resistors Used ................................................................. 14-7
Fig. 14.4 Brightness Adjustment when Internal Split Resistors Used ................................... 14-7
Fig. 14.5 External Split Resistor Connection Example ............................................................ 14-8
Fig. 14.6 State when External Split Resistors Used................................................................. 14-9
Fig. 14.7 Block Diagram of Pins Related to LCD Controller/Driver ...................................... 14-11

xvii
Fig. 14.8 Registers Related to LCD Controller/Driver .............................................................14-12
Fig. 14.9 LCDC Control Register Lower (LCRL) ......................................................................14-13
Fig. 14.10 LCDC Control Register Higher (LCRH).....................................................................14-15
Fig. 14.11 Correspondence between Display RAM and Common/Segment Output Pins.....14-16
Fig. 14.12 Setting of LCD Controller/Driver................................................................................14-18
Fig. 14.13 Example of Output Waveform on 1/2 Bias and 1/2 Duty.........................................14-20
Fig. 14.14 Example of LCD Panel Display Data .........................................................................14-21
Fig. 14.15 Example of Output Waveform on 1/3 Bias and 1/3 Duty.........................................14-23
Fig. 14.16 Example of LCD Panel Display Data .........................................................................14-24
Fig. 14.17 Example of Output Waveform on 1/3 Bias and 1/4 Duty.........................................14-26
Fig. 14.18 Example of LCD Panel Display Data .........................................................................14-27
Fig. 15.1 Block Diagram of Stepping Motor Controller.............................................................15-3
Fig. 15.2 Setting Stepping Motor Controller ..............................................................................15-8
Fig. 15.3 Example of PWM 1, 2 Waveform Output.....................................................................15-9
Fig. 16.1 Block Diagram of DTP/External Interrupt Circuit.......................................................16-5
Fig. 16.2 Block Diagram of DTP/External Interrupt Circuit Pin ................................................16-7
Fig. 16.3 Registers for DTP/External Interrupt Circuit ..............................................................16-8
Fig. 16.4 DTP/Interrupt Factor Register (EIRR)..........................................................................16-8
Fig. 16.5 DTP/Interrupt Enable Register (ENIR).........................................................................16-9
Fig. 16.6 Request Level Setting Register (ELVR)....................................................................16-10
Fig. 16.7 DTP/External Interrupt Circuit....................................................................................16-12
Fig. 16.8 Operation of DTP/External Interrupt Circuit.............................................................16-13
Fig. 16.9 Example of Interface with External Peripheral Unit.................................................16-15
Fig. 16.10 Clearing Factor Hold Circuit when Level Set ...........................................................16-16
Fig. 16.11 DTP/External Interrupt Factor and Interrupt Request Issued when
Interrupt Request Output Enabled ............................................................................16-16
Fig. 17.1 Block Diagram of Delayed Interrupt Generate Module .............................................17-3
Fig. 17.2 Operation of Delayed Interrupt Generate Module......................................................17-4
Fig. 18.1 Block Diagram of Timepiece Timer.............................................................................18-3
Fig. 19.1 Block Diagram of 8-/10-bit A/D Converter ..................................................................19-4
Fig. 19.2 Block Diagram of P60/AN0 to P67/AN7 Pins ..............................................................19-7
Fig. 19.3 Registers for 8-/10-bit A/D Converter..........................................................................19-8
Fig. 19.4 A/D Control Status Register Higher (ADCSH)............................................................19-9
Fig. 19.5 A/D Control Status Register Lower (ADCSL) ...........................................................19-11
Fig. 19.6 A/D Data Register (ADCRH/ ADCRL).........................................................................19-13
Fig. 19.7 Setting in Single-shot Conversion Mode..................................................................19-16
Fig. 19.8 Setting in Continuous Conversion Mode .................................................................19-17
Fig. 19.9 Setting in Pause-conversion Mode ...........................................................................19-18
Fig. 19.10 Example of Operation Flow when Using EI2OS........................................................19-19
Fig. 19.11 Flow of Data Protection Function when Using EI2OS..............................................19-21
Fig. 19.12 Flow of EI2OS Start Program (Single-shot Mode)....................................................19-23
Fig. 19.13 Flow Chart of EI2OS Start Program (Continuous Mode) .........................................19-25
Fig. 19.14 Flow Chart of EI2OS Start Program (Stop Mode) .....................................................19-27

xviii
Fig. 20.1 Block Diagram of Sound Generator ........................................................................... 20-3
Fig. 20.2 Relationship between Tone Signal and Register Value ........................................... 20-7
Fig. 20.3 Relationship between Register Value and PWM Pulse ............................................ 20-8
Fig. 21.1 Block Diagram of ROM Correction ............................................................................. 21-3
Fig. 21.2 System Structure Example......................................................................................... 21-6
Fig. 21.3 ROM Correction Processing Flow .............................................................................. 21-7
Fig. 21.4 ROM Correction Processing Flow .............................................................................. 21-8
Fig. 21.5 ROM Correction Processing Flow Diagram............................................................... 21-9
Fig. 22.1 Block Diagram of ROM Mirror Function Select Module ........................................... 22-3
Fig. 22.2 Memory Area................................................................................................................. 22-4
Fig. 23.1 Block Diagram of CAN Controller............................................................................... 23-4
Fig. 23.2 Node Status Transition Diagram............................................................................... 23-13
Fig. 23.3 Bit Time Segment in CAN Specification................................................................... 23-17
Fig. 23.4 Bit Time Segment in CAN Controller........................................................................ 23-17
Fig. 23.5 Transmission Flowchart of the CAN Controller...................................................... 23-33
Fig. 23.6 Flowchart Determining Message Buffer (x) where Receive Messages Stored.... 23-35
Fig. 23.7 Reception Flowchart for the CAN Controller........................................................... 23-36
Fig. 23.8 Example of Receive Interrupt Processing ............................................................... 23-40
Fig. 23.9 Examples of Operation of Multi-level Message Buffer........................................... 23-42
Fig. 24.1 Block Diagram of Detection Reset Circuit for Low Voltage and CPU Operation... 24-4
Fig. 24.2 Low Voltage and CPU Operation Detection Reset Control Register (LVRC)......... 24-5
Fig. 25.1 Block Diagram for Entire Flash Memory.................................................................... 25-4
Fig. 25.2 Sector Configuration of 1-Mbit Flash Memory .......................................................... 25-5
Fig. 25.3 Example of Data Programming Procedure.............................................................. 25-18
Fig. 25.4 Example of Sector Erasing Procedure..................................................................... 25-20
Fig. 26.1 Example of Serial Write Connection for MB90F428/A
(User Power Supply Used)........................................................................................... 26-5
Fig. 26.2 Example of Serial Write Connection for MB90F428/A
(Power Supplied from the Writer) ............................................................................... 26-7
Fig. 26.3 Example of Minimum Connection to the Flash Microcontroller Programmer
(User Power Supply Used)........................................................................................... 26-9
Fig. 26.4 Example of Minimum Connection to the Flash Microcontroller Programmer
(Power Supplied from the Writer) ............................................................................. 26-11

xix
Tables
Table 1-1 Overview of MB90420/5 (A) Series.............................................................................1-3
Table 1-2 Features of MB90420/5 (A) Series..............................................................................1-4
Table 1-3 Pin Description..........................................................................................................1-11
Table 1-4 I/O Circuits .................................................................................................................1-14
Table 2-1 Access Space for Each Bank Register and Major Use of Access Space..............2-9
Table 2-2 Addressing and Default Spaces ..............................................................................2-10
Table 2-3 Initial Values of Dedicated Registers ......................................................................2-15
Table 2-4 Stack Address Specification....................................................................................2-19
Table 2-5 Interrupt Level Mask Register (ILM) and Interrupt Level (high/low).....................2-24
Table 2-6 Typical Function of the General-Purpose Register ...............................................2-29
Table 2-7 Bank Select Prefix.....................................................................................................2-31
Table 2-8 Instructions Unaffected by Bank Select Prefix ......................................................2-31
Table 2-9 Instructions Requiring Care When Using Bank Select Prefix ..............................2-32
Table 2-10 Instructions Requiring Care When Using Bank Select Prefix (CMR)...................2-32
Table 2-11 Instructions Requiring Care When Using Flag Change Inhibit Prefix (NCC)......2-33
Table 2-12 Prefix Code and Interrupt/hold Inhibit Instruction.................................................2-34
Table 3-1 Reset Factor.................................................................................................................3-3
Table 3-2 Reset Factors and Oscillation Stabilization Wait Times .........................................3-5
Table 3-3 Oscillation Stabilization Wait Time Based on Setting of
Clock Selection Register (CKSCR)............................................................................3-6
Table 3-4 Correspondence of Reset Factor Bit Value and Reset Factor..............................3-11
Table 4-1 Function of Each Bit of Clock Select Register (CKSCR).........................................4-8
Table 5-1
Function of Each Bit of Low-power Consumption Mode Control Register (LPMCR)
..5-8
Table 5-2 Instructions At Transition To Low-power Consumption Mode ..............................5-9
Table 5-3 Operating State in Standby Mode............................................................................5-11
Table 5-4 Operation State in Low-power Consumption Mode...............................................5-20
Table 5-5 Each Pin State in Single Chip Mode........................................................................5-21
Table 6-1 Interrupt Vectors..........................................................................................................6-5
Table 6-2 Interrupt Source, Interrupt Vector, and Interrupt Control Register........................6-6
Table 6-3 Interrupt Control Register List...................................................................................6-7
Table 6-4 Relationship between Interrupt Level Setting Bits and Interrupt Levels.............6-11
Table 6-5 Correspondence between EI2OS Channel Select Bits and Descriptor Addresses6-12
Table 6-6 Relationships between EI2OS Status Bits and EI2OS Status...............................6-12
Table 6-7 Mechanism Related to Hardware Interrupt.............................................................6-13
Table 6-8 Hardware Interrupt Inhibit Instructions...................................................................6-14
Table 6-9 compensation Value (Z) of Interrupt Handling Time..............................................6-20
Table 6-10 Correspondence between Channel Number and Descriptor Address ................6-25
Table 6-11 EI2OS Executing Time ..............................................................................................6-31
Table 6-12 Compensation Value for Data Transfer at EI2OS Executing Time.......................6-31
Table 6-13 Compensation Value (Z) for Interrupt Handling Time............................................6-32
Table 7-1 Setting of Mode Pins...................................................................................................7-4
Table 7-2 Bus Mode Setting Bits and Functions.......................................................................7-5
Table 7-3 Relationships between Mode Pins and Mode Data..................................................7-6

xx
Table 8-1 List of Each Port Functions....................................................................................... 8-4
Table 8-2 Registers for Each Port.............................................................................................. 8-5
Table 8-3 Pins of Port 0............................................................................................................... 8-6
Table 8-4 Correspondence between Registers and Pins for Port 0....................................... 8-7
Table 8-5 Function of Registers for Port 0................................................................................ 8-8
Table 8-6 State of Port 0 Pins...................................................................................................8-10
Table 8-7 Pins of Port 1............................................................................................................. 8-11
Table 8-8 Correspondence between Registers and Pins for Port 1..................................... 8-12
Table 8-9 Function of Registers for Port 1.............................................................................. 8-13
Table 8-10 State of Port 1 Pins................................................................................................... 8-15
Table 8-11 Pins of Port 3............................................................................................................. 8-16
Table 8-12 Correspondence between Registers and Pins for Port 3..................................... 8-17
Table 8-13 Function of Registers for Port 3.............................................................................. 8-18
Table 8-14 State of Port 3 Pins................................................................................................... 8-20
Table 8-15 Pins of Port 4............................................................................................................. 8-21
Table 8-16 Correspondence between Registers and Pins for Port 4..................................... 8-22
Table 8-17 Function of Registers for Port 4.............................................................................. 8-23
Table 8-18 State of Port 4 Pins................................................................................................... 8-25
Table 8-19 Pins of Port 5............................................................................................................. 8-26
Table 8-20 Correspondence between Registers and Pins for Port 5..................................... 8-27
Table 8-21 Function of Registers for Port 5.............................................................................. 8-28
Table 8-22 State of Port 5 Pins................................................................................................... 8-30
Table 8-23 Pins of Port 6............................................................................................................. 8-31
Table 8-24 Correspondence between Registers and Pins for Port 6..................................... 8-32
Table 8-25 Function of Registers for Port 6.............................................................................. 8-33
Table 8-26 State of Port 6 Pins................................................................................................... 8-35
Table 8-27 Pins of Port 7............................................................................................................. 8-36
Table 8-28 Correspondence between Registers and Pins for Port 7..................................... 8-37
Table 8-29 Function of Registers for Port 7.............................................................................. 8-38
Table 8-30 State of Port 7 Pins................................................................................................... 8-40
Table 8-31 Pins of Port 8............................................................................................................. 8-41
Table 8-32 Correspondence between Registers and Pins for Port 8..................................... 8-42
Table 8-33 Function of Registers for Port 8.............................................................................. 8-43
Table 8-34 State of Port 8 Pins................................................................................................... 8-45
Table 8-35 Pins of Port 9............................................................................................................. 8-46
Table 8-36 Correspondence between Registers and Pins for Port 9..................................... 8-47
Table 8-37 Function of Registers for Port 9.............................................................................. 8-48
Table 8-38 State of Port 9 Pins................................................................................................... 8-50
Table 9-1 PONR, STBR, WRST, ERST, SRST (Reset Factor Bits) .......................................... 9-6
Table 9-2 WT1 and 0 (Interval Time Select Bits)....................................................................... 9-7
Table 9-3 Interval Time and Cycle Count TBC1 and 0............................................................. 9-8
Table 9-4 Selection of Watch Timer Interval........................................................................... 9-10
Table 9-5 Time-base Timer Interrupt and EI2OS..................................................................... 9-15