GE P24DM User manual

GE
Grid Solutions
MiCOM P40 Agile
P24DM, P24NM
Technical Manual
Motor Protection IED
Hardware Version: A
Software Version: 62
Publication Reference: P24xM-TM-EN-2.1

Contents
Chapter 1 Introduction 1
1 Chapter Overview 3
2 Foreword 4
2.1 Target Audience 4
2.2 Typographical Conventions 4
2.3 Nomenclature 5
2.4 Compliance 5
3 Product Scope 6
3.1 Ordering Options 6
4 Features and Functions 7
4.1 Protection Functions 7
4.2 Control Functions 8
4.3 Measurement Functions 8
4.4 Communication Functions 9
5 Logic Diagrams 10
6 Functional Overview 12
Chapter 2 Safety Information 13
1 Chapter Overview 15
2 Health and Safety 16
3 Symbols 17
4 Installation, Commissioning and Servicing 18
4.1 Lifting Hazards 18
4.2 Electrical Hazards 18
4.3 UL/CSA/CUL Requirements 19
4.4 Fusing Requirements 19
4.5 Equipment Connections 20
4.6 Protection Class 1 Equipment Requirements 20
4.7 Pre-energisation Checklist 21
4.8 Peripheral Circuitry 21
4.9 Upgrading/Servicing 23
5 Decommissioning and Disposal 24
6 Regulatory Compliance 25
6.1 EMC Compliance: 2014/30/EU 25
6.2 LVD Compliance: 2014/35/EU 25
6.3 R&TTE Compliance: 2014/53/EU 25
6.4 UL/CUL Compliance 25
6.5 ATEX Compliance: 2014/34/EU 25
Chapter 3 Hardware Design 27
1 Chapter Overview 29
2 Hardware Architecture 30
2.1 Memory and Real Time Clock 30
3 Mechanical Implementation 32
3.1 Housing Variants 32
3.2 20TE Rear Panel 33
3.3 30TE Rear Panel 33
3.4 40TE Rear Panel 35
4 Terminal Connections 36
4.1 I/O Options 36
5 Front Panel 37

5.1 20TE Front Panel 37
5.2 30TE Front Panel 38
5.3 40TE Front Panel 39
5.4 Keypad 39
5.5 Liquid Crystal Display 40
5.6 USB Port 40
5.7 Fixed Function LEDs 41
5.8 Function Keys 41
5.9 Programable LEDs 41
Chapter 4 Software Design 43
1 Chapter Overview 45
2 Software Design Overview 46
3 System Level Software 47
3.1 Real Time Operating System 47
3.2 System Services Software 47
3.3 Self-Diagnostic Software 47
3.4 Startup Self-Testing 47
3.4.1 System Boot 47
3.4.2 System Level Software Initialisation 48
3.4.3 Platform Software Initialisation and Monitoring 48
3.5 Continuous Self-Testing 48
4 Platform Software 49
4.1 Record Logging 49
4.2 Settings Database 49
4.3 Interfaces 49
5 Protection and Control Functions 50
5.1 Acquisition of Samples 50
5.2 Frequency Tracking 50
5.3 Fourier Signal Processing 50
5.4 Programmable Scheme Logic 51
5.5 Event Recording 51
5.6 Disturbance Recorder 52
5.7 Function Key Interface 52
Chapter 5 Configuration 53
1 Chapter Overview 55
2 Settings Application Software 56
3 Using the HMI Panel 57
3.1 Navigating the HMI Panel 58
3.2 Getting Started 58
3.3 Default Display 59
3.4 Default Display Navigation 60
3.5 Password Entry 61
3.6 Processing Alarms and Records 62
3.7 Menu Structure 62
3.8 Changing the Settings 63
3.9 Direct Access (The Hotkey menu) 64
3.9.1 Setting Group Selection Using Hotkeys 64
3.9.2 Control Inputs 65
3.9.3 Circuit Breaker Control 65
3.10 Function Keys 66
4 Date and Time Configuration 68
4.1 Time Zone Compensation 68
4.2 Daylight Saving Time Compensation 68
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5 Settings Group Selection 69
Chapter 6 Current Protection Functions 71
1 Chapter Overview 73
2 Thermal Overload Protection 74
2.1 Thermal Overload Protection 74
2.2 Thermal Replica 75
2.3 Thermal Trip 76
2.4 User programmable curve for thermal overload protection 78
2.5 Application Notes 78
2.5.1 Thermal Overload Setting Guidelines 78
3 Overcurrent Protection Principles 84
3.1 IDMT Characteristics 84
3.1.1 IEC 60255 IDMT Curves 85
3.1.2 European Standards 87
3.1.3 North American Standards 88
3.1.4 IEC and IEEE Inverse Curves 90
3.1.5 Differences Between the North american and European Standards 91
3.1.6 Programmable Curves 91
3.2 Principles of Implementation 91
3.2.1 Timer Hold Facility 92
4 Phase Overcurrent Protection 94
4.1 Phase Overcurrent Protection Implementation 94
4.2 Non-Directional Overcurrent Logic 95
4.3 Directional Element 96
4.3.1 Directional Overcurrent Logic 98
4.4 Application Notes 98
4.4.1 Short Circuit Protection 98
5 Current Setting Threshold Selection 101
6 Negative Sequence Overcurrent Protection 102
6.1 Negative Sequence Overcurrent Protection Implementation 102
6.2 Non-Directional Negative Sequence Overcurrent Logic 103
6.3 Directional Element 103
6.3.1 Directional Negative Sequence Overcurrent Logic 104
6.4 Phase Rotation 104
6.5 Application Notes 105
6.5.1 Negative Sequence Protection 105
7 Earth Fault Protection 109
7.1 Earth Fault Protection Elements 109
7.2 Non-directional Earth Fault Logic 110
7.3 IDG Curve 110
7.4 Directional Element 111
7.4.1 Residual Voltage Polarisation 111
7.4.2 Negative Sequence Polarisation 113
7.5 Application Notes 114
7.5.1 Setting Guidelines (Directional Element) 114
7.5.2 Peterson Coil Earthed Systems 115
7.5.3 Setting Guidelines (Compensated networks) 118
7.5.4 Solidly Earthed System 119
7.5.5 Insulated System 120
7.5.6 Resistance Earthed Systems 123
7.5.7 High Resistance Earthing 123
7.5.8 Petersen coil earthed systems 124
7.5.9 Operation of sensitive earth fault element 129
8 Sensitive Earth Fault Protection 130
8.1 SEF Protection Implementation 130
8.2 Non-directional SEF Logic 130
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8.3 EPATR B Curve 131
8.4 Directional Element 131
8.4.1 Wattmetric Characteristic 132
8.4.2 Icos phi / Isin phi characteristic 133
8.4.3 Directional SEF Logic 134
8.5 Application Notes 135
8.5.1 Insulated Systems 135
8.5.2 Setting Guidelines (Insulated Systems) 136
9 Cold Load Pickup 138
9.1 Implementation 138
9.2 CLP Logic 139
9.3 Application Notes 139
9.3.1 CLP for Resistive Loads 139
9.3.2 CLP for Motor Feeders 139
9.3.3 CLP for Switch Onto Fault Conditions 140
10 Selective Logic 141
10.1 Selective Logic Implementation 141
10.2 Selective Logic Diagram 141
11 Timer Setting Selection 142
12 Blocked Overcurrent Protection 143
12.1 Blocked Overcurrent Implementation 143
12.2 Blocked Overcurrent Logic 143
12.3 Blocked Earth Fault Logic 143
12.4 Application Notes 144
12.4.1 Busbar Blocking Scheme 144
13 Second Harmonic Blocking 146
13.1 Second Harmonic Blocking Implementation 146
13.2 Second Harmonic Blocking Logic (POC Input) 147
13.3 Application Notes 147
13.3.1 Setting Guidelines 147
14 Stall protection 148
14.1 Prolonged start 148
14.2 Locked rotor during starting – (stall time < start time) 149
14.3 Stall during running 150
14.4 Momentary reduction in system voltage during running 150
14.5 Reacceleration after a reduction in system voltage 150
14.6 Low voltage ride through authorization 151
14.7 Auto re-start authorization restoration sequence 152
14.8 Application Notes 154
14.8.1 Start/stall protection 154
14.8.2 Excessive start time/locked rotor protection - stall time > start time 155
14.8.3 Stall protection (Stall while running) 155
14.8.4 Excessive start time/locked rotor protection - stall time < start time 156
14.8.5 Momentary reduction in system voltage during running of the motor 156
14.8.6 Low voltage protection (reacceleration authorization) 157
14.8.7 AUTO RE-START authorization 157
15 Number of Starts 158
15.1 Time between starts 160
15.2 Number of starts limitation 161
16 Anti-Backspin Protection 162
16.1 Application Notes 163
16.1.1 Anti-Backspin protection 163
Chapter 7 Restricted Earth Fault Protection 165
1 Chapter Overview 167
2 REF Protection Principles 168
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2.1 Restricted Earth Fault Types 169
2.1.1 Low Impedance Bias Characteristic 169
2.1.2 High Impedance REF Principle 170
3 Restricted Earth Fault Protection Implementation 172
3.1 Restricted Earth Fault Protection Settings 172
3.2 Low Impedance REF 172
3.2.1 Setting the Bias Characteristic 172
3.2.2 Delayed Bias 173
3.3 High Impedance REF 173
3.3.1 High Impedance REF Calculation Principles 173
4 Application Notes 175
4.1 Low Impedance REF Protection Application 175
4.1.1 Setting Guidelines for Biased Operation 175
4.1.2 Low Impedance REF Scaling Factor 175
4.2 High Impedance REF Protection Application 176
4.2.1 Setting Guidelines for High Impedance Operation 176
Chapter 8 CB Fail Protection 177
1 Chapter Overview 179
2 Circuit Breaker Fail Protection 180
3 Circuit Breaker Fail Implementation 181
3.1 Circuit Breaker Fail Timers 181
3.2 Zero Crossing Detection 181
4 Circuit Breaker Fail Logic 183
5 Undercurrent and ZCD Logic for CB Fail 185
6 CB Fail SEF Protection Logic 186
7 CB Fail Non Current Protection Logic 187
8 Circuit Breaker Mapping 188
9 Application Notes 189
9.1 Reset Mechanisms for CB Fail Timers 189
9.2 Setting Guidelines (CB fail Timer) 189
9.3 Setting Guidelines (Undercurrent) 190
Chapter 9 Current Transformer Requirements 191
1 Chapter Overview 193
2 CT requirements 194
2.1 Phase Overcurrent Protection 194
2.1.1 Directional Elements 194
2.1.2 Non-directional Elements 195
2.2 Earth Fault Protection 195
2.2.1 Directional Elements 195
2.2.2 Non-directional Elements 195
2.3 SEF Protection (Residually Connected) 195
2.3.1 Directional Elements 195
2.3.2 Non-directional Elements 196
2.4 SEF Protection (Core-Balanced CT) 196
2.4.1 Directional Elements 196
2.4.2 Non-directional Elements 196
2.5 Low Impedance REF Protection 196
2.6 High Impedance REF Protection 197
2.7 Use of Metrosil Non-linear Resistors 197
2.8 Use of ANSI C-class CTs 199
Chapter 10 Voltage Protection Functions 201
1 Chapter Overview 203
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2 Undervoltage Protection 204
2.1 Undervoltage Protection Implementation 204
2.2 Undervoltage Protection Logic 205
2.3 Application Notes 206
2.3.1 Undervoltage Protection 206
3 Overvoltage Protection 207
3.1 Overvoltage Protection Implementation 207
3.2 Overvoltage Protection Logic 208
3.3 Application Notes 209
3.3.1 Overvoltage Setting Guidelines 209
4 Residual Overvoltage Protection 210
4.1 Residual Overvoltage Protection Implementation 210
4.2 Residual Overvoltage Logic 211
4.3 Application Notes 211
4.3.1 Calculation for Solidly Earthed Systems 211
4.3.2 Calculation for Impedance Earthed Systems 212
4.3.3 Setting Guidelines 213
5 Negative Sequence Overvoltage Protection 214
5.1 Negative Sequence Overvoltage Implementation 214
5.2 Negative Sequence Overvoltage Logic 214
5.3 Application Notes 214
5.3.1 Setting Guidelines 214
6 Positive Sequence Undervoltage Protection 216
6.1 Positive Sequence Undervoltage Implementation 216
6.2 Positive Sequence Undervoltage Logic 216
7 Positive Sequence Overvoltage Protection 217
7.1 Positive Sequence Overvoltage Implementation 217
7.2 Positive Sequence Overvoltage Logic 217
8 Moving Average Voltage Functions 218
8.1 Moving Average Undervoltage Logic 218
8.2 Moving Average Overvoltage Logic 219
8.3 Moving Average Zero Sequence Voltage Logic 219
8.4 Moving Average Positive Sequence Voltage Logic 220
8.5 Moving Average Negative Sequence Voltage Logic 220
8.6 Moving Average Undervoltage Blocking PSL 220
Chapter 11 Frequency Protection Functions 221
1 Chapter Overview 223
2 Frequency Protection Overview 224
2.1 Frequency Protection Implementation 224
3 Underfrequency Protection 225
3.1 Underfrequency Protection Implementation 225
3.2 Underfrequency Protection Logic 225
3.3 Application Notes 225
3.3.1 Setting Guidelines 225
4 Overfrequency Protection 227
4.1 Overfrequency Protection Implementation 227
4.2 Overfrequency Protection Logic 227
4.3 Application Notes 227
4.3.1 Setting Guidelines 227
5 Independent R.O.C.O.F Protection 229
5.1 Indepenent R.O.C.O.F Protection Implementation 229
5.2 Independent R.O.C.O.F Protection Logic 229
5.3 Application Notes 230
5.3.1 Setting Guidelines 230
6 Frequency-supervised R.O.C.O.F Protection 231
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6.1 Frequency-supervised R.O.C.O.F Implementation 231
6.2 Frequency-supervised R.O.C.O.F Logic 232
6.3 Application Notes 232
6.3.1 Frequency-Supervised R.O.C.O.F Example 232
6.3.2 Setting Guidelines 233
7 Average Rate of Change of Frequency Protection 234
7.1 Average R.O.C.O.F Protection Implementation 234
7.2 Average R.O.C.O.F Logic 235
7.3 Application Notes 235
7.3.1 Setting Guidelines 235
Chapter 12 Power Protection Functions 237
1 Chapter Overview 239
2 Reverse Power Protection 240
2.1 Reverse Power Implementation 240
Chapter 13 Monitoring and Control 241
1 Chapter Overview 243
2 Event Records 244
2.1 Event Types 244
2.1.1 Opto-input Events 245
2.1.2 Contact Events 245
2.1.3 Alarm Events 245
2.1.4 Fault Record Events 250
2.1.5 Security Events 250
2.1.6 Maintenance Events 251
2.1.7 Protection Events 251
2.1.8 Platform Events 251
3 Disturbance Recorder 252
4 Measurements 253
4.1 Measured Quantities 253
4.1.1 Measured and Calculated Currents 253
4.1.2 Measured and Calculated Voltages 253
4.1.3 Power and Energy Quantities 253
4.1.4 Demand Values 254
4.1.5 Frequency Measurements 254
4.1.6 Other Measurements 254
4.2 Measurement Setup 254
4.3 Opto-input Time Stamping 255
5 CB Condition Monitoring 256
5.1 Application Notes 256
5.1.1 Setting the Thresholds for the Total Broken Current 256
5.1.2 Setting the thresholds for the Number of Operations 256
5.1.3 Setting the thresholds for the Operating Time 257
5.1.4 Setting the Thresholds for Excesssive Fault Frequency 257
6 CB State Monitoring 258
6.1 CB State Monitoring Logic 259
7 Circuit Breaker Control 260
7.1 CB Control using the IED Menu 260
7.2 CB Control using the Hotkeys 261
7.3 CB Control using the Function Keys 261
7.4 CB Control using the Opto-inputs 262
7.5 Remote CB Control 262
7.6 CB Healthy Check 263
7.7 CB Control Logic 264
8 Pole Dead Function 265
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8.1 Pole Dead Logic 265
9 System Checks 266
9.1 System Checks Implementation 266
9.1.1 VT Connections 266
9.1.2 Voltage Monitoring 266
10 Switch Status and Control 267
10.1 Switch Status Logic 268
10.2 Switch Control Logic 269
Chapter 14 Supervision 271
1 Chapter Overview 273
2 DC Supply Monitor 274
2.1 DC Supply Monitor Implementation 274
2.2 DC Supply Monitor Logic 275
3 Voltage Transformer Supervision 276
3.1 Loss of One or Two Phase Voltages 276
3.2 Loss of all Three Phase Voltages 276
3.3 Absence of all Three Phase Voltages on Line Energisation 276
3.4 VTS Implementation 277
3.5 VTS Logic 277
3.6 VTS Acceleration Indication Logic 279
4 Current Transformer Supervision 280
4.1 CTS Implementation 280
4.2 CTS Logic 280
4.3 Application Notes 281
4.3.1 Setting Guidelines 281
5 Trip Circuit Supervision 282
5.1 Trip Circuit Supervision Scheme 1 282
5.1.1 Resistor Values 282
5.1.2 PSL for TCS Scheme 1 283
5.2 Trip Circuit Supervision Scheme 2 283
5.2.1 Resistor Values 284
5.2.2 PSL for TCS Scheme 2 284
5.3 Trip Circuit Supervision Scheme 3 285
5.3.1 Resistor Values 285
5.3.2 PSL for TCS Scheme 3 286
5.4 Trip Circuit Supervision Scheme 4 286
5.4.1 Resistor Values 287
5.4.2 PSL for TCS Scheme 4 287
Chapter 15 Digital I/O and PSL Configuration 289
1 Chapter Overview 291
2 Configuring Digital Inputs and Outputs 292
3 Scheme Logic 293
3.1 PSL Editor 294
3.2 PSL Schemes 294
3.3 PSL Scheme Version Control 294
4 Configuring the Opto-Inputs 295
5 Assigning the Output Relays 296
6 Fixed Function LEDs 297
6.1 Trip LED Logic 297
7 Configuring Programmable LEDs 298
8 Function Keys 300
9 Control Inputs 301
10 Inter-PSL Inputs and Outputs 302
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Chapter 16 Communications 303
1 Chapter Overview 305
2 Communication Interfaces 306
3 Serial Communication 307
3.1 Universal Serial Bus 307
3.2 EIA(RS)485 Bus 307
3.2.1 EIA(RS)485 Biasing Requirements 308
3.3 K-Bus 308
4 Standard Ethernet Communication 310
5 Redundant Ethernet Communication 311
5.1 Supported Protocols 311
5.2 Parallel Redundancy Protocol 311
5.3 High-Availability Seamless Redundancy (HSR) 312
5.3.1 HSR Multicast Topology 312
5.3.2 HSR Unicast Topology 313
5.3.3 HSR Application in the Substation 314
5.4 Rapid Spanning Tree Protocol 315
5.5 Configuring IP Address 316
6 Data Protocols 317
6.1 Courier 317
6.1.1 Physical Connection and Link Layer 317
6.1.2 Courier Database 317
6.1.3 Settings Categories 318
6.1.4 Setting Changes 318
6.1.5 Event Extraction 318
6.1.6 Disturbance Record Extraction 320
6.1.7 Programmable Scheme Logic Settings 320
6.1.8 Time Synchronisation 320
6.1.9 Courier Configuration 320
6.2 IEC 60870-5-103 322
6.2.1 Physical Connection and Link Layer 322
6.2.2 Initialisation 323
6.2.3 Time Synchronisation 323
6.2.4 Spontaneous Events 323
6.2.5 General Interrogation (GI) 323
6.2.6 Cyclic Measurements 323
6.2.7 Commands 323
6.2.8 Test Mode 323
6.2.9 Disturbance Records 324
6.2.10 Command/Monitor Blocking 324
6.2.11 IEC 60870-5-103 Configuration 324
6.3 DNP 3.0 325
6.3.1 Physical Connection and Link Layer 325
6.3.2 Object 1 Binary Inputs 326
6.3.3 Object 10 Binary Outputs 326
6.3.4 Object 20 Binary Counters 327
6.3.5 Object 30 Analogue Input 327
6.3.6 Object 40 Analogue Output 327
6.3.7 Object 50 Time Synchronisation 327
6.3.8 DNP3 Device Profile 328
6.3.9 DNP3 Configuration 336
6.3.10 DNP3 Unsolicited Reporting 337
6.4 MODBUS 337
6.4.1 Physical Connection and Link Layer 337
6.4.2 MODBUS Functions 337
6.4.3 Response Codes 338
6.4.4 Register Mapping 338
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6.4.5 Event Extraction 339
6.4.6 Disturbance Record Extraction 340
6.4.7 Setting Changes 347
6.4.8 Password Protection 347
6.4.9 Protection and Disturbance Recorder Settings 347
6.4.10 Time Synchronisation 348
6.4.11 Power and Energy Measurement Data Formats 349
6.4.12 MODBUS Configuration 350
6.5 IEC 61850 351
6.5.1 Benefits of IEC 61850 351
6.5.2 IEC 61850 Interoperability 352
6.5.3 The IEC 61850 Data Model 352
6.5.4 IEC 61850 in MiCOM IEDs 353
6.5.5 IEC 61850 Data Model Implementation 353
6.5.6 IEC 61850 Communication Services Implementation 353
6.5.7 IEC 61850 Peer-to-peer (GOOSE) communications 354
6.5.8 Mapping GOOSE Messages to Virtual Inputs 354
6.5.9 Ethernet Functionality 354
6.5.10 IEC 61850 Configuration 355
6.6 Concurrent IEC 61850 and DNP3.0 Operation 356
7 Read Only Mode 358
7.1 IEC 60870-5-103 Protocol Blocking 358
7.2 Courier Protocol Blocking 358
7.3 IEC 61850 Protocol Blocking 359
7.4 Read-Only Settings 359
7.5 Read-Only DDB Signals 359
8 Time Synchronisation 360
8.1 Demodulated IRIG-B 360
8.1.1 Demodulated IRIG-B Implementation 361
8.2 SNTP 361
8.3 Time Synchronsiation using the Communication Protocols 361
Chapter 17 Cyber-Security 363
1 Overview 365
2 The Need for Cyber-Security 366
3 Standards 367
3.1 NERC Compliance 367
3.1.1 CIP 002 368
3.1.2 CIP 003 368
3.1.3 CIP 004 368
3.1.4 CIP 005 368
3.1.5 CIP 006 368
3.1.6 CIP 007 369
3.1.7 CIP 008 369
3.1.8 CIP 009 369
3.2 IEEE 1686-2007 369
4 Cyber-Security Implementation 371
4.1 NERC-Compliant Display 371
4.2 Four-level Access 372
4.2.1 Blank Passwords 373
4.2.2 Password Rules 374
4.2.3 Access Level DDBs 374
4.3 Enhanced Password Security 374
4.3.1 Password Strengthening 374
4.3.2 Password Validation 375
4.3.3 Password Blocking 375
4.4 Password Recovery 376
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4.4.1 Entry of the Recovery Password 376
4.4.2 Password Encryption 377
4.5 Disabling Physical Ports 377
4.6 Disabling Logical Ports 377
4.7 Security Events Management 378
4.8 Logging Out 380
Chapter 18 Installation 381
1 Chapter Overview 383
2 Handling the Goods 384
2.1 Receipt of the Goods 384
2.2 Unpacking the Goods 384
2.3 Storing the Goods 384
2.4 Dismantling the Goods 384
3 Mounting the Device 385
3.1 Flush Panel Mounting 385
3.1.1 Rack Mounting 385
3.2 Software Only 386
4 Cables and Connectors 388
4.1 Terminal Blocks 388
4.2 Power Supply Connections 388
4.3 Earth Connnection 389
4.4 Current Transformers 389
4.5 Voltage Transformer Connections 389
4.6 Watchdog Connections 390
4.7 EIA(RS)485 and K-Bus Connections 390
4.8 IRIG-B Connection 390
4.9 Opto-input Connections 391
4.10 Output Relay Connections 391
4.11 Ethernet Metallic Connections 391
4.12 Ethernet Fibre Connections 391
4.13 USB Connection 391
5 Case Dimensions 392
Chapter 19 Commissioning Instructions 395
1 Chapter Overview 397
2 General Guidelines 398
3 Commissioning Test Menu 399
3.1 Opto I/P Status Cell (Opto-input Status) 399
3.2 Relay O/P Status Cell (Relay Output Status) 399
3.3 Test Port Status Cell 399
3.4 Monitor Bit 1 to 8 Cells 399
3.5 Test Mode Cell 399
3.6 Test Pattern Cell 400
3.7 Contact Test Cell 400
3.8 Test LEDs Cell 400
3.9 Test Autoreclose Cell 400
3.10 Red and Green LED Status Cells 400
4 Commissioning Equipment 402
4.1 Recommended Commissioning Equipment 402
4.2 Essential Commissioning Equipment 402
4.3 Advisory Test Equipment 403
5 Product Checks 404
5.1 Product Checks with the IED De-energised 404
5.1.1 Visual Inspection 404
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5.1.2 Insulation 405
5.1.3 External Wiring 405
5.1.4 Watchdog Contacts 405
5.1.5 Power Supply 405
5.2 Product Checks with the IED Energised 405
5.2.1 Watchdog Contacts 406
5.2.2 Test LCD 406
5.2.3 Date and Time 406
5.2.4 Test LEDs 406
5.2.5 Test Alarm and Out-of-Service LEDs 407
5.2.6 Test Trip LED 407
5.2.7 Test User-programmable LEDs 407
5.2.8 Test Opto-inputs 407
5.2.9 Test Output Relays 407
5.2.10 Test Serial Communication Port RP1 407
5.2.11 Test Serial Communication Port RP2 409
5.2.12 Test Ethernet Communication 409
5.2.13 Test Current Inputs 409
5.2.14 Test Voltage Inputs 410
6 Setting Checks 412
6.1 Apply Application-specific Settings 412
6.1.1 Transferring Settings from a Settings File 412
6.1.2 Entering settings using the HMI 412
7 Protection Timing Checks 414
7.1 Overcurrent Check 414
7.2 Connecting the Test Circuit 414
7.3 Performing the Test 414
7.4 Check the Operating Time 414
8 Onload Checks 416
8.1 Confirm Current Connections 416
8.2 Confirm Voltage Connections 416
8.3 On-load Directional Test 417
9 Final Checks 418
Chapter 20 Maintenance and Troubleshooting 419
1 Chapter Overview 421
2 Maintenance 422
2.1 Maintenance Checks 422
2.1.1 Alarms 422
2.1.2 Opto-isolators 422
2.1.3 Output Relays 422
2.1.4 Measurement Accuracy 422
2.2 Replacing the Unit 423
2.3 Cleaning 423
3 Troubleshooting 424
3.1 Self-Diagnostic Software 424
3.2 Power-up Errors 424
3.3 Error Message or Code on Power-up 424
3.4 Out of Service LED on at Power-up 425
3.5 Error Code during Operation 425
3.6 Mal-operation during testing 426
3.6.1 Failure of Output Contacts 426
3.6.2 Failure of Opto-inputs 426
3.6.3 Incorrect Analogue Signals 426
3.7 PSL Editor Troubleshooting 426
3.7.1 Diagram Reconstruction 427
3.7.2 PSL Version Check 427
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3.8 Repair and Modification Procedure 427
Chapter 21 Technical Specifications 429
1 Chapter Overview 431
2 Interfaces 432
2.1 Front USB Port 432
2.2 Rear Serial Port 1 432
2.3 Rear Serial Port 2 432
2.4 IRIG-B Port 432
2.5 Rear Ethernet Port Copper 433
2.6 Rear Ethernet Port - Fibre 433
2.6.1 100 Base FX Receiver Characteristics 433
2.6.2 100 Base FX Transmitter Characteristics 433
3 Performance of Current Protection Functions 434
3.1 Three-phase Overcurrent Protection 434
3.1.1 Three-phase Overcurrent Directional Parameters 434
3.1.2 Thermal Overload Protection 434
3.2 Earth Fault Protection 434
3.2.1 Earth Fault Directional Parameters 435
3.3 Sensitive Earth Fault Protection 435
3.3.1 SEF Directional Parameters 436
3.4 Restricted Earth Fault Protection 436
3.5 Negative Sequence Overcurrent Protection 436
3.5.1 NPSOC Directional Parameters 437
3.6 Stall Protection 437
3.7 Circuit Breaker Fail and Undercurrent Protection 437
3.8 Broken Conductor Protection 437
3.9 Selective Overcurrent Protection 437
3.10 Cold Load Pickup Protection 438
4 Performance of Voltage Protection Functions 439
4.1 Undervoltage Protection 439
4.2 Overvoltage Protection 439
4.3 Residual Overvoltage Protection 439
4.4 Negative Sequence Voltage Protection 439
4.5 Rate of Change of Voltage Protection 440
5 Performance of Frequency Protection Functions 441
5.1 Overfrequency Protection 441
5.2 Underfrequency Protection 441
5.3 Supervised Rate of Change of Frequency Protection 441
5.4 Independent Rate of Change of Frequency Protection 442
5.5 Average Rate of Change of Frequency Protection 442
5.6 Load Restoration 443
5.7 Anti-Backspin 443
6 Power Protection Functions 444
6.1 Reverse Power Protection 444
7 Performance of Monitoring and Control Functions 445
7.1 Voltage Transformer Supervision 445
7.2 Current Transformer Supervision 445
7.3 CB State and Condition Monitoring 445
7.4 PSL Timers 445
7.5 DC Supply Monitor 445
8 Measurements and Recording 447
8.1 General 447
8.2 Measured Operating Data 447
8.3 Disturbance Records 448
8.4 Event, Fault and Maintenance Records 448
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9 Regulatory Compliance 449
9.1 EMC Compliance: 2014/30/EU 449
9.2 LVD Compliance: 2014/35/EU 449
9.3 R&TTE Compliance: 2014/53/EU 449
9.4 UL/CUL Compliance 449
9.5 ATEX Compliance: 2014/34/EU 449
10 Mechanical Specifications 451
10.1 Physical Parameters 451
10.2 Enclosure Protection 451
10.3 Mechanical Robustness 451
10.4 Transit Packaging Performance 451
11 Ratings 452
11.1 AC Measuring Inputs 452
11.2 Current Transformer Inputs 452
11.3 Voltage Transformer Inputs 452
12 Power Supply 453
12.1 Auxiliary Power Supply Voltage 453
12.2 Nominal Burden 453
12.3 Auxiliary Power Supply Interruption 453
13 Input / Output Connections 454
13.1 Isolated Digital Inputs 454
13.1.1 Nominal Pickup and Reset Thresholds 454
13.2 Standard Output Contacts 454
13.3 Watchdog Contacts 455
13.4 Shorting Link 455
14 Environmental Conditions 456
14.1 Ambient Temperature Range 456
14.2 Temperature Endurance Test 456
14.3 Ambient Humidity Range 456
14.4 Corrosive Environments 456
15 Type Tests 457
15.1 Insulation 457
15.2 Creepage Distances and Clearances 457
15.3 High Voltage (Dielectric) Withstand 457
15.4 Impulse Voltage Withstand Test 457
16 Electromagnetic Compatibility 459
16.1 1 MHz Burst High Frequency Disturbance Test 459
16.2 Damped Oscillatory Test 459
16.3 Immunity to Electrostatic Discharge 459
16.4 Electrical Fast Transient or Burst Requirements 459
16.5 Surge Withstand Capability 459
16.6 Surge Immunity Test 460
16.7 Immunity to Radiated Electromagnetic Energy 460
16.8 Radiated Immunity from Digital Communications 460
16.9 Radiated Immunity from Digital Radio Telephones 460
16.10 Immunity to Conducted Disturbances Induced by Radio Frequency Fields 460
16.11 Magnetic Field Immunity 461
16.12 Conducted Emissions 461
16.13 Radiated Emissions 461
16.14 Power Frequency 461
Appendix A Ordering Options 463
Appendix B Settings and Signals 465
Contents P24xM
xiv P24xM-TM-EN-2.1

Appendix C Wiring Diagrams 467
P24xM Contents
P24xM-TM-EN-2.1 xv

Contents P24xM
xvi P24xM-TM-EN-2.1

Table of Figures
Figure 1: Key to logic diagrams 11
Figure 2: Functional Overview (P24DM) 12
Figure 3: Hardware design overview 30
Figure 4: Exploded view of IED 32
Figure 5: 20TE rear panel 33
Figure 6: 30TE Three-MIDOS block rear panel 34
Figure 7: 30TE Two-MIDOS block + communications rear panel 34
Figure 8: 30TE Two-MIDOS block + blanking plate 35
Figure 9: 40TE Three-MIDOS block + communications rear panel 35
Figure 10: Front panel (20TE) 37
Figure 11: Front panel (30TE) 38
Figure 12: Front panel (40TE) 39
Figure 13: Software structure 46
Figure 14: Frequency Response (indicative only) 51
Figure 15: Navigating the HMI 58
Figure 16: Default display navigation 60
Figure 17: Thermal overload protection logic diagram 77
Figure 18: Cooling time constant 77
Figure 19: Example of settings 80
Figure 20: Thermal curve modification 82
Figure 21: IEC 60255 IDMT curves 87
Figure 22: IEC standard and very inverse curves 90
Figure 23: IEC Extremely inverse and IEEE moderate inverse curves 90
Figure 24: IEEE very and extremely inverse curves 91
Figure 25: Principle of protection function implementation 92
Figure 26: Non-directional Overcurrent Logic diagram 95
Figure 27: Directional trip angles 97
Figure 28: Directional Overcurrent Logic diagram (Phase A shown only) 98
Figure 29: OR logic 99
Figure 30: AND logic 99
Figure 31: Definite time overcurrent element 100
Figure 32: Selecting the current threshold setting 101
Figure 33: Negative Sequence Overcurrent logic - non-directional operation 103
Figure 34: Negative Sequence Overcurrent logic - directional operation 104
Figure 35: Equivalent circuits 105
Figure 36: IDG Characteristic 111
Figure 37: Directional angles 112
Figure 38: Directional EF logic with neutral voltage polarization (single stage) 113

Figure 39: Directional angles 114
Figure 40: *Directional Earth Fault logic with negative sequence polarisation (single stage) 114
Figure 41: Current level (amps) at which transient faults are self-extinguishing 115
Figure 42: Earth fault in Petersen Coil earthed system 116
Figure 43: Distribution of currents during a Phase C fault 116
Figure 44: Phasors for a phase C earth fault in a Petersen Coil earthed system 117
Figure 45: Zero sequence network showing residual currents 117
Figure 46: Phase C earth fault in Petersen Coil earthed system: practical case with resistance
present
118
Figure 47: Fuse characteristic 120
Figure 48: Current distribution in an insulated system with C phase fault 121
Figure 49: Phasor diagrams for insulated system with C phase fault 122
Figure 50: Directional tripping characteristic 124
Figure 51: Current distribution in Petersen coil earthed system 125
Figure 52: Distribution of currents during a C phase to earth fault 126
Figure 53: Theoretical case - no resistance present in XL or XC 126
Figure 54: Zero sequence network showing residual currents 127
Figure 55: Practical case:- resistance present in XL and Xc 128
Figure 56: Non-directional SEF logic 130
Figure 57: EPATR B characteristic shown for TMS = 1.0 131
Figure 58: Resistive components of spill current 132
Figure 59: Operating characteristic for Icos 133
Figure 60: Directional SEF with VN polarisation (single stage) 134
Figure 61: Current distribution in an insulated system with C phase fault 135
Figure 62: Phasor diagrams for insulated system with C phase fault 136
Figure 63: Positioning of core balance current transformers 137
Figure 64: Cold Load Pickup logic 139
Figure 65: Selective Logic 141
Figure 66: Selecting the timer settings 142
Figure 67: Blocked Overcurrent logic 143
Figure 68: Blocked Earth Fault logic 144
Figure 69: Simple busbar blocking scheme 144
Figure 70: Simple busbar blocking scheme characteristics 145
Figure 71: 2nd Harmonic Blocking Logic (POC Input) 147
Figure 72: Start successful 148
Figure 73: Locked rotor detection 149
Figure 74: Reacceleration detection 150
Figure 75: Adjustable reacceleration authorization - Voltage restored within the set time 151
Figure 76: Adjustable reacceleration authorization - Voltage restored after the set time 152
Figure 77: Automatic restart authorized- voltage restored within the set time 153
Table of Figures P24xM
xviii P24xM-TM-EN-2.1