Getac 9270D User manual

1
9
92 270D N/B Maintenance 70D N/B Maintenance
BY: Wenrong.pu
Technical Maintenance Department/GTK MTC
Jan. 2010/R01
SERVICE MANUAL FOR
9270D
SERVICE MANUAL FOR
SERVICE MANUAL FOR
9270D
9270D

Contents
1. Hardware Engineering Specification …………………………………………………………………….
1.1 Introduction ………………………………………………………………………………………………………………
1.2 System Hardware Parts…………………………………………………………………………………………………..
1.3 Other Function ………………………………………………………………………………………...………………....
1.4 Peripheral Components …………………………………………………………………………………………………
1.5 Power Management ………………………………………………………………………………………...……………
1.6 Appendix ………………………………………………………………………………………...……………….... …....
2. System View and Disassembly …………………………………………………………………………....
2.1 System View ………………………………………………………………………………………………………………
2.2 Tools Introduction …………………………………………………………………………………………………..……
2.3 System Disassembly ………………………………………………………………………………………………………
3. Definition & Location of Connectors/Switches ………………………………………………………….
3.1 Mother Board ………………………………………………………………………………………………….................
4. Pin Descriptions of Ibex Peak-M…………………………………………………………... …... …... …..
5. System Block Diagram ……………………………………………………………………………………
3
3
6
40
46
48
51
67
67
70
71
88
88
91
161

Contents
6. Trouble Shooting ………………………………………………………………………………………….
6.1 No Power ………………………………………………………………………………………………….......................
6.2 No Display ………………………………………………………………………………………………….....................
6.3 Graphics Controller Failure LCD No Display ………………………………………………………………………..
6.4 External Monitor No Display …………………………………………………………………………………………..
6.5 Memory Failure …………………………………………………………………………………………………............
6.6 Keyboard (K/B) or Touch-Pad (T/P) Failure ………………………………………………………………………....
6.7 Hard Disk Drive Failure ………………………………………………………………………………………………..
6.8 ODD Failure ………………………………………………………………………………………………….................
6.9 USB Ports Failure …………………………………………………………………………………………………........
6.10 Audio Failure ………………………………………………………………………………………………….............
6.11 LAN Failure …………………………………………………………………………………………………...............
6.12 Card Reader Slot Failure …………………………………………………………………………………………......
6.13 Mini Express (Wireless) Socket Failure ……………………………………………………………………………..
6.14 Express Card Socket Failure …………………………………………………………………………………………
7. Reference Material ………………………………………………………………………………………
162
164
165
166
167
168
169
170
171
172
173
174
175
176
177
179

1. Hardware Engineering Specification
1.1 Introduction
The 9270D motherboard implements Intel’s Calpella platform with Arrandale mobile processor. Arrandale is the
next generation of 64-bit, multi-core mobile processors built on 32-nanometer process technology. Throughout this
document, Arrandale may be referredto as simply the processor. Based on the low-power/high-performance
Nehalem microarchitecture, the processor is designed for a two-chip platform as opposed to the traditional three-
chip platforms (processor, GMCH, and ICH). The two-chip platform consists of a processor and the Platform
Controller Hub (PCH) and enables higher performance, lower cost, easier validation, and improved x-y footprint.
Included in this family of processors is an integrated memory controller (IMC) and integrated I/O (IIO) (such as
PCI Express* and DMI) on a single-silicon die. This singledie solution is known as a monolithic processor.
The Ibex Peak provides extensive I/O support. Functions and capabilities include:
¾PCI Express* Base Specification, Revision 2.0 support for up to eight ports.
¾PCI Local Bus Specification, Revision 2.3 support for 33 MHz PCI operations
(supports up to four Req/Gnt pairs).
¾ACPI Power Management Logic Support, Revision 3.0b
¾Enhanced DMA controller, interrupt controller, and timer functions

¾Integrated Serial ATA host controllers with independent DMA operation on up to six ports.
¾FIS-based Port Multiplier support on SATA Ports 4 and 5 in AHCI/RAID mode.
¾USB host interface with support for up to fourteen USB ports; two EHCI high-speed USB 2.0 Host controllers, 2
rate matching hubs, seven UHCI host controllers;
¾Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense
¾System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices
¾Supports Intel® High Definition Audio
¾Supports Intel® Matrix Storage Technology
¾Supports Intel® Trusted Execution Technology
¾Analog and Digital Display ports
— Analog CRT
— HDMI
—DVI
— DisplayPort 1.1
— SDVO

— LVDS (Mobile Only)
¾Low Pin Count (LPC) interface
¾Firmware Hub (FWH) interface support
¾Serial Peripheral Interface (SPI) support
¾Intel® Quiet System Technology (Desktop only)
¾Intel® Anti-Theft Technology
User expendable peripheral interface built on 9270D system are 3 USB + 1 combo E-SATA ports. 9270D system
provides a New Card / Express Card and Mini PCI-E Card. User interface includes internal keyboard, touch pad.
Realtek ALC663 High Definition (Azalia) Audio Codec based multimedia interface includes Built-in stereo speaker
and woofer, Microphone-in and headphone-out audio jacks. There is one communication the RGMII Giga Ethernet
PHY to support RJ-45 LAN jack.
A full set of software drivers and utilities are available to allow advanced operating systems such as Windows Vista
to take full advantage of the hardware capabilities. Features such as bus mastering IDE, Plug and Play, Advanced
Configuration Power Interface (ACPI) with application restart, software-controlled power shutdown.

1.2 System Hardware Parts-1
Spec
Intel Arrandale CPU
45/35W (Processor/chipset SOC)
18.4 SWXGA + Glare/Non Glare
-Max Brightness :TBD
Ibex Peak Chipset
0 MB on board
Type DDRIII SO-DIMM 1066/1333 MHz
Slot 2 SO-DIMM
Max Size 8GB
ATI M96-XT
VRAM 1GB
No. chips 64x16x8
Function Display
Interface Azalia
Speaker 2.5 W speak x2 3Wx1
Int. Mic 1
Other Dolby Home Theater Logo
Basic Function Remark
CPU
Type
TDP
Display 1680x945 HD+
1920x1080 FHD
Chipset
Memory
Graphic
Audio ALC633, Vista Criteria

1.2 System Hardware Parts-2
Spec
Slot Type Express 54 x1
Function Wake on ring support X
To be able to disable by BIOS X
4 in 1 Card Reader
Slot Type MS / MS PRO / SD / MMC
Access LED N/A
Function SDHC Support
Spec
SATA I/F,2.5” 9.5mm height HDD
Function
Structure CBB Compliant
SATA I/F,12.7mm height ODD
Type Super Multi/BD
Structure CBB Compliant
Bezel G-BASE
Basic Function Remark
Express Card USB & PCI-E
Card Reader
Storage Device Remark
HDD
ODD

1.2.1 Intel Arrandale CPU Processor
1.2.1.1 CPU – Intel Arrandale
Arrandale Processor Introduction
Arrandale is the next generation of 64-bit, multi-core mobile processor built on 32- nanometer process
technology. Throughout this document, Auburndale may be referred to as simply the processor. Based on the
low-power/high-performance Nehalem micro-architecture, the processor is designed for a two-chip platform as
opposed to the traditional three-chip platforms (processor, GMCH, and ICH). The two-chip platform consists of
a processor and the Platform Controller Hub (PCH) and enables higher performance, lower cost, easier
validation, and improved x-y footprint. The PCH may also be referred to as Mobile Intel® 5 Series Chipset
(formerly Ibex Peak- M). Auburndale is designed for the Calpella platform and is offered in an rPGA988A or a
BGA1288 package. Included in this family of processors is an integrated graphics and memory controller die on
the same package as the processor core die. This two-chip solution of a processor core die with an integrated
graphics and memory controller die is known as a multi-chip package (MCP) processor.
Note: Integrated graphics and memory controller die is built on 32-nanometer process technology
Processor Feature Details
¾Four execution cores
¾A 32-KB instruction and 32-KB data first-level cache (L1) for each core
¾A 256-KB shared instruction/data second-level cache (L2) for each core

¾Up to 8-MB shared instruction/data last-level cache (L3), shared among all cores
¾Intel® Virtualization Technology (Intel® VT-x)
¾Intel® Virtualization Technology for Directed I/O (Intel® VT-d)
¾Intel® Trusted Execution Technology (Intel® TXT)
¾Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1)
¾Supplemental Streaming SIMD Extensions 4.2 (Intel® SSE4.2)
¾Intel® Hyper-Threading Technology (Intel® HT Technology)
¾Intel® 64 architecture
¾Execute Disable Bit
¾Intel® Turbo Boost Technology

1.2.1.2 Mobile Intel Arrandale system memory support
The Integrated Memory Controller (IMC) supports DDR3 protocols with two, independent, 64-bit wide channels
each accessing one SO-DIMM. It supports a maximum of one, unbuffered non-ECC DDR3 SO-DIMM per-
channel thus allowing up to two device ranks per-channel. DDR3 Data Transfer Rates: — 800 MT/s (PC3-6400),
and 1066 MT/s (PC3-8500)
¾DDR3 SO-DIMM Modules:
— Raw Card A – double-sided x16 unbuffered non-ECC
— Raw Card B – single-sided x8 unbuffered non-ECC
— Raw Card C – single-sided x16 unbuffered non-ECC
— Raw Card D – double-sided x8 (stacked) unbuffered non-ECC
— Raw Card F – double-sided x8 (planar) unbuffered non-ECC
¾DDR3 DRAM Device Technology:
— Standard 1-Gb, and 2-Gb technologies and addressing are supported for x16 and x8 devices. There is no
support for memory modules with different technologies or capacities on opposite sides of the same memory
module. If one side of a memory module is populated, the other side is either identical or empty.

System Memory Timing Support
The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and command signal mode
timings on the main memory interface:
¾tCL = CAS Latency
¾tRCD = Activate Command to READ or WRITE Command delay
¾tRP = PRECHARGE Command Period
¾CWL = CAS Write Latency
¾Command Signal modes = 1n indicates a new command may be issued every clock and 2n indicates a new
command may be issued every 2 clocks. Command launch mode programming depends on the transfer rate and
memory configuration.
System Memory Organization Modes
The IMC supports two memory organization modes, single-channel and dual-channel. Depending upon how the
SO-DIMM Modules are populated in each memory channel, a number of different configurations can exist.
Rules for Populating Memory Slots
In all modes, the frequency of system memory is the lowest frequency of all memory modules placed in the
system, as determined through the SPD registers on the memory modules. The system memory controller supports
only one SO-DIMM connector per channel. For dual-channel modes both channels must have an SO DIMM
connector populated. For single-channel mode, only a single-channel can have an SO-DIMM connector populated.

1.2.2 Intel Platform control HUB Ibex Peak chipset
1.2.2.1 Introduction
¾Direct Media Interface
—10 Gb/s each direction, full duplex
—Transparent to software
¾PCI Express*
—NEW: 8 PCI Express root ports
—NEW: PCI Express 2.0 specification running at 2.5GT/s.
—NEW: Ports 1-4 and 5-8 can independently be configured to support eight x1s, two x4s, two x2s and four x1s, or
one x4 and four x1 port widths.
—Support for full 2.5 Gb/s bandwidth in each direction per x1 lane
—Module based Hot-Plug supported (e.g., ExpressCard*)

¾PCI Bus Interface
—Supports PCI Rev 2.3 Specification at 33 MHz
—Four available PCI REQ/GNT pairs
—Support for 64-bit addressing on PCI using DAC protocol
¾Integrated Serial ATA Host Controller
—Up to six SATA ports
—Data transfer rates up to 3.0 Gb/s (300 MB/s).
—Integrated AHCI controller
¾External SATA support
—NEW: Port Disable Capability
¾Intel®High Definition Audio Interface
—PCI Express endpoint
—Independent Bus Master logic for eight general purpose streams: four input and four output
—Support four external Codecs

—Supports variable length stream slots
—Supports multichannel, 32-bit sample depth, 192 kHz sample rate output
—Provides mic array support
—Allows for non-48 kHz sampling output
—Support for ACPI Device
¾USB 2.0
—NEW: Two USB 2.0 Rate Matching Hubs to replace functionality of UHCI controllers
—Two EHCI Host Controllers, supporting up to fourteen external ports
—Per-Port-Disable Capability
—Includes up to two USB 2.0 High-speed Debug Ports
—Supports wake-up from sleeping states S1-S4
—Supports legacy Keyboard/Mouse software

¾Integrated Gigabit LAN Controller
—NEW: PCI Express* connection
—Integrated ASF Management Controller
—Network security with System Defense
—Supports IEEE 802.3
—10/100/1000 Mbps Ethernet Support
—Jumbo Frame Support
¾Power Management Logic
—Supports ACPI 3.0b
—ACPI-defined power states (processor driven C states)
—ACPI Power Management Timer
—SMI# generation
—All registers readable/restorable for proper resume from 0 V suspend states
—Support for APM-based legacy power management for non-ACPI implementations

¾Enhanced DMA Controller
—Two cascaded 8237 DMA controllers
—Supports LPC DMA
¾SMBus
—Faster speed, up to 100 kbps
—Flexible SMBus/SMLink architecture to optimize for ASF
—Provides independent manageability bus through SMLink interface
—Supports SMBus 2.0 Specification
—Host interface allows processor to communicate via SMBus
—Slave interface allows an internal or external Microcontroller to access system resources
—Compatible with most two-wire components that are also I2C compatible
¾High Precision Event Timers
—Advanced operating system interrupt scheduling

¾Real-Time Clock
—256-byte battery-backed CMOS RAM
—Integrated oscillator components
—Lower Power DC/DC Converter implementation
¾Serial Peripheral Interface (SPI)
—Supports up to two SPI devices
—Supports 20 MHz, 33 MHz SPI devices
—Support up to two different erase granularities
¾Interrupt Controller
—Supports up to eight PCI interrupt pins
—Supports PCI 2.3 Message Signaled Interrupts
—Two cascaded 82C59 with 15 interrupts
—Integrated I/O APIC capability with 24 interrupts
—Supports Processor System Bus interrupt delivery

¾Firmware Hub I/F supports BIOS Memory size up to 8 MBytes
¾Low Pin Count (LPC) I/F
—Supports two Master/DMA devices.
—Support for Security Device (Trusted Platform Module) connected to LPC.
¾Package
—27 mm x 27 mm FCBGA (Desktop Only)
—27 mm x 25 mm FCBGA (Mobile Only)
—22 mm x 20 mm FCBGA (Mobile SFF Only)
¾Analog Display Port
¾Digital Display
—Three Digital Display ports capable of supporting HDMI/DVI and Display port
—One Digital Display port supporting SDVO
—LVDS

1.2.2.2 Features and Functions
Digital Media Interface (DMI)
Digital Media Interface (DMI) is the chip-to-chip connection between the processor and Ibex Peak chipset. This
high-speed interface integrates advanced priority-based servicing allowing for concurrent traffic and true
isochronous transfer capabilities. Base functionality is completely software-transparent, permitting current and
legacy software to operate normally.
PCI Express* Interface
The Ibex Peak provides up to 8 PCI Express Root Ports, supporting the PCI Express Base Specification, Revision
2.0. Each Root Port supports 2.5 GB/s bandwidth in each direction (5 GB/s concurrent). PCI Express Root Ports 1-4
can be statically configured as four x1 Ports or ganged together to form one x4 port. Ports 5 and 6 can only be used
as two x1 ports.
Serial ATA (SATA) Controller
The Ibex Peak has two integrated SATA host controllers that support independent DMA operation on up to six ports
and supports data transfer rates of up to 3.0 GB/s (300 MB/s). The SATA controller contains two modes of
operation – a legacy mode using I/O space, and an AHCI mode using memory space. Software that uses legacy
mode will not have AHCI capabilities. The Ibex Peak supports the Serial ATA Specification, Revision 1.0a. The
Ibex Peak also supports several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0 Specification,
Revision 1.0 (AHCI support is required for some elements).