Hitachi F-ZTAT H8/3039 Series User manual

Hitachi Single-Chip Microcomputer
H8/3039 Series
H8/3039, H8/3038
H8/3037, H8/3036
H8/3039 F-ZTATTM
Hardware Manual
ADE-602-131A
Rev. 2.0
1/12/98
Hitachi,Ltd

Preface
The H8/3039 Series comprises high-performance single-chip microcomputers (MCUs) that
integrate system supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, I/O ports, and other facilities. Of the two SCI
channels, one has been expanded to support the ISO/IEC 7816-3 smart card interface. Functions
have also been added to reduce power consumption in battery-powered applications: individual
modules can be placed in standby, and the frequency of the system clock supplied to the chip can
be divided down under software control.
The five MCU operating modes offer a choice of expanded mode, single-chip mode, and address
space size, enabling the H8/3039 Series to adapt quickly and flexibly to a variety of conditions.
In addition to its masked-ROM versions, the H8/3039 Series has an F-ZTATTM* version with user
programmable on-chip flash memory that can be programmed on-board. These versions enable
users to respond quickly and flexibly to changing application specifications.
This manual describes the H8/3039 Series hardware. For details of the instruction set, refer to the
H8/300H Series Programming Manual.

i
Contents
Section 1 Overview........................................................................................................... 1
1.1 Overview............................................................................................................................ 1
1.2 Block Diagram................................................................................................................... 5
1.3 Pin Description.................................................................................................................. 6
1.3.1 Pin Arrangement .................................................................................................. 6
1.3.2 Pin Functions........................................................................................................ 7
1.4 Pin Functions..................................................................................................................... 11
Section 2 CPU..................................................................................................................... 15
2.1 Overview............................................................................................................................ 15
2.1.1 Features ................................................................................................................ 15
2.1.2 Differences from H8/300 CPU............................................................................. 16
2.2 CPU Operating Modes ...................................................................................................... 17
2.3 Address Space.................................................................................................................... 18
2.4 Register Configuration ...................................................................................................... 19
2.4.1 Overview.............................................................................................................. 19
2.4.2 General Registers.................................................................................................. 20
2.4.3 Control Registers.................................................................................................. 21
2.4.4 Initial CPU Register Values ................................................................................. 22
2.5 Data Formats...................................................................................................................... 23
2.5.1 General Register Data Formats ............................................................................ 23
2.5.2 Memory Data Formats.......................................................................................... 24
2.6 Instruction Set.................................................................................................................... 26
2.6.1 Instruction Set Overview...................................................................................... 26
2.6.2 Instructions and Addressing Modes ..................................................................... 27
2.6.3 Tables of Instructions Classified by Function...................................................... 29
2.6.4 Basic Instruction Formats..................................................................................... 39
2.6.5 Notes on Use of Bit Manipulation Instructions.................................................... 40
2.7 Addressing Modes and Effective Address Calculation..................................................... 40
2.7.1 Addressing Modes................................................................................................ 40
2.7.2 Effective Address Calculation.............................................................................. 43
2.8 Processing States ............................................................................................................... 47
2.8.1 Overview.............................................................................................................. 47
2.8.2 Program Execution State...................................................................................... 48
2.8.3 Exception-Handling State .................................................................................... 48
2.8.4 Exception-Handling Sequences............................................................................ 50
2.8.5 Reset State............................................................................................................ 51
2.8.6 Power-Down State................................................................................................ 51
2.9 Basic Operational Timing.................................................................................................. 52

ii
2.9.1 Overview.............................................................................................................. 52
2.9.2 On-Chip Memory Access Timing........................................................................ 52
2.9.3 On-Chip Supporting Module Access Timing....................................................... 53
2.9.4 Access to External Address Space ....................................................................... 54
Section 3 MCU Operating Modes............................................................................... 55
3.1 Overview............................................................................................................................ 55
3.1.1 Operating Mode Selection.................................................................................... 55
3.1.2 Register Configuration ......................................................................................... 56
3.2 Mode Control Register (MDCR)....................................................................................... 57
3.3 System Control Register (SYSCR).................................................................................... 58
3.4 Operating Mode Descriptions............................................................................................ 60
3.4.1 Mode 1.................................................................................................................. 60
3.4.2 Mode 3.................................................................................................................. 60
3.4.3 Mode 5.................................................................................................................. 60
3.4.4 Mode 6.................................................................................................................. 60
3.4.5 Mode 7.................................................................................................................. 60
3.5 Pin Functions in Each Operating Mode............................................................................. 61
3.6 Memory Map in Each Operating Mode............................................................................. 61
3.7 Restrictions on Use of Mode 6.......................................................................................... 70
Section 4 Exception Handling...................................................................................... 73
4.1 Overview............................................................................................................................ 73
4.1.1 Exception Handling Types and Priority............................................................... 73
4.1.2 Exception Handling Operation............................................................................. 73
4.1.3 Exception Vector Table........................................................................................ 74
4.2 Reset.................................................................................................................................. 76
4.2.1 Overview.............................................................................................................. 76
4.2.2 Reset Sequence..................................................................................................... 76
4.2.3 Interrupts after Reset............................................................................................ 78
4.3 Interrupts............................................................................................................................ 78
4.4 Trap Instruction ................................................................................................................. 79
4.5 Stack Status after Exception Handling.............................................................................. 79
4.6 Notes on Stack Usage........................................................................................................ 80
Section 5 Interrupt Controller....................................................................................... 81
5.1 Overview............................................................................................................................ 81
5.1.1 Features ................................................................................................................ 81
5.1.2 Block Diagram...................................................................................................... 82
5.1.3 Pin Configuration ................................................................................................. 83
5.1.4 Register Configuration ......................................................................................... 83
5.2 Register Descriptions......................................................................................................... 84
5.2.1 System Control Register (SYSCR) ...................................................................... 84

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5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 86
5.2.3 IRQ Status Register (ISR).................................................................................... 91
5.2.4 IRQ Enable Register (IER) .................................................................................. 92
5.2.5 IRQ Sense Control Register (ISCR)..................................................................... 93
5.3 Interrupt Sources................................................................................................................ 94
5.3.1 External Interrupts................................................................................................ 94
5.3.2 Internal Interrupts................................................................................................. 95
5.3.3 Interrupt Vector Table.......................................................................................... 95
5.4 Interrupt Operation............................................................................................................ 98
5.4.1 Interrupt Handling Process................................................................................... 98
5.4.2 Interrupt Sequence................................................................................................ 103
5.4.3 Interrupt Response Time...................................................................................... 104
5.5 Usage Notes....................................................................................................................... 105
5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction...................... 105
5.5.2 Instructions that Inhibit Interrupts........................................................................ 106
5.5.3 Interrupts during EEPMOV Instruction Execution.............................................. 106
5.5.4 Usage Notes.......................................................................................................... 106
Section 6 Bus Controller................................................................................................ 109
6.1 Overview............................................................................................................................ 109
6.1.1 Features ................................................................................................................ 109
6.1.2 Block Diagram...................................................................................................... 110
6.1.3 Input/Output Pins.................................................................................................. 111
6.1.4 Register Configuration ......................................................................................... 111
6.2 Register Descriptions......................................................................................................... 112
6.2.1 Access State Control Register (ASTCR).............................................................. 112
6.2.2 Wait Control Register (WCR).............................................................................. 113
6.2.3 Wait State Controller Enable Register (WCER).................................................. 114
6.2.4 Address Control Register (ADRCR).................................................................... 115
6.3 Operation ........................................................................................................................... 117
6.3.1 Area Division........................................................................................................ 117
6.3.2 Bus Control Signal Timing .................................................................................. 119
6.3.3 Wait Modes .......................................................................................................... 121
6.3.4 Interconnections with Memory (Example) .......................................................... 127
6.4 Usage Notes....................................................................................................................... 129
6.4.1 Register Write Timing.......................................................................................... 129
6.4.2 Precautions on setting ASTCR and ABWCR* .................................................... 129
Section 7 I/O Ports ........................................................................................................... 131
7.1 Overview............................................................................................................................ 131
7.2 Port 1.................................................................................................................................. 135
7.2.1 Overview.............................................................................................................. 135
7.2.2 Register Descriptions............................................................................................ 135

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7.2.3 Pin Functions in Each Mode ................................................................................ 137
7.3 Port 2.................................................................................................................................. 139
7.3.1 Overview.............................................................................................................. 139
7.3.2 Register Descriptions............................................................................................ 140
7.3.3 Pin Functions in Each Mode ................................................................................ 142
7.3.4 Input Pull-Up Transistors..................................................................................... 144
7.4 Port 3.................................................................................................................................. 145
7.4.1 Overview.............................................................................................................. 145
7.4.2 Register Descriptions............................................................................................ 145
7.4.3 Pin Functions in Each Mode ................................................................................ 147
7.5 Port 5.................................................................................................................................. 148
7.5.1 Overview.............................................................................................................. 148
7.5.2 Register Descriptions............................................................................................ 148
7.5.3 Pin Functions in Each Mode ................................................................................ 151
7.5.4 Input Pull-Up Transistors..................................................................................... 152
7.6 Port 6.................................................................................................................................. 153
7.6.1 Overview.............................................................................................................. 153
7.6.2 Register Descriptions............................................................................................ 153
7.6.3 Pin Functions in Each Mode ................................................................................ 155
7.7 Port 7.................................................................................................................................. 158
7.7.1 Overview.............................................................................................................. 158
7.7.2 Register Description............................................................................................. 158
7.8 Port 8.................................................................................................................................. 159
7.8.1 Overview.............................................................................................................. 159
7.8.2 Register Descriptions............................................................................................ 160
7.8.3 Pin Functions........................................................................................................ 161
7.9 Port 9.................................................................................................................................. 162
7.9.1 Overview.............................................................................................................. 162
7.9.2 Register Descriptions............................................................................................ 162
7.9.3 Pin Functions........................................................................................................ 163
7.10 Port A................................................................................................................................. 166
7.10.1 Overview.............................................................................................................. 166
7.10.2 Register Descriptions............................................................................................ 167
7.10.3 Pin Functions........................................................................................................ 169
7.11 Port B................................................................................................................................. 176
7.11.1 Overview.............................................................................................................. 176
7.11.2 Register Descriptions............................................................................................ 176
7.11.3 Pin Functions........................................................................................................ 178
Section 8 16-Bit Integrated Timer Unit (ITU).......................................................... 185
8.1 Overview............................................................................................................................ 185
8.1.1 Features ................................................................................................................ 185
8.1.2 Block Diagrams.................................................................................................... 188

v
8.1.3 Input/Output Pins.................................................................................................. 193
8.1.4 Register Configuration ......................................................................................... 195
8.2 Register Descriptions......................................................................................................... 198
8.2.1 Timer Start Register (TSTR)................................................................................ 198
8.2.2 Timer Synchro Register (TSNC).......................................................................... 199
8.2.3 Timer Mode Register (TMDR) ............................................................................ 201
8.2.4 Timer Function Control Register (TFCR)............................................................ 204
8.2.5 Timer Output Master Enable Register (TOER).................................................... 206
8.2.6 Timer Output Control Register (TOCR).............................................................. 209
8.2.7 Timer Counters (TCNT)....................................................................................... 210
8.2.8 General Registers (GRA, GRB)........................................................................... 211
8.2.9 Buffer Registers (BRA, BRB).............................................................................. 212
8.2.10 Timer Control Registers (TCR)............................................................................ 213
8.2.11 Timer I/O Control Register (TIOR) ..................................................................... 216
8.2.12 Timer Status Register (TSR)................................................................................ 218
8.2.13 Timer Interrupt Enable Register (TIER).............................................................. 220
8.3 CPU Interface.................................................................................................................... 222
8.3.1 16-Bit Accessible Registers.................................................................................. 222
8.3.2 8-Bit Accessible Registers ................................................................................... 224
8.4 Operation ........................................................................................................................... 225
8.4.1 Overview.............................................................................................................. 225
8.4.2 Basic Functions .................................................................................................... 226
8.4.3 Synchronization.................................................................................................... 236
8.4.4 PWM Mode.......................................................................................................... 238
8.4.5 Reset-Synchronized PWM Mode......................................................................... 242
8.4.6 Complementary PWM Mode ............................................................................... 245
8.4.7 Phase Counting Mode .......................................................................................... 255
8.4.8 Buffering .............................................................................................................. 257
8.4.9 ITU Output Timing .............................................................................................. 264
8.5 Interrupts............................................................................................................................ 266
8.5.1 Setting of Status Flags.......................................................................................... 266
8.5.2 Clearing of Status Flags........................................................................................ 268
8.5.3 Interrupt Sources .................................................................................................. 269
8.6 Usage Notes....................................................................................................................... 270
Section 9 Programmable Timing Pattern Controller.............................................. 285
9.1 Overview............................................................................................................................ 285
9.1.1 Features ................................................................................................................ 285
9.1.2 Block Diagram...................................................................................................... 286
9.1.3 TPC Pins............................................................................................................... 287
9.1.4 Registers............................................................................................................... 288
9.2 Register Descriptions......................................................................................................... 289
9.2.1 Port A Data Direction Register (PADDR) ........................................................... 289

vi
9.2.2 Port A Data Register (PADR)..............................................................................289
9.2.3 Port B Data Direction Register (PBDDR)............................................................290
9.2.4 Port B Data Register (PBDR)...............................................................................290
9.2.5 Next Data Register A (NDRA)............................................................................291
9.2.6 Next Data Register B (NDRB).............................................................................293
9.2.7 Next Data Enable Register A (NDERA)..............................................................295
9.2.8 Next Data Enable Register B (NDERB)..............................................................296
9.2.9 TPC Output Control Register (TPCR).................................................................297
9.2.10TPC Output Mode Register (TPMR)...................................................................300
9.3 Operation...........................................................................................................................302
9.3.1 Overview..............................................................................................................302
9.3.2 Output Timing......................................................................................................303
9.3.3 Normal TPC Output.............................................................................................304
9.3.4 Non-Overlapping TPC Output.............................................................................306
9.3.5 TPC Output Triggering by Input Capture............................................................308
9.4 Usage Notes.......................................................................................................................309
9.4.1 Operation of TPC Output Pins.............................................................................309
9.4.2 Note on Non-Overlapping Output........................................................................309
Section 10 Watchdog Timer............................................................................................311
10.1Overview............................................................................................................................311
10.1.1Features...................................................................................................................311
10.1.2Block Diagram......................................................................................................312
10.1.3Pin Configuration.................................................................................................312
10.1.4Register Configuration.........................................................................................313
10.2Register Descriptions.........................................................................................................314
10.2.1Timer Counter (TCNT)........................................................................................314
10.2.2Timer Control/Status Register (TCSR)................................................................315
10.2.3Reset Control/Status Register (RSTCSR)............................................................317
10.2.4Notes on Register Access.....................................................................................319
10.3Operation...........................................................................................................................321
10.3.1Watchdog Timer Operation..................................................................................321
10.3.2Interval Timer Operation......................................................................................322
10.3.3Timing of Setting of Overflow Flag (OVF).........................................................323
10.3.4Timing of Setting of Watchdog Timer Reset Bit (WRST)..................................324
10.4Interrupts............................................................................................................................325
10.5Usage Notes.......................................................................................................................325
Section 11 Serial Communication Interface...............................................................327
11.1Overview............................................................................................................................327
11.1.1Features................................................................................................................327
11.1.2Block Diagram......................................................................................................329
11.1.3Input/Output Pins..................................................................................................330

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11.1.4 Register Configuration ......................................................................................... 330
11.2 Register Descriptions......................................................................................................... 331
11.2.1 Receive Shift Register (RSR)............................................................................... 331
11.2.2 Receive Data Register (RDR) .............................................................................. 331
11.2.3 Transmit Shift Register (TSR).............................................................................. 332
11.2.4 Transmit Data Register (TDR)............................................................................. 332
11.2.5 Serial Mode Register (SMR)................................................................................ 333
11.2.6 Serial Control Register (SCR).............................................................................. 337
11.2.7 Serial Status Register (SSR)................................................................................. 341
11.2.8 Bit Rate Register (BRR)....................................................................................... 345
11.3 Operation ........................................................................................................................... 354
11.3.1 Overview.............................................................................................................. 354
11.3.2 Operation in Asynchronous Mode........................................................................ 356
11.3.3 Multiprocessor Communication........................................................................... 365
11.3.4 Synchronous Operation........................................................................................ 372
11.4 SCI Interrupts .................................................................................................................... 381
11.5 Usage Notes....................................................................................................................... 382
Section 12 Smart Card Interface .................................................................................... 387
12.1 Overview............................................................................................................................ 387
12.1.1 Features ................................................................................................................ 387
12.1.2 Block Diagram...................................................................................................... 388
12.1.3 Pin Configuration ................................................................................................. 389
12.1.4 Register Configuration ......................................................................................... 389
12.2 Register Descriptions......................................................................................................... 390
12.2.1 Smart Card Mode Register (SCMR).................................................................... 390
12.2.2 Serial Status Register (SSR)................................................................................. 392
12.3 Operation.......................................................................................................................... 394
12.3.1 Overview.............................................................................................................. 394
12.3.2 Pin Connections.................................................................................................... 394
12.3.3 Data Format.......................................................................................................... 396
12.3.4 Register Settings................................................................................................... 398
12.3.5 Clock .................................................................................................................... 400
12.3.6 Data Transfer Operations ..................................................................................... 402
12.4 Usage Note ........................................................................................................................ 408
Section 13 A/D Converter................................................................................................ 411
13.1 Overview............................................................................................................................ 411
13.1.1 Features ................................................................................................................ 411
13.1.2 Block Diagram...................................................................................................... 412
13.1.3 Input Pins.............................................................................................................. 413
13.1.4 Register Configuration ......................................................................................... 414
13.2 Register Descriptions......................................................................................................... 415

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13.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 415
13.2.2 A/D Control/Status Register (ADCSR)................................................................ 416
13.2.3 A/D Control Register (ADCR)............................................................................. 419
13.3 CPU Interface.................................................................................................................... 420
13.4 Operation ........................................................................................................................... 421
13.4.1 Single Mode (SCAN = 0)..................................................................................... 421
13.4.2 Scan Mode (SCAN = 1) ....................................................................................... 423
13.4.3 Input Sampling and A/D Conversion Time.......................................................... 425
13.4.4 External Trigger Input Timing ............................................................................. 426
13.5 Interrupts............................................................................................................................ 427
13.6 Usage Notes....................................................................................................................... 427
Section 14 RAM.................................................................................................................. 433
14.1 Overview............................................................................................................................ 433
14.1.1 Block Diagram...................................................................................................... 434
14.1.2 Register Configuration ......................................................................................... 434
14.2 System Control Register (SYSCR).................................................................................... 435
14.3 Operation ........................................................................................................................... 436
Section 15 ROM.................................................................................................................. 437
15.1 Overview............................................................................................................................ 437
15.2 Overview of Flash Memory............................................................................................... 438
15.2.1 Features ................................................................................................................ 438
15.2.2 Block Diagram...................................................................................................... 439
15.2.3 Pin Configuration ................................................................................................. 440
15.2.4 Register Configuration ......................................................................................... 440
15.3 Register Descriptions......................................................................................................... 441
15.3.1 Flash Memory Control Register (FLMCR).......................................................... 441
15.3.2 Erase Block Register (EBR)................................................................................. 445
15.3.3 RAM Control Register (RAMCR) ....................................................................... 446
15.3.4 Flash Memory Status Register (FLMSR)............................................................. 448
15.4 On-Board Programming Modes........................................................................................ 449
15.4.1 Boot Mode............................................................................................................ 452
15.4.2 User Program Mode ............................................................................................. 457
15.5 Programming/Erasing Flash Memory................................................................................ 459
15.5.1 Program Mode...................................................................................................... 460
15.5.2 Program-Verify Mode.......................................................................................... 461
15.5.3 Erase Mode........................................................................................................... 463
15.5.4 Erase-Verify Mode............................................................................................... 463
15.6 Flash Memory Protection.................................................................................................. 465
15.6.1 Hardware Protection............................................................................................. 465
15.6.2 Software Protection.............................................................................................. 467
15.6.3 Error Protection.................................................................................................... 467

ix
15.6.4 NMI Input Disable Conditions............................................................................. 469
15.7 Flash Memory Emulation by RAM................................................................................... 470
15.8 Flash Memory PROM Mode............................................................................................. 471
15.8.1 PROM Mode Setting............................................................................................ 471
15.8.2 Memory Map........................................................................................................ 471
15.8.3 PROM Mode Operation ....................................................................................... 472
15.8.4 Memory Read Mode............................................................................................. 474
15.8.5 Auto-Program Mode ............................................................................................ 477
15.8.6 Auto-Erase Mode.................................................................................................. 479
15.8.7 Status Read Mode................................................................................................. 481
15.8.8 PROM Mode Transition Time.............................................................................. 482
15.8.9 Notes On Memory Programming......................................................................... 483
15.9 Notes on Flash Memory Programming/Erasing................................................................ 484
15.10 Mask ROM Overview........................................................................................................ 489
15.10.1 Block Diagram...................................................................................................... 489
15.11 Notes on Ordering Mask ROM Version Chip .................................................................. 490
Section 16 Clock Pulse Generator .................................................................................. 491
16.1 Overview............................................................................................................................ 491
16.1.1 Block Diagram...................................................................................................... 492
16.2 Oscillator Circuit ............................................................................................................... 493
16.2.1 Connecting a Crystal Resonator........................................................................... 493
16.2.2 External Clock Input ............................................................................................ 495
16.3 Duty Adjustment Circuit.................................................................................................... 498
16.4 Prescalers........................................................................................................................... 498
16.5 Frequency Divider............................................................................................................. 498
16.5.1 Register Configuration ......................................................................................... 498
16.5.2 Division Control Register (DIVCR) .................................................................... 499
16.5.3 Usage Notes.......................................................................................................... 499
Section 17 Power-Down State.......................................................................................... 501
17.1 Overview............................................................................................................................ 501
17.2 Register Configuration ...................................................................................................... 503
17.2.1 System Control Register (SYSCR) ...................................................................... 503
17.2.2 Module Standby Control Register (MSTCR)....................................................... 505
17.3 Sleep Mode........................................................................................................................ 507
17.3.1 Transition to Sleep Mode ..................................................................................... 507
17.3.2 Exit from Sleep Mode .......................................................................................... 507
17.4 Software Standby Mode.................................................................................................... 508
17.4.1 Transition to Software Standby Mode.................................................................. 508
17.4.2 Exit from Software Standby Mode....................................................................... 508
17.4.3 Selection of Oscillator Waiting Time after Exit from Software Standby Mode.. 509
17.4.4 Sample Application of Software Standby Mode.................................................. 510

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17.4.5 Usage Note ........................................................................................................... 510
17.5 Hardware Standby Mode................................................................................................... 511
17.5.1 Transition to Hardware Standby Mode................................................................ 511
17.5.2 Exit from Hardware Standby Mode ..................................................................... 511
17.5.3 Timing for Hardware Standby Mode ................................................................... 511
17.6 Module Standby Function.................................................................................................. 512
17.6.1 Module Standby Timing....................................................................................... 512
17.6.2 Read/Write in Module Standby............................................................................ 512
17.6.3 Usage Notes.......................................................................................................... 512
17.7 System Clock Output Disabling Function......................................................................... 513
Section 18 Electrical Characteristics.............................................................................. 515
18.1 Electrical characteristics of Masked ROM Version.......................................................... 515
18.1.1 Absolute Maximum Ratings................................................................................. 515
18.1.2 DC Characteristics................................................................................................ 516
18.1.3 AC Characteristics................................................................................................ 527
18.1.4 A/D Conversion Characteristics........................................................................... 533
18.2 Electrical characteristics of Flash Memory Version.......................................................... 534
18.2.1 Absolute Maximum Ratings................................................................................. 534
18.2.2 DC Characteristics................................................................................................ 535
18.2.3 AC Characteristics................................................................................................ 542
18.2.4 A/D Conversion Characteristics........................................................................... 548
18.2.5 Flash Memory Characteristics.............................................................................. 549
18.3 Operational Timing............................................................................................................ 551
18.3.1 Bus Timing........................................................................................................... 551
18.3.2 Control Signal Timing.......................................................................................... 555
18.3.3 Clock Timing........................................................................................................ 557
18.3.4 TPC and I/O Port Timing..................................................................................... 557
18.3.5 ITU Timing .......................................................................................................... 558
18.3.6 SCI Input/Output Timing ..................................................................................... 559
Appendix A Instruction Set................................................................................................. 561
A.1 Instruction List................................................................................................................... 561
A.2 Operation Code Maps....................................................................................................... 576
A.3 Number of States Required for Execution......................................................................... 579
Appendix B Internal I/O Register Field.......................................................................... 589
B.1 Addresses........................................................................................................................... 589
B.2 Function............................................................................................................................. 597
Appendix C I/O Block Diagrams...................................................................................... 655
C.1 Port 1 Block Diagram........................................................................................................ 655
C.2 Port 2 Block Diagram........................................................................................................ 656

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C.3 Port 3 Block Diagram........................................................................................................ 657
C.4 Port 5 Block Diagram........................................................................................................ 658
C.5 Port 6 Block Diagram........................................................................................................ 659
C.6 Port 7 Block Diagram........................................................................................................ 661
C.7 Port 8 Block Diagram........................................................................................................ 662
C.8 Port 9 Block Diagram........................................................................................................ 664
C.9 Port A Block Diagram....................................................................................................... 668
C.10 Port B Block Diagram ....................................................................................................... 671
Appendix DPin States........................................................................................................... 674
D.1 Port States in Each Mode .................................................................................................. 674
D.2 Pin States at Reset.............................................................................................................. 676
Appendix E Timing of Transition to and Recovery
from Hardware Standby Mode................................................................... 679
Appendix F Product Code Lineup.................................................................................... 680
Appendix G Package Dimensions..................................................................................... 681

1
Section 1 Overview
1.1 Overview
The H8/3039 Series comprises microcomputers (MCUs) that integrate system supporting
functions together with an H8/300H CPU core featuring an original Hitachi architecture.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU,
enabling easy porting of software from the H8/300 Series.
The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit
(ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial
communication interface (SCI), an A/D converter, I/O ports, and other facilities.
The H8/3039 Series consists of four models: the H8/3039 with 128 kbytes of ROM and 4 kbytes
of RAM, the H8/3038 with 64 kbytes of ROM and 2 kbytes of RAM, the H8/3037 with 32 kbytes
of ROM and 1 kbytes of RAM, and the H8/3036 with 16 kbytes of ROM and 512 bytes of RAM.
The five MCU operating modes offer a choice of expanded mode, single-chip mode and address
space size.
In addition to the masked-ROM version of the H8/3039 Series, an F-ZTATTM* version with an on-
chip flash memory that can be freely programmed and reprogrammed by the user after the board is
installed is also available. This version enables users to respond quickly and flexibly to changing
application specifications, growing production volumes, and other conditions.
Table 1-1 summarizes the features of the H8/3039 Series.
Note: * F-ZTAT (Flexible ZTAT) is a trademark of Hitachi, Ltd.

2
Table 1-1 Features
Feature Description
CPU Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
• Sixteen 16-bit general registers
(also useable as sixteen 8-bit registers or eight 32-bit registers)
High-speed operation
• Maximum clock rate: 18 MHz
• Add/subtract: 111 ns
• Multiply/divide: 778 ns
Two CPU operating modes
• Normal mode (64-kbyte address space)
• Advanced mode (16-Mbyte address space)
Instruction features
• 8/16/32-bit data transfer, arithmetic, and logic instructions
• Signed and unsigned multiply instructions (8 bits ×8 bits, 16 bits ×16 bits)
• Signed and unsigned divide instructions (16 bits ÷8 bits, 32 bits ÷16 bits)
• Bit accumulator function
• Bit manipulation instructions with register-indirect specification of bit positions
Memory H8/3039
• ROM: 128 kbytes
• RAM: 4 kbytes
H8/3038
• ROM: 64 kbytes
• RAM: 2 kbytes
H8/3037
• ROM: 32 kbytes
• RAM: 1 kbyte
H8/3036
• ROM: 16 kbytes
• RAM: 512 bytes
Interrupt • Five external interrupt pins: NMI, IRQ0, IRQ1, IRQ4, IRQ5
controller • 25 internal interrupts
• Three selectable interrupt priority levels
Bus controller • Address space can be partitioned into eight areas, with independent bus
specifications in each area
• Two-state or three-state access selectable for each area
• Selection of four wait modes

3
Table 1-1 Features (cont)
Feature Description
16-bit integrated
timer unit (ITU) • Five 16-bit timer channels, capable of processing up to 12 pulse outputs or 10
pulse inputs
• 16-bit timer counter (channels 0 to 4)
• Two multiplexed output compare/input capture pins (channels 0 to 4)
• Operation can be synchronized (channels 0 to 4)
• PWM mode available (channels 0 to 4)
• Phase counting mode available (channel 2)
• Buffering available (channels 3 and 4)
• Reset-synchronized PWM mode available (channels 3 and 4)
• Complementary PWM mode available (channels 3 and 4)
Programmable • Maximum 15-bit pulse output, using ITU as time base
timing pattern
controller (TPC)
• Up to three 4-bit pulse output groups and one 3-bit pulse output group (or one 15-
bit group, one 8-bit group, or one 7-bit group)
• Non-overlap mode available
Watchdog timer • Reset signal can be generated by overflow
(WDT), 1 channel • Reset signal can be output externally (However, not available with the F-ZTAT
version.)
• Usable as an interval timer
Serial • Selection of asynchronous or synchronous mode
communication • Full duplex: can transmit and receive simultaneously
interface (SCI), • On-chip baud-rate generator
2 channels • Smart card interface functions added (SCI0 only)
A/D converter • Resolution: 10 bits
• Eight channels, with selection of single or scan mode
• Variable analog conversion voltage range
• Sample-and-hold function
• Can be externally triggered
I/O ports • 55 input/output pins
• 8 input-only pins
Operating modes Five MCU operating modes
Mode Address Space Address Pins Bus Width
Mode 1 1 Mbyte A0to A19 8 bits
Mode 3 16 Mbytes A23 to A08 bits
Mode 5 1 Mbyte A0to A19 8 bits
Mode 6 64 kbytes — —
Mode 7 1 Mbyte — —
• On-chip ROM is disabled in modes 1 and 3

4
Table 1-1 Features (cont)
Feature Description
Power-down • Sleep mode
state • Software standby mode
• Hardware standby mode
• Module standby function
• Programmable System clock frequency division
Other features • On-chip clock oscillator
Product lineup Model (5V) Model (3V)*Package ROM
HD64F3039F HD64F3039VF 80-pin QFP
(FP-80A) Flash memory
HD64F3039TE HD64F3039VTE 80-pin TQFP
(TFP-80C)
HD6433039F HD6433039VF 80-pin QFP
(FP-80A) Mask ROM
HD6433039TE HD6433039VTE 80-pin TQFP
(TFP-80C)
HD6433038F HD6433038VF 80-pin QFP
(FP-80A) Mask ROM
HD6433038TE HD6433038VTE 80-pin TQFP
(TFP-80C)
HD6433037F HD6433037VF 80-pin QFP
(FP-80A) Mask ROM
HD6433037TE HD6433037VTE 80-pin TQFP
(TFP-80C)
HD6433036F HD6433036VF 80-pin QFP
(FP-80A) Mask ROM
HD6433036TE HD6433036VTE 80-pin TQFP
(TFP-80C)
Note: *There are two 3 V versions: one with VCC = 2.7 V to 5.5 V and ø = 2 to 8 MHz, and one
with VCC = 3.0 V to 5.5 V and ø = 2 to 10 MHz. However, there is only one flash memory
version, with VCC = 3.0 to 5.5 V and ø = 2 to 10 MHz.

5
1.2 Block Diagram
Figure 1-1 shows an internal block diagram of the H8/3039 Series.
P77/AN7 P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0
AVCC
AVSS
PA7/TP7/TIOCB2/A20 PA6/TP6/TIOCA2/A21 PA5/TP5/TIOCB1/A22 PA4/TP4/TIOCA1/A23
PA3/TP3/TIOCB0/TCLKD
PA2/TP2/TIOCA0/TCLKC
PA1/TP1/TCLKB
PA0/TP0/TCLKA
PB7/TP15/ADTRG
PB5/TP13/TOCXB4
PB4/TP12/TOCXA4
PB3/TP11/TIOCB4 PB2/TP10/TIOCA4
PB1/TP9/TIOCB3 PB0/TP8/TIOCA3
P27/A15
P26/A14
P25/A13
P24/A12
P23/A11
P22/A10
P21/A9
P20/A8
P17/A7
P16/A6
P15/A5
P14/A4
P13/A3
P12/A2
P11/A1
P10/A0
P95/SCK1/IRQ5
P94/SCK0/IRQ4
P93/RxD1
P92/RxD0
P91/TxD1
P90/TxD0
P53/A19
P52/A18
P51/A17
P50/A16
Data bus (lower)
Bus
controller
Clock osc.
H8/300H CPU
ROM
(Flash memory,
masked ROM)
RAM
16-bit
integrated
timer unit
(ITU)
Programmable
timing pattern
controller (TPC)
Interrupt
controller
Serial
communication
interface
(SCI) ×2 channel
Watchdog
timer
(WDT)
A/D converter
Port 3
P65/WR
P64/RD
P63/AS
P60/WAIT
P81/IRQ1
P80/IRQ0
MD1
MD0
EXTAL
XTAL
ø
STBY
RES
RESO/FWE*
NMI
VCC VCC
VSS VSS VSS
P37/D7 P36/D6 P35/D5 P34/D4 P33/D3 P32/D2 P31/D1 P30/D0
Port 2Port 1 Port 5
Port 9
Port 7Port APort B
Note: *Masked ROM : RESO
Flash memor
y
: FWE
Port 8 Port 6
Address bus
Data bus (upper)
MD2
Figure 1-1 Block Diagram

6
1.3 Pin Description
1.3.1 Pin Arrangement
Figure 1-2 shows the pin arrangement of the H8/3039 Series.
P71/AN1
P70/AN0
AVSS
RESO/FWE*
P65/WR
P64/RD
P63/AS
VCC
XTAL
EXTAL
VSS
NMI
RES
STBY
ø
MD1
MD0
P60/WAIT
P53/A19
P52/A18
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
TIOCA3/TP8/PB0
TIOCB3/TP9/PB1
TIOCA4/TP10/PB2
TIOCB4/TP11/PB3
TOCXA4/TP12/PB4
TOCXB4/TP13/PB5
MD2
ADTRG/TP15/PB7
TxD0/P90
RxD0/P92
IRQ4/SCK0/P94
VSS
D0/P30
D1/P31
D2/P32
D3/P33
D4/P34
D5/P35
D6/P36
D7/P37
PA7/TP7/TIOCB2/A20 PA6/TP6/TIOCA2/A21 PA5/TP5/TIOCB1/A22 PA4/TP4/TIOCA1/A23 PA3/TP3/TIOCB0/TCLKD
PA2/TP2/TIOCA0/TCLKC PA1/TP1/TCLKB
PA0/TP0/TCLKA P95/SCK1/IRQ5
P93/RxD1 P91/TxD1 P81/IRQ1 P80/IRQ0 AVcc P77/AN7 P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2
VCC
A0/P10 A1/P11 A2/P12 A3/P13 A4/P14 A5/P15 A6/P16 A7/P17
VSS
A8/P20 A9/P21
A10/P22 A11/P23 A12/P24 A13/P25 A14/P26 A15/P27 A16/P50 A17/P51
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Top view
(FP-80A, TFP-80C)
Note: *Masked ROM: RESO
Flash memory: FWE
Figure 1-2 Pin Arrangement (FP-80A, TFP-80C Top View)

7
1.3.2 Pin Functions
Pin Assignments in Each Mode: Table 1-2 lists the FP-80A and TFP-80C pin assignments in
each mode.
Table 1-2 FP-80A and TFP-80C Pin Assignments in Each Mode
Pin Name
Pin
No. Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 PROM Mode Flashmemory
1PB
0
/TP8/
TIOCA3
PB0/TP8/
TIOCA3
PB0/TP8/
TIOCA3
PB0/TP8/
TIOCA3
PB0/TP8/
TIOCA3
NC
2PB
1
/TP9/
TIOCB3
PB1/TP9/
TIOCB3
PB1/TP9/
TIOCB3
PB1/TP9/
TIOCB3
PB1/TP9/
TIOCB3
NC
3PB
2
/TP10/
TIOCA4
PB2/TP10/
TIOCA4
PB2/TP10/
TIOCA4
PB2/TP10/
TIOCA4
PB2/TP10/
TIOCA4
NC
4PB
3
/TP11/
TIOCB4
PB3/TP11/
TIOCB4
PB3/TP11/
TIOCB4
PB3/TP11/
TIOCB4
PB3/TP11/
TIOCB4
NC
5PB
4
/TP12/
TOCXA4
PB4/TP12/
TOCXA4
PB4/TP12/
TOCXA4
PB4/TP12/
TOCXA4
PB4/TP12/
TOCXA4
NC
6PB
5
/TP13/
TOCXB4
PB5/TP13/
TOCXB4
PB5/TP13/
TOCXB4
PB5/TP13/
TOCXB4
PB5/TP13/
TOCXB4
NC
7MD
2MD2MD2MD2MD2VSS
8PB
7
/TP15/
ADTRG PB7/TP15/ ADTRG PB7/TP15/ ADTRG PB7/TP15/ ADTRG PB7/TP15/ ADTRG NC
9P9
0
/TxD0P90/TxD0P90/TxD0P90/TxD0P90/TxD0NC
10 P92/RxD0P92/RxD0P92/RxD0P92/RxD0P92/RxD0VSS
11 P94/SCK0/
IRQ4
P94/SCK0/
IRQ4
P94/SCK0/
IRQ4
P94/SCK0/
IRQ4
P94/SCK0/
IRQ4
NC
12 VSS VSS VSS VSS VSS VSS
13 D0D0D0P30P30I/O0
14 D1D1D1P31P31I/O1
15 D2D2D2P32P32I/O2
16 D3D3D3P33P33I/O3
17 D4D4D4P34P34I/O4
18 D5D5D5P35P35I/O5
19 D6D6D6P36P36I/O6
20 D7D7D7P37P37I/O7