HP 13220 Manual

P f' () c: ~?~:;~:; () T' Mod u1e
Manual Part No. 13220-91087
REVISED
JAN··· () 4····B2
DATA TERMINAL
TECHNICAL INFORMATION
HEWLETT~PACKARD
Printed in U.S.A.

P f' 0 c (~~:; ~:; 0 7' M () d u1e
Manual Part No. 13220-91087
I~EVISED
JAN··· () 4····0t?
NOTICE
The inforMation contained in this dOCUMent is subject to change
w:i.ti"lou"t notic€~.
HEWl..ETT····Pt-.CI{ARD t'\AI{EB NO WARI~ANTY OF ANY I{IND WITH '~EGAI~l) TO THIS
MATERIAL, INCLUDING, BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Hewlett-Packard
shall not be liable for errors contained herein or for incidental or
con~)f:~quf.·!n·t:i.al dat ... aqE~s in c()nn~:~ction with th(·! fUl'nis;hinq, ~)E~l'for'Manc:~?,
or use of this Material.
This dOCUMent contains proprietary inforMation which is protected by
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photocopied or reproduced without the prior written consent of Hewlett-
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NOTE: Thi~:; docuME!nt is par't of th(~ ~?'6;:~XX DATA TERMINAl... pr'oduct
~:) 0! r' :i. f:·! s T f..! C hn i cal I n for' Mat ion Pi:\ c: ka (J f! (HP j.3 ;:~ ;:? () ) .

i.O IN"l"RODUCTION
The 02620-60087 Processor PCA perforMs the terMinal logic functions for
the 2622A terMinal. Its operation is based on the Z80A Microprocessor
and the National SeMiconductor 8367 CRT Controller (CRTC).
The control and I/O section of the Processor PCA provides control
~;> i qna1 ~:> , :i. n put / 0 ut put and d i~ tap roc (~s~:;:i. n(J fun c t j. 0 n~:; . The MeM 0 r' y
section provides 16K bytes of dynaMic RAM for display MeMory, scratch
pad MeMory and data buffers, and space for up to six 4K or 8K byte RUMs
of which 32K are used for COMplete terMinal operation (8K of ROM
optional with integral printer). The video control section provides
all tiMing signals for driving the sweep circuitry and video logic as
well as perforMing direct MeMory access CDMA) of display data. A
detailed description of the operation of each of these sections follows
:i. n ~:;ec t ion 3. 0 .
2.0 OPERATING PARAMETERS.
A SUMMary of operating paraMeters for the Processor Module is contained
in tables 1.0 through 4.0
Table 1.0 Physical ParaMeters
===============================================================================
Par' t Si ze (I... x W x D) 1 W(~ i qh t 1
1 NUI"',IHH' 1 NOMf:·~nclatul'~~ 1 +/ .... 0.1 Inche~; 1 (Pounds> 1
1=============1==============================1=======================1========1
1 I 1 1 1
1 1 1 1 1
1 02620-60087 1 Processor PCA 1 12.3 x 10.9 x O.S 1 1.4 1
1 1 1 1
I 1 1 1
1 1 1 1
===============================================================================

1 :'5;:~:~O
Pl' ()Cf.~<':;~;()l' Mod uIe'
Table 2.0 Reliability and EnvironMental InforMation
1 ~5220 .... f/1 0 H'7 / () ~5
Rev JAN-()4····f32
================:========~======================================================
I
I
I EnvironMental: HP Class B
I
I
I Restrictions: Type tested at product level
I
I
I
I==~===========~==============================================================
I
I Failure Rate: 3.71 (percent per 1000 hours)
I
===================~======~====================================================
Table 3.0 Power Supply RequireMents - Measured
(At +/-5% Unless Otherwise Specified)
===~=============================~=============================================
I
+16 Volt Supply +12 Volt Supply +5 Volt Supply I -12 Volt Supply
I
ill 0 MA @ 200 MA @ 2.0 A I @ SO MA
I
I NOT APPLICABLE I I I I
I ::: ::;: :~: :::: :::::::: :::: :::::::::::: :::::::: :::: :::: :;:: :::: :::::::: :'~::::: :::: :::: :::: :::: :.:::::: :::: :::: :::: :::: :::: :::::-.:::::: :::: :::::::: :::: ::: I =:::::::::::: :::: :::: :::::::: :::: :::::::: :.~::::: :::::::::::: :::: :::: :::::::::::: :::::::::".:: ::::::::::: :::: :::: = :::: = :::: :::: :::::::: =I
I I I
I 115 volts ac I 220 volts ae I
I I I
I ~ A I @. A I
I I I
I NOT APPL.ICABL.E I NOT APPLICABLE I
===============================================================================

13~~2 ()
P f' 0 C £~ ~:; ~:) () f' M () du1e
Table 4.0 Connector InforMation
:1. 3~~~:~ 0···9108'7/04
R (::~ v JAN··· () 4···B;?
===~==========~===~========~===================================================
Connector Signal
1 and P in No. 1 NaM(~
1==============1================
J1 1
Pin ···1
.... 2
.... ~5
.... 4
· .. ··7
.... 8
·-9
1
I
I
1
I
1
1
1
1
\
1
\
\
I
t
1
I
.... :1. 0 I
I
.... :1.1 I
I
.... :1. ;,? t
I
"-L3 t
-14
· .. ·16
.... 1·7
-1t3
-·19
"-20
.... 21
·-22
.. -;~3
-24
"-25
-26
PRINTER
PWI~ ON/FAIL
WRITE
Ai
DATA ()
DATA 1
DATA 2
DATA :5
DATA 4
DATA S
DATA 6
DATA 7
GND
PINT
AO
+SV
+SV
+SV
+SV
GND
GND
GND
GNU
GND
Signal I
Description I
=============================================\
** PRINTER **
Negative True, Printer Strobe
Negative True,Power On/Failing
Negative True, Write signal
Negative True, Fun~tion select bit 1
LSB - Negative True, Data
MSB - Negative True, Data
Set printer contrast
Negative True, Printer Interrupt
Negative True, Function select bit 0
Vcc Power
Power Retul'n

1. ~5~~2()
Pl'OC(~SS)Ol' Module
13220-91.08'7/0S
Rev JAN-()4-B2
Table 4.0 Connector InforMation (Cont'd)
===============================================================================~
I Connector Signal
I and Pin No. I NaMe
Signal
Description
\==============1================ ==============================================
I J;:.~ I
I 1
I Pin -·1
+5V
\ -.~:~
\ -3 +SV
\ -4 +12V
I -S GND
I -6 GND
I .. _ ... _. __ ._ ... _ .. __ .......... _ ...... _.
** POWER SUPPL.Y **
+SV Power
N/C
+5V Power
+1;':'~V Power
R€~t ur'n f 01' Power
Ret urn for' P ow(~r
I -'7 PWR ON/FAIL Negative True, Power On/Failing
\ -8 -1.2V -12V Power
I -9 BATTERY Positive Battery TerMinal
I -10 1 BATRET I Negative Battery TerMinal
I ........................................ - ............ 'I ._.- .... '''' .- ..... - ..................... - •• - .-.- I .. -.-- .- ...... - .- ....... - ............. _.-.- ........... , ..... - .......... -.-.- .. - .... '''' .- ... _.- .... _ .... - ..... - ..... _._.- --'- .. _.- I
I J~3 1 I
I ..... __ .. _. __ .... __ . I
I Pin -1 HLFBRT I
I -2 I
\ -3 RETURN I
\ ........ _ ........... _._._. I
I --4 FUL.L.BI~ T \
\ -5 RETURN I
\ -6 RETURN \
I I
I .... 'J iJ'f~:'ifi)rf I
\ -8 I HORDR I
I ..... - ........ , _ .......... - ........ - ........... -. :1 .......... - ............ - ............... - ............. - •. -
\ J4
\
I
I
I
I
\
I
I
)
Pin .... 1
.... 2
· .. ·3
... -4
· .. ·s
· .. ·6
.... ·7
-·B
· .. ·9
.... 1 ()
····1.1
.... 12
\(EYO
KEYj .
KEY2
KEY:~
I<EY4
KEYS
KEY6
KEYACT
GNI>
BELL..
+Sv
** SWEEP **
Negative true, Half Bright Video
N/C
Return for half bright twisted pair
Negative true, Full Bright Video
Return for Video twisted pair
Return for Drive signals
Negative True, Vertical Drive
Horizontal Drive
** KEYBOARD **
Key
Data
(LSB)
KE~y Data
Key Data
Key Data
Key
Data
N/C
K(~~y
Dc:l ta
)(ey
Data
(MSS)
Key Active (Status of key selected)
Pow(~r Return
Bell Line
+5v Power
================================~===============================================

j. ~5;.:!.2 0
Pr'oc(::~ssor' Module
Table 4.0 Connector InforMation (Cont'd)
1 ~5220'-91 08'7/06
Rev JAN-()4'-B2
~===============================================================================
Connector Signal Signal
and pin No. I NaM€~ I Des;cr'iption
==============1================1==============================================
JS
**
DATA COMM
**
Pin
.... j. N/C
-.;~
+SV +SV
Pod P ow€~r
"'~3
+SV +SV
Pod
Power
.... 4
GN!)
P()w(~r
R(~tul'n
~~S
GNl>
P OWf-~r'
I~et urn
"~6
GND
P()w(~r
Return
.. ~'J
DeDi
Rat(:~
S~~lect
(23)
.. ··8
Nit
.. ~9
RD R (~c f:d. V (·~d
l)clti:\
(3)
.. ··10
Nit
· .. ·1 i
(,(:'
.,,,:>
Clf~dr'
To
Send
(5)
.... 12
DM Di:l ta
S(?t
Rei:ld y
(6)
"~13
N/C
· .. ·14
Nit
.... 1S
SG
Si~}na 1
Gr' 0 und
(7)
-··16
NIt
.... j. 'J
N/C
.... 18
OCR1
Rinq Ind:i.cator
(~~2 )
· .. ·j.9
+1;~V
+12V
Pod Power
.... ;? 0
--1;:!V '-1~~\)
Pod Power
--21
SD Tr';HlSMl. t t(~d
Data
(2)
.. - ;;!;,?
RS
r~eqllest To
Send
(4)
.... ;:?~~
TR Ready
(20)
"-;?4
Nit
"-25
N/C
.... 26
NIt
-~27
N/C
.. ··;,?8
N/C
.. -29
N/C
-~3 ()
Nit
"-31
N/C
"-3;.~
GND Return
.. ··33 SHIEL.l)
Shi(-.~ld
Ground
( 1 )
.... ~34
N/C
(n) denotes the RS-232 pin nUMber
================================================================================

1 ~3~!'~~0
Pl' ()c€-~~:;s()r' M()d u le
1:3220·-91. OB'7 10'7
Rev JAN···· 04'-(32
3.0 FUNCTIONAL DESCRIPTION
Refer t() bl()ck diagraM (fig. 1), scheMatic diagraMs (figs. 2,3),
tiMing diagraMs (figs. 4-8), COMponent location diagraM (fig. 9) and
parts list (fig. 10) located in the appendix. The following describes
the ()peration of the three Major sections of the Processor peA) control
and lID, MeMory, and video c()ntrol.
CONTROL. AND I/O SECTION
Clock
A 25.7715 MHz crystal is attached to the CRTC which oscillates at the
video d()t frequency. This is buffered by the CRTC and again by a
74LS244 (US11) to beCOMe DRCX, buffered dot rate clock. This clock is
then divided by seven by the 748163 (Ub11) to produce 3.6816 MHz, which
is shaped by Q4 and its associated circuitry to produce a SYMMetrical
clock for the ZaOA, which has a zero level < 0.4SV and a one level>
4.4V. This clock is also divided by two to produce a 1.8408 MHz clock
which the datacoMM chip (U613) uses to produce baud rates.
lOOA
The laOA Microprocessor perforMS the Major control and data Manipula-
tion functions of the processor peA. It provides addresses and control
signals to read and write data frOM and to both MeMory and I/O ports.
It also responds to two externally generated interrupts, NNMI and NINT,
which, when enabled, interrupt current execution and cause the ZaOA to
branch to its interrupt service routine. The ZBOA also responds to a
bus request signal, NBUSREQ, allowing the CRTC control of the systeM
b u ~:)es .
At power up (or reset) the ZaOA begins executing instructions frOM
prograM MeMory beginning at address OOOOH. A routine is executed which
initializes variables and devices according to inforMation contained in
non-volatile MeM()ry (CMOS) and perforMS a self test of ROM and RAM. If
an error is detected a series of beeps are issued to the keyboard which
indicate the failing ROM or RAM. After inintialization the prograM
enters a Major 10()P responding to inputs frOM the keyboard and datacoMM
por'ts.
Three 74LS244's (U4'7,U57,U511) buffer the address and control lines
frOM the Z80A. The 1 of a decoder, U76, is used to separate prograM
MeMory into six blocks, each BK bytes long. The addressed ROM is en-
abled during a MeMory read by the TNRD and TNMREQ signals ()r during an
instructi()n fetch by the NMl signal. Since the tiMe to read the data
in an instruction fetch is less than that for a MeM()ry read, the NM1
signal was used to provide an early enable of the ROM allowing it to
respond within the required tiMe. ROMs with access tiMes of 350 ns
frOM address or 300 ns frOM enable are required t() run the systeM at
full speed. [PROMs or ROMs with 450 ns access tiMes frOM address May
be used by installing JUMper WS and reMoving JUMper W6, which causes
the ZaOA to wait one cycle l()nger during instructi()n fetches. The quad
latch U610 and ass()ciated gating provides the required wait signal to
th~:~ ZBOA.,

13220
Processor Module
13220-91087/08
Rev JAN-04-82
3.1.3
I/O Ports
CMUS
The Z80A is capable of addressing 2S6 different input/output ports.
I/O addresses froM the ZaOA appear on address bits AO-A7 and the
accuMulator contents appear on bits A8-A1S. I/O addresses 0-7FH are
used to access locations in the nonvolatile CMOS RAM, U73, where
configuration data is stored. Since the CMOS RAM is not fast enough to
respond within the I/O cycle tiMe a wait state is generated (by U6l0)
each tiMe the CMOS RAM is accessed. Diodes CR6-CR8 ensure that around
S volts is always on t~e CMOS supply pin. EMMitter follower Circuit,
Q3, Makes sure that during a power off the CMOS is always disabled
before the l80A buses beCOMe undefined and reMains so until buses
beCOMe defined at power on. During power off the battery Maintains
CMOS contents. If power on configuration is to be fixed, the COMS RAM
May be replaced by an HM7611 PROM (however it Must be realized that the
standard read/COMpleMent/write test for the CMOS self test would show a
CMOS error since the prOM cannot be written).
DATACOMM
The SY6SS1 Asynchronous COMMunications Interface Adapter perforMS the
parallel to serial conversion, error detection and baud rate generation
functions required for serial data COMMunication. It appears to the
laOA as four read only and four write only ports with address bit TA2
selecting the read/write function. This is done to COMpensate for the
unique tiMing of the 6500 series devices. The SY6551 is selected by
the rising edge of SELDC which is inverted frOM U24, the 1 of 8
decoder. The addresses of the SY6SS1 (U613) are AO-A7H.
The status inputs of the SY6SSl produce undesirable results and
therefore are forced to their active low states while the necessary
status signals are routed through another port. RS-232 line driver,
USi4, and receiver, U614, are ~sed to convert frOM TTL levels to RS-232
levels (+-12V) and vice versa. TranSMitted signals are: send data
(SD), terMinal ready (TR), request to send (RS) and optional control
driver 1 (OCD1). Received signals are: receive d~ta (RD), data Mode
(DM), optional control receiver 1 (OCR1), and clea~ to send (eS).
The datacoMM subsysteM operates in an asynChronous, full-duplex, point-
to-point environMent. Characters May be tranSMitted and received
siMultaneously (full-duplex) with character flow occurring over randOM
tiMe intervals (asynchronous). To achieve hardware synchronization
each character is fraMed by a start bit and a stop bit (2 stop bits at
110 baud). The addition of the fraMing bits for tranSMitted characters
and the detection of fraMing bits for the received characters are done
by the SY65S1. The parity (for error detection) of the character is
selectable (in the datacoMM configuration Menu) and is also generated
and detected by the SY6SS1 which reports errors (parity, fraMing, and
overrun) to the ZaOA by Means of a status register in the SY6SS1 which
is read when a character is received. The data tranSMission and
reception rates are set by the ZaOA in an internal reqister within the
SY6SS1.

13220
Processor Module
13220-91087/09
Rev JAN-04-82
Rates are selectable (in the datacoMM configuration Menu) frOM 110 to
9600 baud.
The datacoMM status inputs and outputs provide the necessary control
lines to connect the terMinal to a host COMputer via a ModeM, or to
provide direct hardware handshaking between the terMinal and host. At
power-on the TR and RS lines are activated to indicate that the
terMinal is ready. Upon receipt of a ModeM disconnect escape sequence
(esc f) the TR line is brought inactive for .about two seconds to
disconnect the ModeM. The presence of a ModeM connection is detected
by DM which causes the indicator "LED" (an asterisk '*') to be
displayed on the bOttoM center of the display. The CS signal frOM the
host when active allows the terMinal to tranSMit data and goes inactive
to halt tranSMission (the terMinal May ignore CS depending on datacoMM
configuration). The state of OCDl is controlled by a configuration
strap with its default state being low (inactive). This line selects
the ModeM rate for dual speed ModeMS. OCRl is Monitored in datacoMM
self test to detect the presence of the loopback test hood. All ModeM
status lines are active high (+12V).
Upon receipt of a character frOM datacoMM the SY6SS1 generates an
interrupt signal (NINT) to the lBOA. This causes the ZaOA to branch to
the datacoMM interrupt service routine which reads the SY6S51 status,
clearing the interrupt, and if no errors are present, inputs th~
character and places it into the datacoMM buffer in RAM. Characters
for which errors (parity, fraMing or overrun) are present cause a
delete character to be placed in the buffer.
Teus PORTS
The reMaining I/O ports are buffered to the ZaOA data bus by the
biderectional bus driver, U37. This was done because of data bus
loading. The signal TNRD selects the direction of the driver which is
enabled for all I/O accesses except CMOS RAM and datacOMM.
U25
forMS the keystatus port located at address 80H. The keystatus
port returns the status of 8 keys at a tiMe, which keys are deterMined
by th~ keyboard/display port (U26). Four bits of the key address
(colUMn address) are supplied by U26 (located at address B8H) and three
More frOM the eRTC scan line outputs (row address). As the row address
(scan line count) frOM the CRTC change, keystates are clocked into the
keystatus shift register (a high bit indicating key active) frOM which
they are later read. The colUMn address is increMented (during an NMI)
for each of the first sixteen display rows thereby scanning the entire
range of keyboard addresses.

j.~3;~~?O
P l' () C ~~ s ~:; () f' r1 0 cI u1e
L3220-91 OB'7 /10
Rev JAN-'O 4···82
The keyboard/display port also enables a counter (U114) which counts
horizontal sync pulses down to a bell frequency. The bell signal is
the n ~:; hap (~d bY (~4 an cI i t~:; a ,;) soc i ate d c: i l' cui t . T I'\(~ reMa i ni ng bit S 0 f
the I«~~ y boa l' d/ d i ~; P :I. e) y POl" t d E-~ t (;H' Min E~ whe t h £o~ r £om han c £o~ Men t <.!; will be
enabled and latches the signal which deterMines the blinkrate of
blinking characters.
The NNMI (non-Maskable interrupt) signal to the ZaOA is Masked
externally by a D flip-flop (half of U612). Port addresses B8H to 8FH
select the NENNMI signal of the port decoder, clocking the latch while
address bit TAO is the data input. This Means that a write to port 88H
clears the latch, disabling NMI, while a write to port 89H sets the
latch f.·H\i:\bling NMI.
The systeM status port, U36, located at address 90H allows the ZaOA to
l' (.:~ ad t h E~ V (~H' tic alb 1 elf) k s i 9na1 ( VB l. AN K) f 0 f' S Yn c: h l' 0 ni zi ng the s of twa l' e
with the hardware. It also provides the inputs f~r the datacoMM status
signals discussed above and also Monitors the integral printer s~atus.
The integral printer port at address 98H buffers data continuously to
the printer bus, the data being latched in the printer when the
NPRINTER signal is active. The processor writes data and COMMands to
the printer via U16 and half of U1S. Printer control is specified by
perforMing a write operation to the printer with address lines TAO and
TA1 and data lines TDO-TD7 selecting the particular function. Printer
status is read back frOM the printer on the upper half of U1S which is
enabled for read operations frOM the printer port. The presence of the
printer is detected by reading status frOM the printer and checking
data bit TU1. TU1 will be low if the printer is not connected due to
the pullup resistor R1. When the printer is connected to the processor
Ji pin 11 is pulled low by the printer therby indicating connection.
Each character in the printer is forMed by 30 bytes of dot data, each
pair of bytes being Made up of the dot data needed to forM the
character if the character cell is scanned horizontally. The first
byte in the pair indicates the state of every other dot while seven
bits of the following byte indicate the state of the interstitial dots
for the saMe horizontal scan. Thus fifteen pairs of.bytes correspond
to fifteen horizontal scans of the character. In this way any
character font in a 1S by 1S cell May be created. The printer buffers
the data and translates the horizontal dot inforMation into vertical
dots for printing. Each 30 bytes of dot data are followed by a print
COMMand to print the character. The printer is also able to print in
expanded and cOMpressed Modes.
The reMaining TBUS port located at ASH latches SOMe signals to the
video section and one for the datacoMM section. The NMODEM signal is
inverted to provide the clock for the latch (U3S).

13;:~~~ 0
Pr'ocf.~~:;~:;or Module
13~?20·M·91 OB7 /1.1
R (~v J AN .. - () 4·-S;:!.
3.2 MEMORY SECTION
~3. 2.1
The Z80A is capable of addressing 65536 (64K) bytes of MeMory data.
The MeMory Map for this processor is'shown in the table below.
OOOOH
2000H
4000H
TABLE S.O TerMinal MeMory Map
NMI Service Routine
S~~lf t€~st code
Function keys code
l)at .. :lCOMM code
Configuration code
Video intrinsics
U63 HK
16K
U6S ~~41<
6000H I Internal printer code
I
I U66 ~5:r:.!\(
I ................ _. - ..................... M ..................... _ ..................... _ .............. M' ........ M ...... _ ..................... _. _. M ... M ......... _. _ ... M.
BOOOH I Not u~:;ed
I (CRTC Map)
I U67 I 40K
I ......................................... - ............................ "" ............................ _ .............. - ................................. _ .. M. .... .... .... .... ........ I
AOOOH I Not us(~d I
I (CRTC Map) I
I U68 I 4BK
I ........................................ _. 'M' 'M'"'' ........ -' - ......................... - .................... _ .............................................................. _ .. I
CO () OH I DynaMic I~AM I
I -
buffers I
I -
display MeMory I
I -
stack I
I -
systeM variables I
I I
I ZDO : ZDt : ZD2 : ZD3 : ZD4 : IDS : ID6 : ID7 I
I U41 : U42 : U43 : U44 : US1 : US2 : US3 : US4 I 64K
R€~a d· .. ·on 1y ·· .. M(-:~Mor y
As can be seen frOM the MeMory Map 4B K of address space has been
allocated for read-onlY-MeMory (ROM). This MeMory contains the ZaOA
prograMS which controls the terMinal operation. The ROM space is
decoded into six 81< byte blocks by the 74LS138 decoder U76. A JUMper
on address bit TA12 for each ROM allows the use of either BI< byte or 41<
byte ROMs (or EPROMs). Note that BK bytes of address space is
allocated for each ROM device even if it is only a 4K byte ROM (the
upper 41< of that block is unusable).

l :·~;.:?;:!.o
P l' 0 C E~ S \;) 0 l' Mod u1e i
:~220-9i OB'1 Ii,!
R ~~ v J AN·M. 04···82
During an instruction (opcode) fetch the Z80A activates the NM1 signal
to indicate that an instruction fetch cycle is in process. This signal
is used to provide an early enable of the ROM being addressed during an
opcode fetch therby allowing the use of ROMs with an access tiMe on 350
ns froM address or 300 ns froM enable (note that an opcode fetch is o~e
clock cycle shorter than a MeMory read operation) without wait states.
During a MeMory read frOM ROM the TNMREQ and TNRD signals go active
G~nabling th(~ addl'f.~Ssf:~d ROM. Data is r'f.~quired valid app('OXiMatf.~ly 470
n ~:) fro M i:l dd l' (0 S s) the r e of 0 r' e n () wa its t ,1 t es ar (-? r (~q u ire d for M (-? til 0 r y rea ds
even when using 450 ns EPRUMs. Note that data is placed directly on
thE' Z80t-1 dati-'l but:; without buP·fering.
RandoM-acceSS-MeMory
The RAM subsysteM has been designed around the MK4ll6-2 (or equivalent)
16K x 1 bit dynaMic RAMs. The MK4116-2 has a MiniMUM access tiMe of
150 ns and MiniMUM cycle tiMe of 320 ns. U41-44 and US1-S4 supply data
bits TDO-TD7 respectively to provide the 16K bytes of RAM data storage.
Th(~ I~AM~;; ar'e acce~)~;(~d in thl'(;:O(-? ways: by the ZaOA for M~?MOr'y read or
Wf':i. te clC:ce5se~) by the lBOA d U1' ing a l'efl'€-~sh c yc Ie and by the CI~TC
during a DMA (direct-MeMory-access) cycle. Each of the three is
discussed below. Refer to figure 6.0 for RAM tiMing.
ZUOA I~EAD/WI~ ITE
A Z80A access to RAM is initiated by lowering the TNMREQ signal at an
address location between COOOH and FFFFH (RAM address range). Prior to
TNMREQ going low the output of U77 would be high causing l's to be
shifted through the shift register) U510, by DRCX. As TNMREQ goes low
(TNRFSH is high) the output of U77 goes low also. As the clock occurs,
O's are shifted through the shift register causing outputs QA-QD to go
low in turn. This produces the RAM tiMing sequence as follows: NRAS-
strobes in row address) MUX-changes RAM address inputs to colUMn
address) NCAS-strobes in colUMn address and activates internal RAM
circuitry to access the addressed cell. Data ouput on MDO-MD7 is vaild
100 ns frOM NCAS. When the Z80A is finish~d accessing the RAM the
TNMREQ signal goes high and 1'5 are shifted through the shift register
COMpleting the RAM cycle.
If the Z80A is perforMing d read operation the TNRD line is lowered
along with TNMREQ (TNWR reMains high). The TNRD signal is gated with
the output of U77 to enable the transparent latch, U62) during the read
operation. When the NMUX signal goes high (as MUX goes low) the
transparent latch beCOMes transparent) that is, the outputs follow the
inputs) placing the RAM outputs on the ZBOA data bus. The latch
outputs are enabled until TNRD and TNMREQ go high again.
For a write operation, the ZaOA lowers TNMREQ and places the output
data on the data bus. ApproxiMately one Z80A clock later the TNWR line
goes low strobing the data into the internal data latch in the RAM.
The TNRD signal will be high disabling the transparent latch so RAM

13220
Processor Module
13220-91087/13
Rev JAN-04-82
outputs will never be on the l80A data bus. The cycle proceeds as for
a read operation with TNMREQ going high, shifting 1'5 through the shift
register to cOMplete the cycle.
zaOA REFRESH
The nature of dynaMic RAMs requires that each row Must be accessed
every two Milliseconds to guarantee the contents of that row are held.
The l8UA has a built-in refresh function to provide signals which
perforM dynaMic RAM refresh without requiring extra processor overhead.
The ZaOA Maintains a 7 bit MeMory refresh counter which is increMented
following each instruction fetch. While the instruction is being
decoded and executed the refresh counter is output on address bits TAU-
TA7 while the TNRFSH and INMREQ signals are brought low, initiating the
RAS-MUX-CAS sequence, refreshing that row. Since the TNRD and TNWR
signals reMain high during the refresh cycle, the MeMory contents are
unaltered and the transparent latch is not enabled so that the accessed
byte does not appear on the bus.
eRTC DMA
Twice per video row, on scan lines 6 and 14 (if starting to count froM
0), the NBUSREQ signal to the ZaOA is activated to allow the eRTC to
perforM DMA of enhanceMent and character data (see section 3.3 for More
inforMation on the eRTC). The ZaOA responds to NBUSREQ at the end of
the current Machine cycle by tristating its address and control lines
and activating the NBUSAK line signalling that the bus is available and
will reMain so until NBUSREQ is raised. The NBUSAK signal is inverted
and buffered by U79 to provide both IBUSAK (active high) and TNBUSAK
(active low, buffered). These signals are used to tristate the address
and control buffers U47, US? and US11 and enable the video subsysteM
for DMA action. TBUSAK enables the CRTC to place the lower 12 bits of
the DMA address on the bus and enables the output of the transparent
latch, U62, as well as enable the load signal to the shift register,
USiO. TNBUSAK enables the upper four bits of the DMA address frOM U74
onto the bus and takes the recirculating line buffer, U38, out of the
recirculate Mode (see section 3.3 for More inforMation on DMA
addressing).
ApproxiMately four character tiMes before the start of the video row
the line rate clock (LRC) output of the CRTC goes high enabling the
load Signal to the shift register through the AND gate U71U. The load
signal is derived frOM the character rate clock, LCGAX, which is
delayed three dot tiMes through U410 in order to synchronize the RAM
access to the video tiMing and guarantee sufficient address set up tiMe
to the RAMs. 1he load signal causes RAS-CAS shift register, U510, to
be parallel loaded on the next riSing edge of DRCX (dot rate clock).
Upon loading, the shift register output QD is high and QA is low. THis
condition forces the output of U77 to go low, causing a's to be shifted
through the shift register. The next three occurances of DRCX produce

13220
Processor Module
13220-91087/14
Rev JAN-04-82
the NRAS-MUX-NCAS sequence, accessing the addressed byte. Data is
available 100 ns froM NCAS, and, since NMUX is high, is placed directly
on the Z80A data bus (U&2 is in transparent Mode), and therefore on the
line buffer inputs. As the shift register output QD goes low the
output of U77 is forced high and 1'5 are shifted through the shift
register cOMpleting the RAM cycle. As MUX goes high again, NMUX goes
low causing the data out frOM the RAM to be latched in the transparent
latch, U62, where it is held until the next MeMory access. As LBCDEL
(delayed line buffer clock) goes low the data is clocked into the line
buffer U38. The CRTC increMents the address and the next load signal
occurs 9 dot tiMes frOM the first, repeating the DMA cycle. In this
way 80 sequential bytes of data are fetched frOM the RAM and loaded
into the line buffer during the 80 active video character tiMes of the
display.
Note: Although the shift register load signal is enabled four
character tiMes before active video, the CRTC holds the starting
address until active video and then increMents it during active
video. In addition, the data is not clocked into the line buffer
until the line buffer clock transitions low during active video.
On the last scan line of a character row, scan line 14, the CRTC lowers
the LBRE (line buffer recirculate enable) output, taking line buffers
U28 and U39 out of the recirculate Mode (where the output is shifted
back into the input) thereby allowing data to be clocked into the
inputs. During the DMA cycle of scan line 14, as characters are being
output frOM line buffer U39 to the display, characters for the next row
are fetched frOM MeMory and loaded into line buffer U39. At the saMe
tiMe, as enhanceMent data is shifted out frOM U28, the data which was
previously stored in the teMporary line buffer U38 (during the DMA
cycle of scan line 6) is shifted into U28. In this way the display
data for the next row of characters is loaded into the line buffers
during the last scan line of the previous row as it is being displayed
on the screen.

13;'?';~O
Pr'oce~;~:;o~' Module
1 :5220-91 OB'l /1 S
Re v J" AN-· 0 4·_·B2
VIDEO CONTROL SECTION
Ov~~rvi€o~w
The video control section generates the tiMing signals required to
fetch character and enhanceMent data frOM MeMory and drive the analog
sweep circuitry to display that inforMation on the CRT.
The display is divided into 26 rows of SO character cells each. Each
character cell is a rectangle, 15 dots vertical by nine dots
horizontal. Any character to be displayed is produced by selectively
lighting the dots of the character cell which shape that character,
leaving the others blank. Dots are left blank on either side and on
the top and bottOM of the character cell to provide horizontal and
vertical seperation between norMal characters. This is not true of
characters which are continuous across the character boundary, such as
line drawing characters (used to display forMS).
The analog sweep circuitry sweeps the electron beaM frOM left to right
and frOM top to bOttOM across the display. As the beaM is swept
horizontally it is turned on to produce a lighted dot and off to blank
a dot position. As the beaM reaches the end of its scan a horizontal
~:;ync: ~:;i(lnal :i.s ~:;ent to the sweep c(~using the beaM to retf'aC(~
horizontally and begin sweeping again. During this tiMe the beaM is
also being swept vertically. The COMbination of these two produces the
display raster. As the beaM reaches the bottOM of the display a
vertical sync signal is sent to the sweep causing the beaM to retrace
frOM the bOttOM right to the top left corner. In this Manner the CRT
display is written 60 tiMes per second (when configured at 60 Hz) or
optionally SO tiMes per second (configured at SO Hz).
HOI~IZONTAL TIMING
After the 80th character position of a scan line the beaM is turned off
(blanked) and reMains so as the horizontal retrace takes place. The
beaM is enabled again as it reaches the position for the first
character of the next scan. This blanking interval is called
"horizonti:tl blanl<ing". This blanking (~llows tiM~? for th(o? t.)(~i~M to
retracB
1
settle at the left side and begin tracing again. The portion
oft h f~ ~~ can whe f' (o? the be (;\ M i~::, £~ n <":t b led i ~.) know nat:; .. act :l v G~ v:l d eo" . Th ~?
horizontal scan tiMe consists of the 80 character tiMes of active video
plus 3S character tiMes of horizontal bl<":tnking for a total of 115
character tiMes per scan (1 character tiMe ~ 349 ns). This produces (;\
horizontal scan frequency of 24.9 KHz.
The horizontal sync signal is activated 16 character tiMes before the
last video character of the scan and is active for 7 character tiMes.
It is produced in advance of the last character to COMpensate for the
d f.~:I. ay il"l t h (o? ~:)W(o?(~P h0 r i z 0 n tal c en t fn' in (1 c:ir cui t .

1.3~?';;'~0
Pr' 0 c: f.~ ~:i ~) 0 f' Mod uI (~~
13220--9108'7/16
R (~ v JAN·- 0 4,-, 8 ~:.!
3.3.2
VERTICAL. TIMING
The 26 active video rows of the display each require 1S horizontal
scans for a total of 390 active video scans. After the last scan line
of the last row is displayed, a vertical blank signal is activated
which disables the electron beaM during the vertical retrace tiMBo The
beaM is enabled again on the first scan line of the first row. The
duration of the vertical blank interval depends upon the occurance of
the vertical sync signal which triggers the vertical retrace. This
vertical sync tiMing depends in turn on the frequency with which the
fraMe (one entire display) is refreshed. This fraMe rate May be
configured to either SO or 60 Hz corresponding to the AC line
frequencies in foreign countries or the U.S. to eliMinate display
interference between the power supply and CRT. The following table
describes the tiMing relationships between the vertical blank and
vertical sync signals and the fraMe rate.
TABLE b.O FraMe TiMing
FraM(~ Rat(~
60 Hz I SO Hz
Delay after v. blank to
v. sync (=1= scan lines) 0
v. sync width (I scan lines) 19
64
v. blank duration (I scan lines) 25 1.08
Total i scan lines per fraMe 415
Display MeMory addressing
Section 3.2.2 describes how the eRTC perforMS DMA to load the line
buffers with character and enhanceMent data for display. Before it
perforMS DMA, the CRTC Must be loaded with a starting address (called
the row-start address). Each tiMe the CRTC is enabled it fetches 80
consecutive bytes of data starting frOM the row start address and
places it into one of the recirculating line buffers.
The Z80A Maintains a table of 24 row start addresses in MeMory
indicating the addresses of the first byte of character data for each
of the character rows being displayed. Rows 2S and 26 contain the soft
key labels and are always accessed frOM fixed locations. This table is
actually a subset ~f a larger table which contains row-start addresses
for all 48 display rows. The address of the first enhanceMent byte of
a row is the first character byte address offset by 80.

13220
Processor Module
13220-91087/17
Rev JAN-04-82
3.3.3
Two scan lines prior to the NBUSREQ signal being activated a non-
Maskable interrupt (NMI) is generated which causes the Z80A to branch
to the NMI service routine after COMpleting the current instruction.
Part of this service routine writes the row-start address for the next
DMA into the rowstart register of the CRTC. The row-start address is
written into the CRTC via the address bus itself. At the saMe tiMe,
bits TA13 and TA12 are written into the 74LS17S U7S, which provides the
upper bits of the RAM address for DMA. The ZaOA reads the row start
address froM the table, adds the 80 byte offset for enhanceMent data
DMA, Masks bits TA1S and TA14 to a 1 and 0 respectively and then writes
a 02H to this address. By Masking bits TA1S and TA14 the address
corresponds to a ROM location, which of course can't be written. These
bits are decoded by part of U27 and U32, along with TNMREQ and TNWR to
generate the register load signal (U412 pin 38) which latches the
address into the eRTC and U7S for use during the next DMA cycle. The
data bits ZDO and ZD1 select the register to be written to, in this
case, the row-start register. The NMI service routine keeps count of
the next row to be displayed in order to deterMine which row start
address to send to the CRTC next. Since NMI can be disabled for an
indefinate period (for exaMple during a RAM test) it is resynchronized
every fraMe by reading the VBLANK signal through the systeM status
port.
Character display
At any given tiMe the characters for the current row being displayed
are held in the recirculating line buffer U39. The character codes
output frOM this line buffer are resynchronized to the character clock
through the octal latch, U310, frOM which they are sent to the
character ROM, U311. This ROM contains the dot pattern for each scan
line of each each possible character code. The standard character set
uses the ASCII character code to represent the 128 possible characters
in the set. The first 32 characters of the set are the control
characters (escape, line feed, carriage return, etc.) while those
reMaining are the alphanUMeric and punctuation characters. These 128
characters are represented in bits XO-X& with X7 being a O. These bits
along with the scan line count beCOMe addresses for the dot data frOM
the character ROM. Therefore, 11 address bits are required, Meaning
that a 2K byte ROM May be used to contain the dot data for the standard
character set. Bit X7 will then serve as an active low chip select.
By usinq a 4K byte character ROM, two COMplete character sets May be
displayed. In this case bit X7 selects between the two character sets.
Likewise an BK byte ROM can store four COMplete, 128 character,
character sets. The scheMatic shows a signal frOM the enhanceMent data
latch, U29 pin lS, which is inverted by U212, and sent to U311 pin 21.
This signal is used to address the 8K byte character ROM on 4K
boundaries. This COMbined with bit X7 frOM the character data latch
allows selection of any of the four character sets. This upperMost
address bit beCOMes a chip select for 2K or 4K character ROMs.

13220
Processor Module
13220-91087/18
Rev JAN-04-B2
As the character code and scan line count is issued to the character
ROM an access tiMe delay is encountered before the dot data is
available at the outputs. "he character ROM has an access tiMe of 300
ns, therefore one full character tiMe (349 ns) delay is introduced.
As the dot data beCOMes available out of the character ROM the lVSRX
(load video shift register, buffered) signal is brought low which, on
the rising edge of DRCX, parallel loads the data frOM the character ROM
into the character shift registers U312 and U313 (and U314 as explained
later). Since only seven dots per scan line are required for standard
characters, seven dots are loaded frOM the character ROM (low output
Means dot is lit) into the shift registers. The MSB (Most significant
bit) output frOM the character ROM is latched by U1a (on LCGAX clock)
and is used to enable the half-shift function (described below). The
MSB output of U312 is connected to the serial input of U313 essentially
forMing an 8 bit shift register. At the saMe tiMe that the seven dots
are loaded into the shift register a 1 is loaded into the MSB.
The QD output of U313 goes to the character Multiplexor, U213. This
Multiplexor selects one of several inputs to gate to the dot streaM.
For a norMal scan (not half-shift) the Multiplexor select inputs will
be 101 (C input is Most significant) selecting the DS input. As the
dots are loaded into the shift register the first dot (which is high)
appears on the DS input of the Multiplexor and is gated to the dot
streaM. On each of the next 8 dot rate clocks (DRCX) dot data is
shifted one bit position in the shift register and therefore to the DS
Multiplexor input and to the dot streaM. Since the serial input of
U312 is tied ~igh, a 1 (blank dot) is shifted into the shift register
as the dot data is shifted out. Therefore at the end of the 9 dot
clocks COMprising the horizontal scan for a standard character, the
first and last dots are blanked (l's) with the 7 dots frOM the
character ROM in between.
HALF-SHIFf
To avoid the "stairstep" appearance of characters with long diagonals,
a feature known as "half-shift" is iMpleMented which allows and scan
line of a character to be delayed by half a dot tiMe. This half-
shifted scan line, placed between two norMal scan lines, fills in the
diagonal as shown below.
X
X x
X x
X
(no half-shift>
norMal
half-shifted
norMal
half-shifted
norMal
half-shifted
x
X
X
XX
X
(with half-shift>

j.3;;!.;;!.()
Pl' OCE-~S~:j.O(' ModulE'
1:5~!20-91 OB'7 119
Rev JAN .. -04 .... B2
In the ~:;tandard charact(~r set the MSH output of the char'actr~r ROM
indicates that a scan line is to be halfshifted. This output is
1 C1 t ch ed (b y L.CGAX) in t 0 lJ 18 wh (~r' e it ish e Id f' 0 r the (7 dot~;) 0 f the
character tiMe. The output of Uta is fed to the character Multiplexor
select input A which, for half-shifted scan lines, selects the D4 input
(U213 pin 1S). The QD output of the dot shift register, U313, is sent
to the JK flip-flop, U413, clocked on the falling edge of DRCX, which
perforMS the half-shift of the dot data. The output of this flip-flop
goes to the D4 input of the character Multiplexor. The half-shift
flip···flop i~:; pl'eSE-~t by l..VSRX at tl'H~ tit'te n~~w dots ar'e loaded :i.nto the
~:;hift r'(-?~J:i~;;t(~7'~:;.
CDPY BIT
SOMe alternate character sets such as line drawing set or large
character set require all nine dots an a scan line to be active. This
allows for continuous dots across a character boundary as required for
drawing forMS, etc. on the display. In order to get nine dots out of
eight outputs frOM the character ROM, a copy bit circuit is activated
which copies the M5B output into the first two dots while the reMaining
seven ROM outputs forM the reMaining seven dots.
The seven least significant ouputs frOM the character ROM are loaded
into shift registers U312 and U313 as for standard characters. The
MOst significant output is loaded into both the A and B inputs of shift
register U314 at the saMe tiMe as the least significant seven bits.
Thu"::;,. th€-~ MSB i<.:; "cop:i.E-~d" :i.n <':;hift reg:i.<.:;ter U3t4. The l'eMaining dots
are brought frOM the QC output of U313 into the serial inputs of U314
thereby forMing a nine bit shift register with U312, U313, and U314.
The QB output frOM U314 is then fed to the D7 and D6 inputs of the
ch'::H'act0~l' Mult:i.plf.·~xo7' wh:i.c:h (-11'€'~ s(~lE-~ctf.~d whe-m thE-~ selfo:'ct inputs ar'e
11X. Note that the select A input is a don't care since half-shift
cannot be used in these character sets.
The copy bit circuit 15 activated whenever the X'7 output of of the
character latch U310 is active. ReMeMber that this bit is activated to
select the second character set in a 4K character ROM or the second and
f 0 lH' t h ~:; €-~ t ~.; ina n 0K c: h cH' act EH' R(JM. The f i l' S t ~~ ;:.~ c: hal' act E-H' 0 fan y 0 f
the four posible character sets are reserved for control characters and
therefore copy bit is deactivated when these positions are accessed.
'"his condition is decoded by bits XS or X6 being gated with X'7 (U34 and
U1.12) to €,mablf.~ copy b:i.t only for the UppE-H' 96 chcH'actel'~:; of th(~ Sf.~t.
The result of this decoding is latched in the JK flip-flop, U413, which
allows for the access tiMe of the character ROM. The flip-flop is
clocked by the COMbination of LVSRX and DRCX which are gated together
by U411. The output of the copy bit enable latch is then used to
select the copy bit shift register output and gate it to the dot
s t l' 0~a M.