HP 13220 Manual

P f' () c: ~?~:;~:; () T' Mod u1e
Manual Part No. 13220-91087
REVISED
JAN··· () 4····B2
DATA TERMINAL
TECHNICAL INFORMATION
HEWLETT~PACKARD
Printed in U.S.A.

P f' 0 c (~~:; ~:; 0 7' M () d u1e
Manual Part No. 13220-91087
I~EVISED
JAN··· () 4····0t?
NOTICE
The inforMation contained in this dOCUMent is subject to change
w:i.ti"lou"t notic€~.
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shall not be liable for errors contained herein or for incidental or
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i.O IN"l"RODUCTION
The 02620-60087 Processor PCA perforMs the terMinal logic functions for
the 2622A terMinal. Its operation is based on the Z80A Microprocessor
and the National SeMiconductor 8367 CRT Controller (CRTC).
The control and I/O section of the Processor PCA provides control
~;> i qna1 ~:> , :i. n put / 0 ut put and d i~ tap roc (~s~:;:i. n(J fun c t j. 0 n~:; . The MeM 0 r' y
section provides 16K bytes of dynaMic RAM for display MeMory, scratch
pad MeMory and data buffers, and space for up to six 4K or 8K byte RUMs
of which 32K are used for COMplete terMinal operation (8K of ROM
optional with integral printer). The video control section provides
all tiMing signals for driving the sweep circuitry and video logic as
well as perforMing direct MeMory access CDMA) of display data. A
detailed description of the operation of each of these sections follows
:i. n ~:;ec t ion 3. 0 .
2.0 OPERATING PARAMETERS.
A SUMMary of operating paraMeters for the Processor Module is contained
in tables 1.0 through 4.0
Table 1.0 Physical ParaMeters
===============================================================================
Par' t Si ze (I... x W x D) 1 W(~ i qh t 1
1 NUI"',IHH' 1 NOMf:·~nclatul'~~ 1 +/ .... 0.1 Inche~; 1 (Pounds> 1
1=============1==============================1=======================1========1
1 I 1 1 1
1 1 1 1 1
1 02620-60087 1 Processor PCA 1 12.3 x 10.9 x O.S 1 1.4 1
1 1 1 1
I 1 1 1
1 1 1 1
===============================================================================

1 :'5;:~:~O
Pl' ()Cf.~<':;~;()l' Mod uIe'
Table 2.0 Reliability and EnvironMental InforMation
1 ~5220 .... f/1 0 H'7 / () ~5
Rev JAN-()4····f32
================:========~======================================================
I
I
I EnvironMental: HP Class B
I
I
I Restrictions: Type tested at product level
I
I
I
I==~===========~==============================================================
I
I Failure Rate: 3.71 (percent per 1000 hours)
I
===================~======~====================================================
Table 3.0 Power Supply RequireMents - Measured
(At +/-5% Unless Otherwise Specified)
===~=============================~=============================================
I
+16 Volt Supply +12 Volt Supply +5 Volt Supply I -12 Volt Supply
I
ill 0 MA @ 200 MA @ 2.0 A I @ SO MA
I
I NOT APPLICABLE I I I I
I ::: ::;: :~: :::: :::::::: :::: :::::::::::: :::::::: :::: :::: :;:: :::: :::::::: :'~::::: :::: :::: :::: :::: :.:::::: :::: :::: :::: :::: :::: :::::-.:::::: :::: :::::::: :::: ::: I =:::::::::::: :::: :::: :::::::: :::: :::::::: :.~::::: :::::::::::: :::: :::: :::::::::::: :::::::::".:: ::::::::::: :::: :::: = :::: = :::: :::: :::::::: =I
I I I
I 115 volts ac I 220 volts ae I
I I I
I ~ A I @. A I
I I I
I NOT APPL.ICABL.E I NOT APPLICABLE I
===============================================================================

13~~2 ()
P f' 0 C £~ ~:; ~:) () f' M () du1e
Table 4.0 Connector InforMation
:1. 3~~~:~ 0···9108'7/04
R (::~ v JAN··· () 4···B;?
===~==========~===~========~===================================================
Connector Signal
1 and P in No. 1 NaM(~
1==============1================
J1 1
Pin ···1
.... 2
.... ~5
.... 4
· .. ··7
.... 8
·-9
1
I
I
1
I
1
1
1
1
\
1
\
\
I
t
1
I
.... :1. 0 I
I
.... :1.1 I
I
.... :1. ;,? t
I
"-L3 t
-14
· .. ·16
.... 1·7
-1t3
-·19
"-20
.... 21
·-22
.. -;~3
-24
"-25
-26
PRINTER
PWI~ ON/FAIL
WRITE
Ai
DATA ()
DATA 1
DATA 2
DATA :5
DATA 4
DATA S
DATA 6
DATA 7
GND
PINT
AO
+SV
+SV
+SV
+SV
GND
GND
GND
GNU
GND
Signal I
Description I
=============================================\
** PRINTER **
Negative True, Printer Strobe
Negative True,Power On/Failing
Negative True, Write signal
Negative True, Fun~tion select bit 1
LSB - Negative True, Data
MSB - Negative True, Data
Set printer contrast
Negative True, Printer Interrupt
Negative True, Function select bit 0
Vcc Power
Power Retul'n

1. ~5~~2()
Pl'OC(~SS)Ol' Module
13220-91.08'7/0S
Rev JAN-()4-B2
Table 4.0 Connector InforMation (Cont'd)
===============================================================================~
I Connector Signal
I and Pin No. I NaMe
Signal
Description
\==============1================ ==============================================
I J;:.~ I
I 1
I Pin -·1
+5V
\ -.~:~
\ -3 +SV
\ -4 +12V
I -S GND
I -6 GND
I .. _ ... _. __ ._ ... _ .. __ .......... _ ...... _.
** POWER SUPPL.Y **
+SV Power
N/C
+5V Power
+1;':'~V Power
R€~t ur'n f 01' Power
Ret urn for' P ow(~r
I -'7 PWR ON/FAIL Negative True, Power On/Failing
\ -8 -1.2V -12V Power
I -9 BATTERY Positive Battery TerMinal
I -10 1 BATRET I Negative Battery TerMinal
I ........................................ - ............ 'I ._.- .... '''' .- ..... - ..................... - •• - .-.- I .. -.-- .- ...... - .- ....... - ............. _.-.- ........... , ..... - .......... -.-.- .. - .... '''' .- ... _.- .... _ .... - ..... - ..... _._.- --'- .. _.- I
I J~3 1 I
I ..... __ .. _. __ .... __ . I
I Pin -1 HLFBRT I
I -2 I
\ -3 RETURN I
\ ........ _ ........... _._._. I
I --4 FUL.L.BI~ T \
\ -5 RETURN I
\ -6 RETURN \
I I
I .... 'J iJ'f~:'ifi)rf I
\ -8 I HORDR I
I ..... - ........ , _ .......... - ........ - ........... -. :1 .......... - ............ - ............... - ............. - •. -
\ J4
\
I
I
I
I
\
I
I
)
Pin .... 1
.... 2
· .. ·3
... -4
· .. ·s
· .. ·6
.... ·7
-·B
· .. ·9
.... 1 ()
····1.1
.... 12
\(EYO
KEYj .
KEY2
KEY:~
I<EY4
KEYS
KEY6
KEYACT
GNI>
BELL..
+Sv
** SWEEP **
Negative true, Half Bright Video
N/C
Return for half bright twisted pair
Negative true, Full Bright Video
Return for Video twisted pair
Return for Drive signals
Negative True, Vertical Drive
Horizontal Drive
** KEYBOARD **
Key
Data
(LSB)
KE~y Data
Key Data
Key Data
Key
Data
N/C
K(~~y
Dc:l ta
)(ey
Data
(MSS)
Key Active (Status of key selected)
Pow(~r Return
Bell Line
+5v Power
================================~===============================================

j. ~5;.:!.2 0
Pr'oc(::~ssor' Module
Table 4.0 Connector InforMation (Cont'd)
1 ~5220'-91 08'7/06
Rev JAN-()4'-B2
~===============================================================================
Connector Signal Signal
and pin No. I NaM€~ I Des;cr'iption
==============1================1==============================================
JS
**
DATA COMM
**
Pin
.... j. N/C
-.;~
+SV +SV
Pod P ow€~r
"'~3
+SV +SV
Pod
Power
.... 4
GN!)
P()w(~r
R(~tul'n
~~S
GNl>
P OWf-~r'
I~et urn
"~6
GND
P()w(~r
Return
.. ~'J
DeDi
Rat(:~
S~~lect
(23)
.. ··8
Nit
.. ~9
RD R (~c f:d. V (·~d
l)clti:\
(3)
.. ··10
Nit
· .. ·1 i
(,(:'
.,,,:>
Clf~dr'
To
Send
(5)
.... 12
DM Di:l ta
S(?t
Rei:ld y
(6)
"~13
N/C
· .. ·14
Nit
.... 1S
SG
Si~}na 1
Gr' 0 und
(7)
-··16
NIt
.... j. 'J
N/C
.... 18
OCR1
Rinq Ind:i.cator
(~~2 )
· .. ·j.9
+1;~V
+12V
Pod Power
.... ;? 0
--1;:!V '-1~~\)
Pod Power
--21
SD Tr';HlSMl. t t(~d
Data
(2)
.. - ;;!;,?
RS
r~eqllest To
Send
(4)
.... ;:?~~
TR Ready
(20)
"-;?4
Nit
"-25
N/C
.... 26
NIt
-~27
N/C
.. ··;,?8
N/C
.. -29
N/C
-~3 ()
Nit
"-31
N/C
"-3;.~
GND Return
.. ··33 SHIEL.l)
Shi(-.~ld
Ground
( 1 )
.... ~34
N/C
(n) denotes the RS-232 pin nUMber
================================================================================

1 ~3~!'~~0
Pl' ()c€-~~:;s()r' M()d u le
1:3220·-91. OB'7 10'7
Rev JAN···· 04'-(32
3.0 FUNCTIONAL DESCRIPTION
Refer t() bl()ck diagraM (fig. 1), scheMatic diagraMs (figs. 2,3),
tiMing diagraMs (figs. 4-8), COMponent location diagraM (fig. 9) and
parts list (fig. 10) located in the appendix. The following describes
the ()peration of the three Major sections of the Processor peA) control
and lID, MeMory, and video c()ntrol.
CONTROL. AND I/O SECTION
Clock
A 25.7715 MHz crystal is attached to the CRTC which oscillates at the
video d()t frequency. This is buffered by the CRTC and again by a
74LS244 (US11) to beCOMe DRCX, buffered dot rate clock. This clock is
then divided by seven by the 748163 (Ub11) to produce 3.6816 MHz, which
is shaped by Q4 and its associated circuitry to produce a SYMMetrical
clock for the ZaOA, which has a zero level < 0.4SV and a one level>
4.4V. This clock is also divided by two to produce a 1.8408 MHz clock
which the datacoMM chip (U613) uses to produce baud rates.
lOOA
The laOA Microprocessor perforMS the Major control and data Manipula-
tion functions of the processor peA. It provides addresses and control
signals to read and write data frOM and to both MeMory and I/O ports.
It also responds to two externally generated interrupts, NNMI and NINT,
which, when enabled, interrupt current execution and cause the ZaOA to
branch to its interrupt service routine. The ZBOA also responds to a
bus request signal, NBUSREQ, allowing the CRTC control of the systeM
b u ~:)es .
At power up (or reset) the ZaOA begins executing instructions frOM
prograM MeMory beginning at address OOOOH. A routine is executed which
initializes variables and devices according to inforMation contained in
non-volatile MeM()ry (CMOS) and perforMS a self test of ROM and RAM. If
an error is detected a series of beeps are issued to the keyboard which
indicate the failing ROM or RAM. After inintialization the prograM
enters a Major 10()P responding to inputs frOM the keyboard and datacoMM
por'ts.
Three 74LS244's (U4'7,U57,U511) buffer the address and control lines
frOM the Z80A. The 1 of a decoder, U76, is used to separate prograM
MeMory into six blocks, each BK bytes long. The addressed ROM is en-
abled during a MeMory read by the TNRD and TNMREQ signals ()r during an
instructi()n fetch by the NMl signal. Since the tiMe to read the data
in an instruction fetch is less than that for a MeM()ry read, the NM1
signal was used to provide an early enable of the ROM allowing it to
respond within the required tiMe. ROMs with access tiMes of 350 ns
frOM address or 300 ns frOM enable are required t() run the systeM at
full speed. [PROMs or ROMs with 450 ns access tiMes frOM address May
be used by installing JUMper WS and reMoving JUMper W6, which causes
the ZaOA to wait one cycle l()nger during instructi()n fetches. The quad
latch U610 and ass()ciated gating provides the required wait signal to
th~:~ ZBOA.,

13220
Processor Module
13220-91087/08
Rev JAN-04-82
3.1.3
I/O Ports
CMUS
The Z80A is capable of addressing 2S6 different input/output ports.
I/O addresses froM the ZaOA appear on address bits AO-A7 and the
accuMulator contents appear on bits A8-A1S. I/O addresses 0-7FH are
used to access locations in the nonvolatile CMOS RAM, U73, where
configuration data is stored. Since the CMOS RAM is not fast enough to
respond within the I/O cycle tiMe a wait state is generated (by U6l0)
each tiMe the CMOS RAM is accessed. Diodes CR6-CR8 ensure that around
S volts is always on t~e CMOS supply pin. EMMitter follower Circuit,
Q3, Makes sure that during a power off the CMOS is always disabled
before the l80A buses beCOMe undefined and reMains so until buses
beCOMe defined at power on. During power off the battery Maintains
CMOS contents. If power on configuration is to be fixed, the COMS RAM
May be replaced by an HM7611 PROM (however it Must be realized that the
standard read/COMpleMent/write test for the CMOS self test would show a
CMOS error since the prOM cannot be written).
DATACOMM
The SY6SS1 Asynchronous COMMunications Interface Adapter perforMS the
parallel to serial conversion, error detection and baud rate generation
functions required for serial data COMMunication. It appears to the
laOA as four read only and four write only ports with address bit TA2
selecting the read/write function. This is done to COMpensate for the
unique tiMing of the 6500 series devices. The SY6551 is selected by
the rising edge of SELDC which is inverted frOM U24, the 1 of 8
decoder. The addresses of the SY6SS1 (U613) are AO-A7H.
The status inputs of the SY6SSl produce undesirable results and
therefore are forced to their active low states while the necessary
status signals are routed through another port. RS-232 line driver,
USi4, and receiver, U614, are ~sed to convert frOM TTL levels to RS-232
levels (+-12V) and vice versa. TranSMitted signals are: send data
(SD), terMinal ready (TR), request to send (RS) and optional control
driver 1 (OCD1). Received signals are: receive d~ta (RD), data Mode
(DM), optional control receiver 1 (OCR1), and clea~ to send (eS).
The datacoMM subsysteM operates in an asynChronous, full-duplex, point-
to-point environMent. Characters May be tranSMitted and received
siMultaneously (full-duplex) with character flow occurring over randOM
tiMe intervals (asynchronous). To achieve hardware synchronization
each character is fraMed by a start bit and a stop bit (2 stop bits at
110 baud). The addition of the fraMing bits for tranSMitted characters
and the detection of fraMing bits for the received characters are done
by the SY65S1. The parity (for error detection) of the character is
selectable (in the datacoMM configuration Menu) and is also generated
and detected by the SY6SS1 which reports errors (parity, fraMing, and
overrun) to the ZaOA by Means of a status register in the SY6SS1 which
is read when a character is received. The data tranSMission and
reception rates are set by the ZaOA in an internal reqister within the
SY6SS1.

13220
Processor Module
13220-91087/09
Rev JAN-04-82
Rates are selectable (in the datacoMM configuration Menu) frOM 110 to
9600 baud.
The datacoMM status inputs and outputs provide the necessary control
lines to connect the terMinal to a host COMputer via a ModeM, or to
provide direct hardware handshaking between the terMinal and host. At
power-on the TR and RS lines are activated to indicate that the
terMinal is ready. Upon receipt of a ModeM disconnect escape sequence
(esc f) the TR line is brought inactive for .about two seconds to
disconnect the ModeM. The presence of a ModeM connection is detected
by DM which causes the indicator "LED" (an asterisk '*') to be
displayed on the bOttoM center of the display. The CS signal frOM the
host when active allows the terMinal to tranSMit data and goes inactive
to halt tranSMission (the terMinal May ignore CS depending on datacoMM
configuration). The state of OCDl is controlled by a configuration
strap with its default state being low (inactive). This line selects
the ModeM rate for dual speed ModeMS. OCRl is Monitored in datacoMM
self test to detect the presence of the loopback test hood. All ModeM
status lines are active high (+12V).
Upon receipt of a character frOM datacoMM the SY6SS1 generates an
interrupt signal (NINT) to the lBOA. This causes the ZaOA to branch to
the datacoMM interrupt service routine which reads the SY6S51 status,
clearing the interrupt, and if no errors are present, inputs th~
character and places it into the datacoMM buffer in RAM. Characters
for which errors (parity, fraMing or overrun) are present cause a
delete character to be placed in the buffer.
Teus PORTS
The reMaining I/O ports are buffered to the ZaOA data bus by the
biderectional bus driver, U37. This was done because of data bus
loading. The signal TNRD selects the direction of the driver which is
enabled for all I/O accesses except CMOS RAM and datacOMM.
U25
forMS the keystatus port located at address 80H. The keystatus
port returns the status of 8 keys at a tiMe, which keys are deterMined
by th~ keyboard/display port (U26). Four bits of the key address
(colUMn address) are supplied by U26 (located at address B8H) and three
More frOM the eRTC scan line outputs (row address). As the row address
(scan line count) frOM the CRTC change, keystates are clocked into the
keystatus shift register (a high bit indicating key active) frOM which
they are later read. The colUMn address is increMented (during an NMI)
for each of the first sixteen display rows thereby scanning the entire
range of keyboard addresses.