IBM System/370 145 Service manual

System/370
Model 145
Reference Summary
S229-2239-1
IBM Corporation, Field Support Documentation, Dept 927,
Rochester, Minnesota 55901

PREFACE
This publication is primarily intended for
customer engineers servicing System/370
Model 145.
Second Edition (September 1972)
This
is a major revision of, and makes
8229-2239-0 obsolete.
Address any comments concerning the contents
of this publication to: IBM, Field Support
Documentation, Dept 927, Rochester,
Minnesota 55901
© International Business Machines Corporation 1972

Section 1 - Control Words
Branch and Module
CONTENTS
Switch Word
"O" . . . 1. 1
Branch Word . . . . . 1.2
GA Function Charts . 1.3
GA Function Charts . 1.4
GA Function Charts . 1.5
Branch and
Link or Return Word . 1.6
Word Move Word Version"O" .
1. 7
Word Move Word Version
"1" . . . 1.8
Storage Word, Non K-Addressable . 1.9
Storage Word, K-Addressable . . . 1.10
Arithmetic Word 10 Byte Version 1.11
Arithmetic Word, Fullword Version 1.12
Arithmetic Word, 11 Direct
ByteVersion . . . . . . . . . . 1.13
Arithmetic Word, 10/11 Indirect
Byte Version . . . 1.14
ALU Entry Gating 1.15
Stat Set Symbols . 1.15
BranchSymbols . 1.15
Arithmetic Word Chart Selection 1.16
Address Formation Chart 1.16
Control Word Chart Selection 1.16
Section 2 - CPU
3145 CPU Data Flow . 2.1
I-Cycles Data Flow . 2.2
I-Cycles . . . . . . . . 2.3
PSW Locations . . . . 2.3
Expanded Local Storage . 2.3
I-Cycles . . . . . . . . . . 2.3
I-Cycles Control Line Generation . 2.4
Control Word . . . . . . . 2.4
Control Register Decode . . . . . 2.4
iii

ECCL Board Layout ............ 2.5
Data Bit Location Chart
.......... 2.5
Common Test Points ............ 2.6
3145 CPU BSM Addressing ......... 2.6
Main Storage Frame -128K ........ 2.6
3345
Main Storage Frame -256K ..... 2.6
CPU SAR Bits 15, 16, and 17 ....... 2.6
Memory Troubleshooting Procedure
... 2.7
Example Chart for Array
Card Outputs
of Phase 21 Memory .... 2.8
Cycle Length ................ 2.9
Local Storage Timing Chart . . . . . . . 2.10
External Destination Timing Chart . . . 2.11
Gate Layouts . . . . . . . . . . . . . . . 2.13
CPU Clock Information ......... 2.14
Trap Locations and Routines . . . . . . 2.15
Feature Code Listing . . . . . . . . . . . 2.17
Feature Code Listing . . . . . . . . . . . 2.18
Feature Code Listing . . . . . . . . . . . 2.19
Feature Code Listing . . . . . . . . . 2.20
370 Coreload Feature Part Numbers .. 2.21
370 Coreload Feature Part Numbers . . 2.22
ALO Page Index ............. 2.23
ALO Page Index ............. 2.24
ALO Page Index ............. 2.25
ALO Page Index ............. 2.26
ALO Page Index . . . . . . . . . . . . . 2.27
ALO Page Index . . . . . . . . . . . . . 2.28
ALO Page Index ............. 2.29
ALO Page Index . . . . . . . . . . . . . 2.30
Console Indicators -Logic Reference . . 2.31
Upper Roller -Logic Reference 2.32
Lower Roller -Logic Reference . . . . . 2.33
Section 3 - Console File (23FD)
Console File Control and Data Flow ... 3.1
iv

Compare Mode . . . . 3.2
Control Commands . . 3.2
Operation Commands . 3.2
Console File Disk Address (CFDA)
Byte 3.2
Console File Control Functions 3.3
CF Error Checks . . 3.4
Byte Format . . . . . . . 3.5
Section 4 - Channels
MPX Channel Data Flow
4.1
UCW Addressing Table . 4.2
Byte MPX
UCW . . . . . 4.2
Selector Channel Data Flow 4.3
Standard Device
Addresses . 4.4
Word Buffer . . . . . . . 4.4
Block Multiplex Feature . . 4.5
UCW Pool . . . . . . . . . . 4.6
UCW Assignment Registers . 4.6
UCW Format . . . . . . . . . 4.6
Section 5 - Integrated File Adapter
(IFA)
IFA Data Flow . . . . . . 5.1
General Status Indications 5.2
I FA In-Line Tests . . . 5.2
IFA Information. . . . . . 5.3
I FA Sense Information . . 5.3
Control Words Forced
for I FA
Share Cycles . . . . . . . . . . 5.4
IFA Local Storage Assignments 5.5
IFA CS Area . . . . . . . . . . . . 5.5
I FA Drive Interface . . . . . . . 5.7
I FA Latches Logic References . . 5.8
Section 6 - Console Printers
3210 Control and Data Flow 6.1
3215 Control and Data Flow 6.2
Alter/Display Functions 6.3
v

Console Printer Valid Addresses ..... 6.4
Section 7 - Features Addr Adj Clock
Comparitor, CPU Timer
PSW Format . . . . . . . . . . . . 7.1
Address Translate Process Overview . 7.2
Address Translate Process . . . . . . 7.3
Address Translate Process . . . . . . 7.4
Clock Comparitor CPU Timer (CPT) . 7.6
Section 8 - Software and Logouts
System/370 Instructions Set . . . . . 8.1
Information Retrieval Under DOS/360 . 8.2
Control Registers . . . . . . . . 8.4
CPU Independent Logout . 8.5
Machine Check Interrupt Code . 8.6
Model 145 Machine Dependent Log . 8.7
1/0 Communications Area . . . . . . 8.9
I FA Extended Logout . . . . . . . 8.10
MPX Channel Machine Dependent Log 8.10
Selector Channel/Block Multiplex
Channel Dependent
Log 8.10
ECC Recording 8.11
ECC Recording 8.12
Section 9 - Power
Power Supplies . 9.2
Power Reference Manual . . . . . . .
9.3
Relay Function and Location Chart . 9.4
Initial Regulator Adjustment
for Power-Up Procedure .
9.5
Power-On Sequence . 9.6
Start Line Tips . . . . . 9.10
System Checklist . . . . 9.10
Voltage Levels -Scoping Information 9.13
Miscellaneous Part Numbers . . . . . 9. 16
Section
10- Micro Diagnostics
Basic Diagnostic
FLT. . ...... 10.1
vi

Basic Diagnostic Information ..
Diagnostic Functions ..... .
Local Storage
Map (Diagnostic) .
Diagnostic Test Listing
..
Section 11 - Maps
External Assignment Chart
External Address Line Decoding
External Gating
to A-Registers
FAT· Diagnostic Usage
Expanded Local Storage Map
Local Storage . . . . . . . . .
Local Storage . . . . . . . . .
Control Registers Bit Definitions
Direct Addressable Control Storage
Map ............... .
vii
10.2
10.3
10.4
10.5
11.1
11.2
11.2
.11.27
.11.30
.11.31
.11.32
.11.33
.11.36

INDEX
Section 1 - Control Words
.................
Section 2 - CPU
.........................
Section 3 - Console File .................. .
Section 4 - Channels . . .
................. .
Section 5 - IFA ........................ .
Section 6 - Console Printer
................ .
Section 7 - Features, Address Adjust, Clocks
...
Section 8 - Software and Logout ........... .
Section 9 - Power and
MST General ........ .
Section
10 -Diagnostics ................. .
Section
11 - MAPs ...................... .
ix
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(KFieldl
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GA, A·, KhO
1
Set Poll Control (Soft) Reset Poll Control Set Channel 1 Channel Reset
2
Set Poll Control (Hdwr) Reset Retry Holdup Set Channel 2 Chain Reset
3
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4
Set Channel 4
5 Set Count Ready Start I /0 Reset
Set Channel Loaded
Reset Channel Loaded
6
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Set Control Check
Set CC Diag Buffer
Shift
...
7
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WLR Sample
Set PCI Reset
Interrupts
w 8
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Share Req
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9
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A
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Bus-In to GR
•set Data Out
c Set Op Out
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Diag Set GR Full
D Interface Control Check
Diag Serv Signal •set Service Out
Reset PCI
E
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Reset Halt 1/0
F
*Also Set Retry Holdup

h Set GAL
Reset GAL
K Field GA,
OR, KOh GA, A-, KOh
1 Set Increment Length Reset FCS
2
Set Prog Check Reset
PCI
3
Set Prot Check
Reset Trap Req
4
Set Channel Control Check Reset
CCWO and
5
Set Allow Restart
WLR
Reset Lo Prior Req
6 Chain
End Reset
7
Set Contingent Con Reset Contingent1
8
Set Allow IDA
Con
9
Set Channel Busy Reset Channel Busy
A
Set Interrupt Latch Reset
Interrupt Latch
B
Set CUB Reset CUB
c
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D
Set Low Prior Req Rst
H/L Comp,CC Er
E
Set IFA Inhibit Traps
Rst IFA lnh Traps
F
Set GAH
GA,
OR, KhO
Set IF A Channel Gate
Set Channel 2 Gate
Set Channel 3 Gate
Set Write Clock Gate
Set CS,CR,ln Latches
Set CS,CR ,Out Latches
Set MS,CR,ln Latches
Set MS,CR,Out Latches
Set Control Pulse
Diag Read Data
Diag Clock
Gap Sense
Diag Data Gap Sense
Set Data Field Latch
Iii
Reset GAH
GA, A-.
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Reset Command
Overrun
Machine Reset
Reset
Orientation
Latch
Reset Count Ready,
In.Out
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CE End Op SS
Diag Index
D1ag Raw Data Pulse
Set D1ag Read Gate
B 1t Ring Advance
Set Diag Mode Latch
Reset Diag Mode
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HH
Set GA Straight Reset GA Straight
GA or KHH
11 Set Diag Block Share Not Used •
Cycle - All Channels
22
Reset Diag Block Share
Cycle
Latch· All Not Used
Channels
Reset Blk MPX UCW
Latch
33 Diag Check Reset Not Used
All Channels
44 Set Diagnostic Function
Latch and Diag Reset Not Used
Exp LIS
66 Reset
UCW Scan Latch
All Channels Not Used
Allow
Trap Latch
Set/Reset
88 Set
UCW Scan Latch
All Channels
Block
Trap Latch
Set/Reset
FF Reset Diagnostic Not Used
Function Latch
1.5

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of the •t11 oddr- ofter updoti"I·
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For Holfwon:t epe1t1t1ona .. 2
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6. A zeta is forced for l:wanclt 1- wf>efl SOC i1 specified.
7. Ths S or P ,..,,,... connot be the destuiohon of Ol'I up·
....................
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