Icom IC-F1721D User manual

VHF MOBILE TRANSCEIVERS
iC-f1721/d
iC-f1710
iC-f1821/d
iC-f1810
SERVICE
MANUAL

INTRODUCTION DANGER
This service manual describes the latest service information
for the IC-F1721/D/F1710/F1821/D/F1810 VHF MOBILE
TRANSCEIVER at the time of publication.
6 versions of the IC-F1721 have been designed. This service
manual covers each version.
MODEL
IC-F1721D
IC-F1721
IC-F1710
IC-F1821D
IC-F1821
IC-F1810
VERSION
USA-02, USA-03
USA-04
EUR-02, GEN-02
USA-02, USA-03
USA-04
EUR-02, GEN-02
10 KEY
None
Ye s
TX power
50 W
25 W
50 W
25 W
IC-F1700 series
IC-F1800 series
ORDERING PARTS
Be sure to include the following four points when ordering
replacement parts:
1. 10-digit order numbers
2. Component part number and name
3. Equipment model name and unit name
4. Quantity required
<SAMPLE ORDER>
1110003490 S.IC TA31136FN IC-F1721 MAIN UNIT 5 pieces
8820001210 Screw 2438 screw IC-F1721 Chassis 12 pieces
Addresses are provided on the inside back cover for your
convenience.
NEVER connect the transceiver to an AC outlet or to a DC
power supply that uses more than 16 V. This will ruin the
transceiver.
DO NOT expose the transceiver to rain, snow or any liquids.
DO NOT reverse the polarities of the power supply when
connecting the transceiver.
DO NOT apply an RF signal of more than 20 dBm (100mW)
to the antenna connector. This could damage the trans-
ceiver's front end.
REPAIR NOTES
1. Make sure a problem is internal before disassembling the
transceiver.
2. DO NOT open the transceiver until the transceiver is dis-
connected from its power source.
3. DO NOT force any of the variable components. Turn them
slowly and smoothly.
4. DO NOT short any circuits or electronic parts. An insulat-
ed turning tool MUST be used for all adjustments.
5. DO NOT keep power ON for a long time when the trans-
ceiver is defective.
6. DO NOT transmit power into a signal generator or a
sweep generator.
7. ALWAYS connect a 40 dB to 50 dB attenuator between
the transceiver and a deviation meter or spectrum ana-
lyzer when using such test equipment.
8. READ the instructions of test equipment thoroughly
before connecting equipment to the transceiver.
To upgrade quality, any electrical or mechanical parts and
internal circuits are subject to change without notice or
obligation.
Icom, Icom Inc. and are registered trademarks of Icom Incorporated (Japan) in the United States, the United Kingdom,
Germany, France, Spain, Russia and/or other countries.

SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
SECTION 3 DISASSEMBLY INSTRUCTIONS
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4-2 TRANSMITTER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
4-3 PLL CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4-4 POWER SUPPLY CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4
4-5 OTHER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
4-6 PORT ALLOCATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
SECTION 5 ADJUSTMENT PROCEDURES
5-1 PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
5-2 LCD CONTRAST ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5-3 SOFT WARE ADJUSTMENT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
SECTION 6 PARTS LIST
SECTION 7 MECHANICAL PARTS AND DISASSEMBLY
SECTION 8 SEMI-CONDUCTOR INFORMATION
SECTION 9 BOARD LAYOUTS
9-1 FRONT-A UNIT (for IC-F1700 series) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9-2 FRONT-B UNIT (for IC-F1800 series) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
9-3 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1
SECTION 10 BLOCK DIAGRAM
SECTION 11 VOLTAGE DIAGRAM
11-1 FRONT-A UNIT (for IC-F1700 series) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1
11-2 FRONT-B UNIT (for IC-F1800 series) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
11-3 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
TABLE OF CONTENTS

■GENERAL
• Frequency coverage : 136.000–174.000 MHz
• Type of emission :
• Number of conventional channels : max 256 channels
• Antenna impedance : 50 Ω
• Operating temperature range : –30˚C to +60˚C (–22˚F to +140˚F)
• Power supply requirement : 13.6 V DC nominal [USA], [GEN]
(Negative ground) 13.2 V DC nominal [EUR]
• Current drain (Approx.) :
• Dimensions (projections not included) : 175(W) × 45(H) × 170(D) mm; 67⁄8(W) × 125⁄32(H) × 611⁄16(D) in
• Weight (Approx.) : 1.5 kg; 35⁄16 lb
■TRANSMITTER
• Output power : 25 W [F1710], [F1810]
50 W [F1721/D], [F1821/D]
• Modulation : Variable reactance frequency modulation
• Maximum permissible deviation : ±5.0 kHz (Wide), ±4.0 kHz (Middle), ±2.5 kHz (Narrow)
• Frequency error : ±2.0 ppm [USA], [GEN]
±0.85 kHz [EUR]
• Spurious emissions : 75 dB (typical) [USA], [GEN]
0.25 µW (≤1 GHz), 1.0 µW (>1 GHz) [EUR]
• Adjacent channel power : 70 dB min. for Wide and Middle
60 dB min. for Narrow
• Audio harmonic distortion : 3% typical (Mod. 1 kHz, 40% deviation)
• Limiting charact of modulator : 70–100% of maximum deviation
• Microphone impedance : 600 Ω
■RECEIVER
• Receive system : Double conversion superheterodyne system
• Intermediate frequencies : 1st IF: 46.35 MHz, 2nd IF: 450 kHz
• Sensitivity : 0.25 µV (–119 dBm) typical at 12 dB SINAD [USA], [GEN]
–4 dBµV emf typical at 20 dB SINAD [EUR]
• Adjacent channel selectivity : 70 dB min. (80 dB typical) for Wide and Middle
60 dB min. (75 dB typical) for Narrow
• Spurious response : 70 dB min. (80 dB typical)
• Intermodulation rejection ratio : 70 dB min. (77 dB typical) for Wide [USA], [GEN]
70 dB min. (75 dB typical) for Narrow [USA], [GEN]
65 dB min. (70 dB typical) [EUR]
• Audio output power
(Internal) : 4 W typical at 10% distortion with a 4 Ωload
(External) 22 W typical (BTL) at 10% with a 4 Ω load (D-SUB 25 connector)
• Squelch sensitivity (at threshold) : 0.25 µV typical [USA], [GEN]
–4 dBµV emf typical [EUR]
• Output impedance (Audio) : 4 Ω
Specifications are measured in accordance with EIA-152-C/204D, TIA-603 or EN 300 086.
All stated specifications are subject to change without notice or obligation.
S SECTION 1 SPECIFICATIONS
1 - 1
VERSION WIDE MIDDLE NARROW
[USA]
16K0F3E (25.0 kHz) N/A 11K0F3E (12.5 kHz) [GEN] 8K50F3E (12.5 kHz)
[EUR] 14K0F3E (20.0 kHz)
RECEIVING TRANSMITTING
Stand-by Max. audio at 50 W at 25 W
600 mA 1200 mA 14.0 A 7.0 A

2 - 1
SECTION 2 INSIDE VIEWS
•Bottom view
•MAIN UNIT
Top view
Digital CPU (IC20:
HD64F2239TE16
for IC-1721D/1821D
only)
PLL IC
(IC4: LMX2352TM)
APC circuit
(IC37: TA75S01F)
Mixer circuit
Base band IC
(IC2: AK2346)
D/A converter
(IC8: M62364FP)
+5V regulator
(Q31: 2SB1132)
AF amplifier
(IC38: LA4425A)
D/A converter
(IC30: M62334PP)
RX/TX VCO
circuit
IF amplifier
(Q6: 2SC4215)
Power amplifier
IC29:
S-AV32 for
IC-F1721/D,
F1821/D
S-AV33 for
IC-F1710,
F1810
DTMF decoder
(IC6: LC7382M)
FM IF IC
(IC12: TA31136FN)
RF amplifier
(Q24: 3SK293)
YGR amplifier
(Q23: 2SC3356)
Reference crystal
oscillator
(X2: CR-794 15.3 MHz)
APC circuit
VCO switch circuit
(Q17: XP1214,
Q18: DTC144EU)
Low-pass filter
(IC1: NJM129024)
A/D converter (IC16: AD7476ARTZ for IC-F1721D/IC-F1821D only)
Digital DSP
(IC41:
TMS320VC5416PGE120 for IC-F1721D/IC-F1821D only)
MAIN CPU
(IC23: HD64F2268F)
+8V regulator
(IC36: TA7808F)
T8V regulator
(Q34: 2SD1664)
Power switch
(Q42: 2SJ377)
Ceramic filter
(FI1: CFWM450E
for wide)
Ceramic filter
(FI2: CFWM450G
for narrow)

2 - 2
•FRONT-B UNIT (IC-F1800 series)
•FRONT-A UNIT (IC-F1700 series)
Backlight
dimmer control
ALC amplifier
(IC9: AN6123MS)
Mic amplifier
(IC5: TC75S51F)
LCD driver
(IC7: SED1526F0A)
Reset IC
(IC2: S-80942CNMC)
Mic switch
(IC8: TC4W53F)
Q3: 2SC4116
Q4: DTC114TU
Q5: DTC114TU
Front CPU
(IC3: HD64F3687)
Reset IC
(IC2: S-80942CNMC)
LCD driver
(IC7: SED1526F0A)
Mic amplifier
(IC5: TC75S51F)
Mic switch
(IC8: TC4W53F)
ALC amplifier
(IC9: AN6123MS)
Backlight
dimmer control
Q3: 2SC4116
Q4: DTC114TU
Q5: DTC114TU
Front CPU
(IC3: HD64F3687)

3 - 1
SECTION 3 DISASSEMBLY INSTRUCTIONS
•REMOVING THE FRONT UNIT
1Unscrew 4 screws, A, then remove the bottom cover.
wUnplug J1(B) and J6 (C).
3Unscrew 2 screws, D.
4Remove the front unit in the direction of the arrow.
•REMOVING THE MAIN UNIT
1Remove the bushing, L.
wRemove the MAIN unit in the direction of the arrow.
J1 J6
A
B
C
D
D
L
E
F
•BEFORE REMOVING THE MAIN UNIT
1Unscrew 8 screws, Eand remove the shield plate F.
G
H
I
J
K
2Unscrew 4 screws, Gand remove the shield cover H.
3Unsolder 3 points, Iand 5 points J.
4Remove 2 clips, K.
Continue to right above

4 - 1
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS
4-1-1 ANTENNA SWITCHING CIRCUIT (MAIN UNIT)
The antenna switching circuit functions as a low-pass filter
while receiving and a resonator circuit while transmitting.
This circuit does not allow transmit signals to enter the
receiver circuits.
Received signals enter the antenna connector (CHASSIS;
J1) and pass through the low-pass filters (L42–L44, C375,
C388, C389, C391, C432, C461). The filtered signals are
passed through the λ⁄4type antenna switching circuit (D29,
D30) and then applied to the RF circuit.
4-1-2 RF CIRCUIT (MAIN UNIT)
The RF circuit amplifies signals within the range of fre-
quency coverage and filters out-of-band signals.
The signals from the antenna switching circuit pass
through the two-stage tunable bandpass filters (D23, D26,
L32, L36). The filtered signals are amplified at the RF
amplifier (Q24) and then passed through the another two-
stage tunable bandpass filters (D17, D18, L28) to suppress
unwanted signals. The filtered signals are applied to the
1st mixer circuit.
D17, D18, D23 and D26 employ varactor diodes, that
are controlled by the MAIN CPU (IC23) via the D/A con-
verter (IC30, pins 1, 2), to track the bandpass filter. These
varactor diodes tune the center frequency of an RF
passband for wide bandwidth receiving and good image
response rejection.
4-1-3 1ST MIXER AND 1ST IF CIRCUITS (MAIN UNIT)
The 1st mixer circuit converts the received signals into
fixed frequency of the 1st IF signal with the PLL output fre-
quency. By changing the PLL frequency, only the desired
frequency passes through a monolithic filter at the next
stage of the 1st mixer.
The RF signals from the bandpass filter are mixed with
the 1st LO signals, where come from the RX VCO circuit
(Q11, D6, D7) via the LO amplifier (Q21) and low-pass
filter (L24, C246, C264), at the 1st mixer circuit (D16, L22,
L23) to produce a 46.35 MHz 1st IF signal. The 1st IF sig-
nal is passed through a monolithic filter (FI4) to supplies
unwanted signals and to pass only the desired signals after
being amplified at the IF amplifiers (Q10, Q13, Q14). The
filtered signal is applied to the 1st IF amplifier (Q6) and
then applied to the 2nd IF circuit.
4-1-4 2ND IF AND DEMODULATOR CIRCUITS
(MAIN UNIT)
The 2nd mixer circuit converts the 1st IF signal into a 2nd
IF signal. The double-conversion superheterodyne system
(which convert receive signals twice) improves the image
rejection ratio and obtains stable receiver gain.
The 1st IF signal from the IF amplifier (Q6) is applied to
the 2nd mixer section of the FM IF IC (IC12, pin 16), and
is mixed with the 2nd LO signal to be converted into a
450 kHz 2nd IF signal.
The FM IF IC (IC12) contains the 2nd mixer, limiter ampli-
fier, quadrature detector, active filter and noise amplifier
circuits.
FI1
FI2
2nd IF filters
450 kHz
Noise
detector
Q1
Limiter
amp.
Quadrature
detector
Active
filter
AF signals
5V
X4 Discriminator
IC8
RSSI
Mixer
X2
15.3 MHz
45.9 MHz
1st IF from the IF amplifier (Q6)
NOIS signal to the CPU (IC23: pin 37)
8
2
1
75
BPF
32
3
161311109
IC12
TA31136FN
• 2ND IF AND DEMODULATOR CIRCUITS

4 - 2
A 2nd LO signal (45.9 MHz) is produced at the PLL circuit
by tripling it’s reference frequency (15.3 MHz).
The 2nd IF signal from the 2nd mixer section (IC12, pin 3)
passes through the ceramic filter (Wide: FI1, Narrow: FI1,
Fl2) to remove unwanted heterodyned frequencies. It is then
amplified at the limiter amplifier section (IC12, pin 5) and
applied to the quadrature detector section (IC12, pins 10,
11) to demodulate the 2nd IF signal into AF signals.
The demodulated AF signals are output from pin 9 (IC12)
and applied to the base band IC (IC2).
4-1-5 AF AMPLIFIER CIRCUIT (MAIN UNIT)
The AF amplifier circuit amplifies the demodulated AF sig-
nals to drive a speaker. This transceiver employs the base
band IC which is composed of pre-amplifier, expander,
scrambler, MSK de-modulator, etc. at the AF amplifier sec-
tion.
The AF signals from the FM IF IC (IC12, pin 9) are passed
through the DA switch (IC42, pins 2, 15) and are then
applied to the base band IC (IC2, pin, 23). The signals are
amplified at the AF amplifier section in the base band IC (IC2,
pin 23), and are then applied to the high-pass filter and low-
pass filter section of it.
The filtered signals pass through the high-pass filter to sup-
press unwanted harmonic components. The signals pass
through (or bypass) scrambler and expander sections. The
signals are amplified at the amplifier section in the base
band IC (IC2).
The output signals from IC2 (pin 20) are applied to the AF
volume (IC8, pins 15, 16), and are then applied to the AF
power amplifiers (IC34 pins 3, 4, IC38 pins 1, 4) after pass
through the analog switches (IC42 pins 3, 4 and IC43 pins 1,
15).
The power amplified AF signals are applied to the internal
speaker (IC-F1700 series only) that is connected to J6 via
[EXT SP] jack (J5).
4-1-6 SQUELCH CIRCUITS (MAIN UNIT)
• NOISE SQUELCH
A squelch circuit cuts out AF signals when no RF signals
are received. By detecting noise components in the AF sig-
nals, the squelch circuit switches the AF amplifier controller.
Some noise components in the AF signals from the FM IF
IC (IC12, pin 9) are passed through the D/A converter (IC8,
pins 1, 2). The signals are applied to the active filter section
in the FM IF IC (IC12, pin 8). The active filter section filters
and amplifies noise components. The amplified signals are
converted into the pulse-type signals at the noise detector
section. The detected signals output from pin 13 (NOIS) via
the noise comparator section.
The “NOIS” signal from the FM IF IC is applied to the MAIN
CPU (IC23, pin 37). Then the MAIN CPU analyzes the noise
condition and outputs the AF mute signal as “AFON” from
the pin 19 to the AF power controller (Q28, Q29, D34, D36).
• CTCSS AND DTCS
The tone squelch circuit detects tone signals and opens the
squelch only when receiving a signal containing a matching
subaudible tone (CTCSS or DTCS). When tone squelch is in
use, and a signal with a mismatched or no subaudible tone
is received, the tone squelch circuit mutes the AF signals
even when noise squelch is open.
A portion of the AF signals from the FM IF IC (IC12, pin 9)
pass through the low-pass filter (IC1, pins 8, 10) to remove
AF (voice) signals, and are then applied to the amplifier (IC1,
pins 5, 7). The amplified signals are applied to the CTCSS
or DTCS decoder in the MAIN CPU (IC23, pin 46) via the
“CDEC” line. The MAIN CPU outputs the AF mute signal as
“AFON” from the pin 19 to the AF power controller (Q28,
Q29, D34, D36).
• AF AND MIC AMPLIFIER CIRCUITS
Base band IC
(IC2)
AF signal
from FM IF IC (IC12, pin 9)
23 20 AF
AMP
IC38
Speaker
IC5
IC43
IC1 IC8 D12
Microphone
AMP
3
7
4
FM/PM switch
D/A converter FM mod.
LPF
"CTCSS/DTCS" signal from
D/A conveter IC (IC8, pins 9, 10)
"TONE" signal from
D/A converter IC (IC8, pins 21, 22)
to TX VCO circuit
(Q12, D8, D9)
3
AMP
IC34
FRONT UNIT A/B
3
5
4
IC42
15 341 4
IC8
16
3
5
3
4
1
2
15
IC43
6
7
1
IC8
IC9
AMP
2
1
15
IC42

4 - 3
4-2 TRANSMITTER CIRCUITS
4-2-1 MICROPHONE AMPLIFIER CIRCUIT (MAIN UNIT)
The microphone amplifier circuit amplifies audio signals
within +6 dB/octave pre-emphasis 6characteristics from the
microphone to a level needed for the modulation circuit.
This transceiver employs the base band IC which is com-
posed of microphone amplifier, compressor, scrambler,
limiter, splatter filter, MSK modulator, etc. at the microphone
amplifier section.
The AF signals (MIC) from the microphone connector
(FRONT UNIT; J2, pin 6) are passed through the micro-
phone switch (FRONT UNIT; IC8, pins 1, 6, 7) and are then
applied (or bypass) to the ALC amplifier (FRONT UNIT; IC9)
for digital modulation. The signals are amplified at the micro-
phone amplifier (FRONT UNIT; IC5, pins 3, 4) and then
applied to MAIN UNIT via J1 (pin 10).
The amplified signals are applied to the microphone ampli-
fier section of the base band IC (IC2, pin 3). The amplified
signals are passed through (or bypass) the compressor,
scrambler sections of IC2, and are then passed through the
high-pass, limiter amplifier, splatter filter sections of IC2.
The output signals from the base band IC (IC2, pin 7) are
applied to the FM/PM switch (IC43, pins 12–14) after pass
through the DA switch (IC42, pins 12, 14). The signal are
passed through the low-pass filter (IC1, pins 4, 13) and then
applied to the D/A converter (IC8, pins 3, 4). The output sig-
nal from D/A converter (IC8, pin 3) are applied to the modu-
lation circuit (D12).
4-2-2 MODULATION CIRCUIT (MAIN UNIT)
The modulation circuit modulates the VCO oscillating signal
(RF signal) using the microphone audio signals.
The AF signals from the D/A converter (IC8, pin 3) change
the reactance of varactor diode (D12) to modulate the oscil-
lated signal at the TX VCO circuit (Q12, D8, D9). The modu-
lated VCO signal is amplified at the buffer amplifiers (Q20,
Q22) and is then applied to the YGR amplifier circuit via the
T/R switch (D19).
The CTCSS/DTCS signals (“CENC0”, “CENC1”, ”CENC2”)
from the MAIN CPU (IC23, pins 89–91) are combined at
resistors (R158, R159, R162) and are then pass through
the low-pass filter (IC9, pins 8, 10). The filtered signals are
applied to the D/A converter (IC8, pins 9, 10), and are then
mixed with the filtered microphone audio signals.
The mixed signals are applied to the D/A converter (IC8,
pin 3, 4) after pass through the low-pass filter (IC1, pins 4,
13). The output signal from D/A converter (IC8, pin 3) are
applied to the D12 in the VCO circuit.
4-2-3 YGR/POWER AMPLIFIER CIRCUITS (MAIN UNIT)
The YGR/power amplifier circuits amplify the VCO oscillating
signal to an output power level.
The signal from the VCO circuit passes through the T/R
switch (D19), and is amplified at the YGR (Q23), power (IC29)
amplifiers to obtain 50 W (IC-F1721/D/F1821/D; 25 W for
IC-F1710/F1810) of RF power.
The amplified signal is passed through the low-pass filter
(L35, C345, C346, C348, C349), antenna switching circuit
(D29, D30), low-pass filters (L42, L43, C375, C388, C389,
C391), power detector (D38, D40), low-pass filter (L44,
C432, C461), and is then applied to the antenna connector
(CHASSIS unit; J1).
The bias voltage of the YGR amplifier (Q23) and power
amplifier (IC29) are controlled by the APC circuit.
4-2-4 APC CIRCUIT (MAIN UNIT)
The APC circuit protects the power amplifier from a mis-
matched output load and stabilizes the output power.
The power detector circuit (D38, D40) detects the forward
signals and reflection signals and converts it into DC volt-
age. The output voltage is at a minimum level when the
antenna impedance is matched with 50 Ωand is increased
when it is mismatched.
The detected voltage is applied to the differential amplifier
(IC37; pins 3, 4), and the “T2” signal from the D/A converter
(IC30, pin 2), controlled by the MAIN CPU (IC23), is applied
to the other input for reference (IC37, pin 1). When antenna
impedance is mismatched, the detected voltage exceeds the
power setting voltage. Then the output voltage of the differ-
ential amplifier (IC37, pin 4) controls the bias voltage of the
YGR amplifier (Q23) and power amplifier (IC29) amplifiers to
reduce the output power.
Power
amp.
APC
amp.
YGR
amp.
+
–
VCC
to ANT unit
T2
TMUT
RF signal
from PLL circuit
T8V
APC control circuit
D40
D38
LPF
FOR
REV
Q23
IC37
IC29
• APC CIRCUIT

4-3 PLL CIRCUITS
4-3-1 PLL CIRCUIT (MAIN UNIT)
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL output com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
The PLL circuit contains the RX VCO (Q11, D6, D7) and
TX VCO (Q12, D8, D9). The oscillated signal is amplified
at the buffer amplifier (Q20). The output signal frequency is
doubled at Q19, and is then applied to the PLL IC (IC4, pin 6)
after being passed through the bandpass filter (Q5, D3, D5,
L4, L47, L48, C85, C104, C105, C123, C519–521).
Q5, D3 and D5 switch the filtering frequencies between TX
and RX which is controlled by TXC.
The PLL IC contains a prescaler, programmable counter,
programmable divider and phase detector, etc. The applied
signal is divided at the prescaler and programmable counter
section by the N-data ratio from the MAIN CPU. The divided
signal is detected on phase at the phase detector using the
reference frequency and output from pin 8. The output sig-
nal is passed through the loop filter (Q46, Q47) and is then
applied to the VCO circuit.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
4-3-2 VCO CIRCUITS (MAIN UNIT)
The VCO circuits contains a separate RX VCO (Q11, D6,
D7) and TX VCO (Q12, D8, D9). The oscillated signal is
amplified at the buffer amplifiers (Q20, Q22) and is then
applied to the T/R switch (D19, D20). Then the receive 1st
LO (Rx) signal is applied to the 1st mixer (L22, L23, D16)
and the transmit (Tx) signal to the YGR amplifier circuit (Q23).
A portion of the signal from the buffer amplifier (Q20) is fed
back to the PLL IC (IC4, pin 6) via the doubler circuit (Q19)
as the comparison signal.
4 - 4
4-4 POWER SUPPLY CIRCUITS
Line Description
HV The voltage from a DC power supply.
VCC
The same voltage as the HV line which is
controlled by the power switch circuit (Q41,
Q42). When the [ ] is pushed, the MAIN
CPU outputs the "PWR" control signal to the
power switch circuit to turn the circuit ON.
CPU 5
Common 5 V converted from the HV line
at the CPU5V regulator circuit (IC40). The
output voltage is applied to the MAIN CPU
(IC23) and EEPROM
(IC26), etc.
5V
Common 5 V converted from the CPU5V
line at the 5 V regulator circuit (Q31, Q32).
The output voltage is applied to the PLL IC
(IC4) and D/A converter IC (IC30), etc.
8V
Common 8 V converted from the VCC line
at the 8 V regulator circuit (IC36). The output
voltage is applied to the buffer amplifier (Q22)
and 1st LO amplifier (Q21), etc.
T8V
Transmit 8 V controlled by the T8V regulator
circuit (Q34) using the "TMUT" signal from
the MAIN CPU (IC23). The output voltage is
applied to the driver (Q23) and PA amplifiers
(IC29), etc.
R8V
Receive 8 V controlled by the R8V regulator
circuit (Q30) using the "TXC" signal from
the MAIN CPU (IC23). The output voltage is
applied to the RF amplifier (Q24) and 1st IF
amplifier (Q6), etc.
Shift register
×3
×2
Prescaler
Phase
detector
Loop
filter
Programable
counter
Programable
divider
X2
15.3 MHz
45.9 MHz signal
to the FM IF IC 16
Q11, D6, D7
RX VCO
TX VCO
Buffer
Buffer
Q22
Q19
Q20
Q1
Q46, Q47
19
18
17
PLST
IC4 (PLL IC)
SO
SCK
to transmitter circuit
to 1st mixer circuit
D20
D19
85
Q12, D8, D9
BPF
• PLL CIRCUIT

4-5 OTHER CIRCUITS
4-5-1 COMPANDER CIRCUIT (MAIN UNIT)
IC-F1700/F1800 series have compander circuit which can
improve S/N ratio and become wide dynamic range. The
circuit is composed in the base band IC (IC2).
(1) IN CASE OF RECEIVING
The demodulated AF signals from the FM IF IC (IC12, pin 9)
are applied to the amplifier section in base band IC (IC2, pin
23), and then pass through the low-pass and high-pass filter
section to suppress unwanted signals. The filtered signals
pass through (or bypass) scrambler section, and are then
applied to the expander circuit to expand AF signals.
The output signals from the base band IC (IC2, pin20)
is applied to the AF amplifier circuit after amplified at the
amplifier section.
(2) IN CASE OF TRANSMITTING
The audio signals from the microphone are applied to the
base band IC (IC2, pin 3) via microphone amplifier (FRONT
UNIT; IC5). The signals are amplified at the amplifier section,
and are then applied to the compressor circuit to compress
the audio signals. The signals pass through (or bypass)
scrambler section, and are then applied to the limiter section
after being passed through the high-pass filter.
The filtered signals pass through the splatter filter section,
and are then applied to the modulation circuit (D12) via the
FM/PM switch (IC43, pins12–14) and D/A converter (IC8,
pins 2, 3).
4-5-2 DIGITAL MODE CIRCUIT (IC-F1721D/F1821D only)
(1) IN CASE OF RECEIVING
Output signal from the FM IF IC (IC12, pin 11) is applied to
the IF amplifier (Q3), and is then amplified at the IF amplifier
(IC15, pins, 1, 4) after pass through the bandpass filter (FI3).
The amplified signal is applied to the DSP IC (IC41) via the
A/D converter (IC16, pin 3). The signal is processed at the
DSP IC (IC41) and is then applied to the LINER CODEC IC
(IC18, pin 16) to convert into an analog audio signal.
Output signal from the LINER CODEC IC (IC18) is applied
to the base band IC (IC2, pin 23) same as analog received
signal via the DA switch (IC42, pins 1, 15).
(2) IN CASE OF TRANSMITTING
Output signal from the base band IC (IC2, pin 7) is ampli-
fied at the MOD amplifier (IC44) and is then applied to the
CODEC IC to convert to into a digital signal. The signal is
processed at the DSP IC (IC41) and the DIGITAL CPU (IC20),
and then applied to the low-pass filter (IC13, pins 1–3) after
amplified at IC13 (IC13, pins 5, 7).
The signal is applied to the FM/PM switch (IC43, pins,
12–14) same as an analog transmit signal via the DA switch
(IC42, pins 13, 14).
4 - 5
Scrambler/
De-scrambler
TX/RX
HPF
Pre-
emphasis Limiter Splatter VR2
Expander VR4
RXA2
SMF
De-
emphasis
Com-
pressor
VR1
(HPF)
RX
LPF
VR3
(HPF)
7 MOD
18
19
20 SIGNAL
3TXIN
23RXIN
21SDEC
10
14MDIR
9
MTDT
MTCK
13MSCK
11MDIO
12MRDF
MSK
Modulator
MSK
Demodulator
MSK
BPF
Control
Register
TXA1
RXA1
BPF
From FM IF IC
(IC12, pin 11) To AF amplifier
ciruit
From
MIC amplifier
(FRONT UNIT; IC15)
To FM/PM SW
(IC43, pin 11)
DIGITAL
CPU
LPF
DA SW
AMP AMP
AMP AMP
Q3
IC42 IC13
RECEIVED SIGNAL
FI3
IC13
IC15 IC16
IC20 IC41 IC18 IC44
IC42
IC2
A/D
LINER
CODEC
IC
BASE
BAND
IC
DA SW
DSP
IC
TRANSMIT SIGNAL
• DIGITAL MODE CIRCUITS
• BASE BAND IC BLOCK DIAGRAM

4 - 6
4-6 PORT ALLOCATIONS
4-6-1 MAIN CPU (MAIN UNIT; IC23)
Pin
number
Port
name Description
1 DSDA I/O port for data signal to the D/A con-
verter (IC30 pin 6).
2 DAST Outputs strobe signals to the D/A
converter (IC8, pin 6).
10 SSO Outputs serial data to the PLL IC (IC4,
pin 15) and D/A converter (IC8, pin 8).
11 SCK
Outputs clock signal to the PLL IC (IC4
pin 14), D/A converter (IC8, pin 7),
etc.
13 PLST Outputs strobe signals to the PLL IC
(IC4, pin 16).
15 DASW
Outputs control signal to the digital
/analog switch (IC42).
Low: While analog mode is se-
lected.
16 TXC
Outputs the T8V regulator circuit
(Q34) control signal.
Low: During transmit.
17 TMUT
Outputs the R8V regulator circuit
(Q30) control signal.
Low: During receive.
18 AFON
Outputs control signal for AF mute
circuit (Q28, Q29).
High: While AF amplifier (IC38) is
activated.
19 NWC
Outputs wide/narrow switch (D2, D4)
control signal.
High: When narrow band is se-
lected.
20 DDSD Input port for serial data from the
DTMF decoder IC (IC6, pin 9).
21 DDAC Outputs clock signals to the DTMF
decoder IC (IC6, pin 10).
32 RMUT
Input port for the AF mute signal from
the optional unit via J2.
Low: While RX audio is muted.
33 MMUT
Input port for the microphone mute
signal from the optional unit via J2.
Low: While microphone audio is
muted.
34–36 OPT1–
OPT3 I/O ports for optional unit.
37 NOIS Input port for the noise signal from the
FM IF IC (IC9, pin 13).
38 POSW Input port for the [ ] switch.
Low: While [ ] switch is pushed.
39 DDST
Input port for DTMF detection signal
from the DTMF decoder IC (IC6,
pin 11).
40 IGSW Input port for the remote power con-
trol signal from external connector, J7.
41 PWON
Outputs control signal for the power
switch circuit (Q41, Q42).
Low: While power ON.
43 SENC Outputs single tone encoder signal.
Pin
number
Port
name Description
44 BEEP Outputs beep audio signals.
45 SDEC
Input port for single tone decode
signal from the base band IC (IC2,
pin 21).
46 CDEC Input port for CTCSS/DTCS signal
from the LPF (IC1, pin 7).
47 ULCK Input port for the PLL unlock signal.
Low: The PLL circuit is unlocked.
48 BATV Input port for the connected battery
for the low battery detection.
49 LVIN Input port for the PLL lock voltage.
50 RSSI Input port for the S-meter signal from
the FM IF IC (IC12, pin 12).
51 TEMP Input port for the transceiver’s internal
temperature detecting signal.
68 CLO Outputs the data signal to the FRONT
CPU (FRONT UNIT; IC3).
69 CLI Input port for the data signal from the
FRONT CPU (FRONT UNIT; IC3).
72 HORN
Outputs external device control signal.
High: When matched 5/2 tone sig-
nals are received.
78 MTCK
Input port for transmitting MSK clock
signal from the base band IC (IC2,
pin 9).
79 NTXD
Outputs NMEA data signals for the
connected unit via external connector
(J7).
80 NRXD
Input port for NMEA data signals from
the connected unit via external con-
nector (J7).
88 DIM
Input port for the LCD backlight con-
trol signal from the external connector
(J8).
Low: While LCD backlight is
dimmed.
89–91 CENC0–
CENC2 Output the CTCSS/DTCS signals.
93 MTDT Outputs the MSK data to the base
band IC (IC2, pin 10).
94 MDIR Outputs serial data control signal to
the base band IC (IC2, pin 14 ).
95 MDIO
I/O port for the serial data signals
from/to the base band IC (IC2,
pin 11).
96 MSCK Outputs clock signal for the base
band IC (IC2, pin 13).
97 PMFM
Outputs the the FM/PM switch (IC43,
pin 11) control signal.
High: While PM is selected.
98 ESDA I/O port for data signals from/to the
EEPROM (IC26, pin 5).

4 - 7
4-6-2 FRONT CPU (FRONT UNIT; IC3)
Pin
number
Port
name Description
7 RES Input port for rest signal.
19–22 KR0–
KR3
Input ports for the 10-keypad.
(IC-F1800 series only)
28, 29 LIGT1,
LIGT2
Output control signals for LCD back-
light.
47 LEDT Outputs control signal for the TX LED.
48 LEDR Outputs control signal for the RX LED.
51, 52 DICK,
DIUP
Input ports for control signal from the
dial (S9). (IC-F1700 series only)
53, 54 KYUP,
KYDN
Input ports for control signal from [ ],
[ ] keys. (IC-F1800 series only)
57 HANG
Input port for the microphone hanger
detection signal.
Low: When microphone on the
hanger.
58 PTT Input port for the PTT switch of the
connected microphone.
59–63 KYP0–
KYP4
Input ports for the programmable
function keys (P0–P4).
4-6-4 D/A CONVERTER (MAIN UNIT; IC30)
Pin
number
Port
name Description
1T1
Outputs the bandpass filters (D23,
D26) tuning signal.
2T2
• Outputs the bandpass filters (D17,
D18) tuning signal.
• Outputs the TX power control signal
which selects TX output power of
HIGH, LOW1 or LOW2. The output
signal is applied to the APC amplifier
(IC37, pin 1).
3 TXLVA Outputs TX VCO lock voltage.
4 RXLVA Outputs RX VCO lock voltage.
4-6-3 D/A CONVERTER (MAIN UNIT; IC8)
Pin
number
Port
name Description
2 SQL Outputs AF signal to the squelch cir-
cuit (IC12, pin 8).
3 MOD Outputs modulation signals to the
VCO circuit.
10 TENC Outputs CTCSS/DTCS signals.
11 BAL Outputs deviation balance control sig-
nal.
14 BEPV
Outputs beep audio signals to the
speaker via the AF amplifiers (IC34,
IC38).
15 SIGNAL Outputs AF signals to the speaker via
the AF amplifiers (IC34, IC38).
22 TONE Outputs single tone signal.
23 REF Outputs reference oscillator control
signal.
LIGT1 LIGT2 LIGHT
HIGH HIGH DIM
HIGH LOW OFF
LOW HIGH ON
LOW LOW OFF

▄ REQUIRED TEST EQUIPMENT
EQUIPMENT GRADE AND RANGE EQUIPMENT GRADE AND RANGE
DC power supply Output voltage
Current capacity
: 13.6 (13.2) V DC
: 20 A or more Audio generator Frequency range
Measuring range
: 300–3000 Hz
: 1–500 mV
Modulation analyzer Frequency range
Measuring range
: DC–600 MHz
: 0 to ±10 kHz Attenuator Power attenuation
Capacity
: 50 or 60 dB
: 100 W
Frequency counter
Frequency range
Frequency accuracy
Sensitivity
: 0.1–600 MHz
: ±1 ppm or better
: 100 mV or better
Standard signal
generator (SSG)
Frequency range
Output level
: 0.1–600 MHz
: 0.1 µV to 32 mV
(–127 to –17 dBm)
Digital multimeter Input impedance : 10 MΩ/V DC or better AC millivoltmeter Measuring range : 10 mV to 10 V
RF power meter
Measuring range
Frequency range
Impedance
SWR
: 1–75 W
: 100–800 MHz
: 50 Ω
: Better than 1.2 : 1
Oscilloscope Frequency rang
Measuring range
: DC–20 MHz
: 0.01–20 V
External speaker Input impedance
Capacity
: 4 Ω
: 10 W or more
SECTION 5 ADJUSTMENT PROCEDURES
5 - 1
5-1 PREPARATION
When adjusting IC-F1721/D,F1710,F1821/D,F1810, the optional CS-F1700 ADJ ADJUSTMENT SOFTWARE (Rev. 1.0 or later),
OPC-1122* JIG CABLE (modified OPC-1122 CLONING CABLE; see illustration page 5-3) are required.
▄SYSTEM REQUIREMENTS
• Microsoft®Windows®98/98SE/Me/2000/XP
• RS-232C serial port (D-sub 9 pin)
▄ ADJUSTMENYT SOFTWARE INSTALLATION
qQuit all applications when Windows is running.
wInsert the CD into the appropriate CD drive.
eDouble-click the “Setup.exe” contained in the ‘CS-F1700
ADJ’ folder in the CD drive.
rThe “Welcome to the InstallShield Wizard for CS-F1700
ADJ” will appear. Click [Next>].
tThe “Choose Destination Location” will appear. Then click
[Next>] to install the software to the destination folder. (e.g.
C:\Program Files\Icom\CS-F1700 ADJ)
y
After the installation is completed, the “InstallShield Wiz-
ard Complete” will appear. Then click [Finish].
uEject the CD.
iProgram group ‘CS-F1700 ADJ’ appears in the ‘Programs’
folder of the start menu, and ‘CS-F1700 ADJ’ icon ap-
pears on the desk top screen.
▄ BEFORE STARTING SOFTWARE ADJUSTMENT
Program the adjustment frequencies into the transceiver
using with the CS-F1700 before starting the software adjust-
ment. Otherwise, the transceiver can not start software ad-
justment.
CAUTION!: BACK UP the originally programmed mem-
ory data in the transceiver before program-
ming the adjustment frequencies.
When program the adjustment frequencies into
the transceiver, the transceiver’s memory data
will be overwritten and lose original memory
data at the same time.
Microsoft and Windows are registered trademarks of
Microsoft Corporation in the U.S.A. and other countries.
▄STARTING SOFTWARE ADJUSTMENT
qConnect the transceiver and PC with OPC-1122* JIG
CABLE.
wTurn the transceiver power ON.
eBoot up Windows, and click the program group ‘CS-F1700
ADJ’ in the ‘Programs’ folder of the [Start] menu, then
CS-F1700 ADJ’s window appears.
rClick ‘Connect’ on the CS-F1700 ADJ’s window, then
appears transceiver’s up-to-date condition.
tSet or modify adjustment data as desired.
• ADJUSTMENT FREQUENCY LIST
CH FREQUENCY ADJUSTMENT ITEM
1 155.000 MHz TX power
Mode
: Low1
: Wide/Middle
2 155.000 MHz TX power
Mode
: Low2
: Wide
3 155.000 MHz TX power
Mode
: High
: Wide
4 155.000 MHz TX power
Mode
: Low1
: Narrow
5 155.000 MHz
TX power
Mode
CTCSS
: Low1
: Wide
: 151.4 Hz
6 155.000 MHz TX power
Mode
: Low1
: Digital
7 174.000 MHz TX power
Mode
: Low1
: Wide/Middle
8 174.000 MHz TX power
Mode
: Low1
: Narrow
9 174.000 MHz TX power
Mode
: Low1
: Digital
10 136.000 MHz TX power
Mode
: Low1
: Wide/Middle
11 136.000 MHz TX power
Mode
: Low1
: Narrow
12 136.000 MHz TX power
Mode
: Low1
: Digital
13 136.000 MHz TX power
Mode
: Low1
: Wide

5 - 2
q: Transceiver's connection state
w: Reload adjustment data
e: Receive sensitivity measurement
r: Connected DC voltage measurement
t: PLL lock voltage measurement
y: Operating channel select
u: RF output power
i: FM modulation balance (narrow)
o: CTCSS/DTCS deviation
!0: Squelch level
!1: Reference frequency
!2: Receive sensitivity (automatic)
NOTE:
!3: PLL lock voltage for RX (automatic)
!4: PLL lock voltage for TX (automatic)
!5: PLL lock voltage for RX (manual)
!6: PLL lock voltage for TX (manual)
!7: S-meter adjustment
!8: Digital RSSI
!9: Deviation (narrow)
@0: Deviation (wide/middle)
@1: Deviation (digital)
@2: DSP frequency
@3: Base band frequency
@4: 2/5 TONE deviation
The above values for settings are example only.
Each transceiver has its own specific values for each setting.
r
t
y
u
q
io
!0
!2
!1
!3
!4
!5
!6
!7
w
e
o
!1
!8
!9
@1
@0
@2
@3
@4
• CS-F1700 ADJ'S SCREEN EXAMPLE

Modulation analyzer
(DC measurable)
Attenuator
50 dB or 60 dB
to the antenna connector
to DC cable
Standard signal generator
–127 to –17 dBm
(0.1 V to 32 mV)
CAUTION:
DO NOT transmit while
SSG is connected to
the antenna connector.
RF power meter
50 Ω/ 1–75 W
DC power supply
13.6 (13.2) V / 20 A
Frequency
counter
PC
to the MIC
connector
to an RS-232C port
*OPC-1122
(JIG CABLE)
RS-232C cable
(straight)
IC-F1721/D/F1710
IC-F1821/D/F1810
[]
AC millivoltmeter
Audio generator
+Audio generator
300 Hz to 3 kHz
AC
millivoltmeter
MICE
MIC
PTT
PTT switch
PTTE
Add a jumper wire here
• OPC-1122* (JIG CABLE)
Electrolytic
capacitor
47µF
OPC-1122
(Cloning cable)
5 - 3
• CONNECTION
• JIG CABLE

0 - 0
5-2 SOFT WARE ADJUSTMENT
Select an operation using [↑] / [↓] keys, then set specified value using [←] / [→] keys on the connected
computer keyboard
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
UNIT LOCATION UNIT ADJUST
LCD
CONTRAST
1 • Operating freq.
• Receiving
: 155.000 MHz FRON Connecta digital
multimeter or an oscillo-
scope to the check point
"CONTRAST".
–2.0 V FRONT R59
CONVENIENT:
The PLL lock voltage can be adjustment automatically.
Set the cursor to "RX LVA"/"TX LVA" and then push [ENTER] key.
CONTRAST CHCK POINT
R53: CONTRAST ADJUSTMENT
• FRONT PANEL-A
• FRONT PANEL-B

5 - 5
5-3 SOFT WARE ADJUSTMENT
Select an operation using [↑] / [↓] keys, then set specified value using [←] / [→] keys on the connected computer keyboard
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
UNIT LOCATION
PLL LOCK
VOLTAGE
[LV (RX LVA)]
[LV (TX LVA)]
1 • Operating CH.
• Preset LV(RX LVA)
• Receiving
: CH 1
: 158 [3.10 V]
PC
screen
Check the "LVIN" item on the
CS-F1700 ADJ's screen.
3.10 V
2 • Operating CH.
• Preset LV(TX LVA)
• Transmitting
: CH 10
: 46 [0.90 V]
0.90 V
CONVENIENT:
The PLL lock voltage can be adjustment automatically.
Set the cursor to "RX LVA"/"TX LVA" and then push [ENTER] key.
3 • Operating CH.
• Receiving
: CH 7 PC
screen
Check the "LVIN" item on the
CS-F1700 ADJ's screen.
3.0–4.8 V
(Verify)
4 • Transmitting 2.0–3.0 V
(Verify)
REFERENCE
FREQUENCY
[REF]
• Operating CH. : CH 7 Rear
panel
Loosely couple a frequency
counter to the antenna connec-
tor.
174.000000 MHz
• Connect an RF power meter or 50 Ω
dummy load to the antenna connector.
• Transmitting
DSP
FREQUENCY
[Dig REF]
(IC-F1721D/
F1821D only)
• Operating CH. : CH 9 MAIN
unit
Connect a frequency counter to
CP19.
12.288000 MHz
• Connect an RF power meter or 50 Ω
dummy load to the antenna connector.
• Transmitting
BASE BAND
FREQUENCY
[Dig DA]
(IC-F1721D/
F1821D only)
• Operating CH.
• Preset Dig Mode
: CH 9
: 13
Rear
panel
Loosely couple a frequency
counter to the antenna connec-
tor.
174.000000 MHz
• Connect an RF power meter or 50 Ω
dummy load to the antenna connector.
• Transmitting
CP19: DSP frequency
check point

5 - 6
SOFTWARE ADJUSTMENT (Continued)
Select an operation using [↑] / [↓] keys, then set specified value using [←] / [→] keys on the connected computer keyboard
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
UNIT LOCATION
OUTPUT
POWER
[Power (Hi)]
1 • Operating CH.
• Transmitting
: CH 3 Rear
panel
Connect an RF power meter to
the antenna connector.
25.0 W [25W]
50.0 W [50W]
[Power (L2)] 2 • Operating CH.
• Transmitting
: CH 2 10.0 W [25W]
25.0 W [50W]
[Power (L1)] 3 • Operating CH.
• Transmitting
: CH 1 2.5 W [25W]
5.0 W [50W]
MODULATION
BALANCE
[BAL]
1 • Operating CH.
• Preset [MOD N]
: CH 11
: 100
Rear
panel
Connect a modulation analyzer
with an oscilloscope to the
antenna connector through an
attenuator.
Set to square wave
form
• No audio applied to the [MIC] connector.
• Set a modulation analyzer as:
HPF
LPF
De-emphasis
Detector
: OFF
: 20 kHz
: OFF
: (P–P)/2
• Push [P0] while transmitting.
FM
DEVIATION
(NARROW)
[MOD N C]
1• Operating CH. : CH 4 Rear
panel
Connect a modulation ana-
lyzer to the antenna connector
through an attenuator.
±2.10 kHz
• Connect an audio generator to the [MIC]
connector and set as
: 1.0 kHz/40 mVrms
• Set a Modulation analyzer as:
HPF
LPF
De- emphasis
Detector
• Transmitting
: OFF
: 20 kHz
: OFF
: (P–P)/2
(NARROW)
[MOD N L]
2• Operating CH.
• Transmitting
: CH 11 ±2.10 kHz
(NARROW)
[MOD N H]
3• Operating CH.
• Transmitting
: CH 8 ±2.10 kHz
(WIDE)
[MOD W C]
4• Operating CH.
• Transmitting
: CH 1 ±4.10 kHz
(WIDE)
[MOD W L]
5• Operating CH.
• Transmitting
: CH 10 ±4.10 kHz
(WIDE)
[MOD W H]
6• Operating CH.
• Transmitting
: CH 7 ±4.10 kHz
(MIDDLE)
[MOD W C]
([EUR] only)
7• Operating CH.
• Transmitting
: CH 1 ±3.20 kHz
(MIDDLE)
[MOD W L]
([EUR] only)
8• Operating CH.
• Transmitting
: CH 10 ±3.20 kHz
(MIDDLE)
[MOD W H]
([EUR] only)
9• Operating CH.
• Transmitting
: Ch 7 ±3.20 kHz