Icom IC-F41GS Building instructions

UHF TRANSCEIVER
iC-f40gt
iC-f40gs
iC-f4 1 gt
iC-f4 1 gs
iC-f40gt ic-f40gs iC-f41gt ic-f41gs
S-13803MZ-C1-q
© 2001 Icom Inc.
1-1-32, Kamiminami, Hirano-ku, Osaka 547-0003, Japan
( including MT version )

INTRODUCTION
This service manual describes the latest service information for
the IC-F40GT/GS and IC-F41GT/GS UHF TRANSCEIVER at
the time of publication.
To upgrade quality, all electrical or mechanical parts and inter-
nal circuits are subject to change without notice or obligation.
DANGER
NEVER connect the transceiver to an AC outlet or to a DC
power supply that uses more than 10 V. This will ruin the
transceiver.
DO NOT expose the transceiver to rain, snow or any liq-
uids.
DO NOT reverse the polarities of the power supply when
connecting the tranceiver.
DO NOT apply an RF signal of more than 20 dBm (100
mW) to the antenna connector. This could damage the
transceiver’s front end.
ORDERING PARTS
Be sure to include the following four points when ordering
replacement parts:
1. 10-digit order numbers
2. Component part number and name
3. Equipment model name and unit name
4. Quantity required
<SAMPLE ORDER>
1110001810 S.IC TA7368F IC-F40GT MAIN UNIT 1 piece
8930053170 2337 4-Key IC-F41GS CHASSIS 5 pieces
Addresses are provided on the inside back cover for your
convenience.
REPAIR NOTES
1. Make sure a problem is internal before disassembling the transceiver.
2. DO NOT open the transceiver until the transceiver is disconnected from its power source.
3. DO NOT force any of the variable components. Turn them slowly and smoothly.
4. DO NOT short any circuits or electronic parts. An insulated tuning tool MUST be used for all adjustments.
5. DO NOT keep power ON for a long time when the transceiver is defective.
6. DO NOT transmit power into a signal generator or a sweep generator.
7. ALWAYS connect a 40 dB or 50 dB attenuator between the transceiver and a deviation meter or spectrum analyser when
using such test equipment.
8. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.
IC-F40GT
IC-F41GT
IC-F40GS
IC-F41GS
Communication Equipment
Himmelgeister Str. 100, D-40225 Düsseldorf, Germany
Phone : [phone] Fax : [phone]
URL : http://www.icomeurope.com
Unit 9, Sea St., Herne Bay, Kent, CT6 8LD, U.K.
Phone : [phone] Fax : [phone]
URL : http://www.icomuk.co.uk
Zac de la Plaine, Rue Brindejonc des Moulinais
BP 5804, 31505 Toulouse Cedex, France
Phone : [phone] Fax : [phone]
URL : http://www.icom-france.com
Crta. de Gracia a Manresa Km. 14,750
08190 Sant Cugat del Valles Barcelona, SPAIN
Phone : [phone] Fax : [phone]
URL : http://www.icomspain.com
<
Corporate Headquarters
>
2380 116th Avenue N.E., Bellevue, WA 98004, U.S.A.
Phone : [phone] Fax : [phone]
URL : http://www.icomamerica.com
<
Customer Service
>
Phone : [phone]
Glenwood Centre #150-6165
Highway 17 Delta, B.C., V4K 5B8, Canada
Phone : [phone] Fax : [phone]
URL : http://www.icomcanada.com
A.B.N. 88 006 092 575
290-294 Albert Street, Brunswick, Victoria, 3056, Australia
Phone : [phone] Fax : [phone]
URL : http://www.icom.net.au
146A Harris Road, East Tamaki,
Auckland, New Zealand
Phone : [phone] Fax : [phone]
URL : http://www.icom.co.nz
6F No. 68, Sec. 1 Cheng-Teh Road, Taipei, Taiwan, R.O.C.
Phone : [phone] Fax : [phone]
1-1-32, Kamiminami, Hirano-ku, Osaka 547-0003, Japan
Phone : [phone]
Fax : [phone]
URL : http://www.icom.co.jp/world/index.html
INTERINSICALLY SAFE QUALIFICATION
When servicing intrinsically safe versions of the IC-F40GT/GS
and IC-F41GT/GS the following conditions must be met.
Failing to satisfy any of these conditions will invalidate the
INTRINSICALLY SAFE certification.
1. Servicing the transcever should only be undertaken by
suitably qualified personnel in a non-hazardous area.
Never attempt to remove the case in a hazardous area.
2. ONLY the approved battery, ICOM’s BP-210FM may be
used.
3. USE ONLY safety critical components as specified in the
parts list (SECTION 6), should replacement of any item
be necessary.

L-band 400–430 MHz
M-band
ML-band 440–480 MHz
MH-band 450–490 MHz
H-band
H1-band 480–512 MHz
H2-band 480–520 MHz
TABLE OF CONTENTS
EXPLICIT DEFINITIONS
SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
SECTION 3 DISASSEMBLY INSTRUCTIONS
SECTION 4 CIRCUIT DESCRIPTION
4 - 1 RECEIVER CIRCUITS ................................................................................................... 4 - 1
4 - 2 TRANSMITTER CIRCUITS ............................................................................................ 4 - 2
4 - 3 PLL CIRCUIT................................................................................................................... 4 - 3
4 - 4 POWER SUPPLY CIRCUITS ......................................................................................... 4 - 4
4 - 5 CPU PORT ALLOCATIONS ........................................................................................... 4 - 4
SECTION 5 ADJUSTMENT PROCEDURES
5 - 1 PREPARATION................................................................................................................ 5 - 1
5 - 2 PLL ADJUSTMENT.......................................................................................................... 5 - 4
5 - 3 SOFTWARE ADJUSTMENT ........................................................................................... 5 - 5
SECTION 6 PARTS LIST
SECTION 7 MECHANICAL PARTS AND DISASSEMBLY
SECTION 8 SEMI-CONDUCTOR INFORMATION
SECTION 9 BOARD LAYOUTS
9 - 1 FRONT UNIT ................................................................................................................... 9 - 1
9 - 2 F40G MAIN UNIT ............................................................................................................ 9 - 3
9 - 3 F41G MAIN UNIT ............................................................................................................ 9 - 5
SECTION 10 BLOCK DIAGRAM
SECTION 11 VOLTAGE DIAGRAM
FREQUENCY COVERAGE CHANNEL SPACING
Wide/Narrow-type 25 kHz/12.5 kHz
Middle/Narrow-type 20 kHz/12.5 kHz

Measurement method
Frequency coverage
Type of emission
Number of conventional channels
Power supply requirement
Current drain (approx.)
Frequency error
Usable temperature range
Dimensions (proj. not included)
Weight (with BP-210)
RF output power
Modulation system
Maximum permissible deviation
Spurious emissions
Adjacent channel power
Audio frequency response
Audio hormonic distortion
FM hum and noise (typical)
Residual modulation (typical)
Limitting charact of modulator
Ext. microphone connector
Receive system
Intermediate frequencies
Sensitivity (typical)
Squelch sencitivity (at threshold) (typical)
Adjcent channel selectivity (typical)
Spurious response
Intermoduration (typical)
FM hum and noise (typical)
Hum and noise (with CCITT filter) (typical)
Audio output power (at 7.2 V DC)
External SP connector
1 - 1
All stated specifications are subject to change without notice or obligation.
USA/GEN EUR
RECEIVER TRANSMITTER GENERAL
EIA-152-C/204D or TIA-603 ETS 300 086 (GEN)
[L-band] : 400.000–430.000 MHz
[ML-band] : 440.000–480.000 MHz [GEN]/[EUR]
[MH-band] : 450.000–490.000 MHz [USA]/[GEN]
[H-band] : 480.000–512.000 MHz [USA], 480.000–520.000 MHz [GEN]
16K0F3E [25 kHz; Wide], 8K50F3E [12.5 kHz; Narrow]
Max. 256 ch (16 channels ×16 banks)
7.2 V DC (negative ground; supplied battery pack)
TX at High 2.0 A
Rx rated audio 300 mA
stand-by 95 mA (typical)
±2.5 ppm ±1.5 kHz
–30˚C to +60˚C (–22˚F to +140˚F) –25˚C to +55˚C (–13˚F to +131˚F)
54(W) ×139(H) ×38(D) mm; 21⁄8(W) ×515⁄32(H) ×11⁄2(D) inch
420 g; 14.8 oz
4 W / 2 W / 1 W (High/Low2/Low1)
Variable reactance frequency modulation
±5.0 kHz [Wide], ±2.5 kHz [Narrow]
73 dBc typical 0.25 µW
70 dB [Wide], 60 dB [Narrow]
+2 dB to –8 dB of 6 dB/octarve
range from 300 Hz to 3000 Hz [Wide]/2550 Hz [Narrow]
3% typical at 1 kHz, 40% deviation
46 dB [Wide], 40 dB [Narrow] ——
—— 45 dB [Wide], 43 dB [Narrow]
60–100% of max. deviation
9-pin multi connector/2.2 kΩ
Double-conversion superheterodyne system
1st: 47.25 MHz, 2nd: 450 kHz
0.25 µV at 12 dB SINAD –4 dBµV (emf) at 20 dB SINAD
0.25 µV –4 dBµV (emf)
73 dB [Wide], 63 dB [Narrow]
70 dB
74 dB 70 dB
46 dB [Wide], 40 dB [Narrow] ——
—— 45 dB [Wide], 43 dB [Narrow]
500 mW typical at 5% distortion with a 8 Ωload
600 mW typical at 5% distortion with a 6 Ωload
9-pin multi connector/8 Ω
SECTION 1 SPECIFICATIONS

2-1
SECTION 2 INSIDE VIEWS
• FRONT UNIT
Bottom view
• MAIN UNIT
Top view
• MAIN UNIT
Bottom view
KEY LED switch
(Q1, Q2: 2SC4116BL)
LCD module
(DS10: EDMMUD1FA0)
Internal speaker switch circuit
(Q6, Q7: CPH3403, Q8: 2SC4081,
Q9: DTC144EUA)
Expander IC
(IC1: TC74VHC373FT)
Power detector
(D2, D3: RB706F)
Antenna switching
(D25, D24: MA77)
(D1: 1SV307)
D/A converter
(IC27: M62334)
PLL IC
(IC1: SA7025)
INT/EXT microphone switch
(IC19: TC7W53FK)
Power amplifier
(Q1: 2SK2974)
Pre-drive amplifier
(Q2: 2SK2973)
YGR amplifier
(Q3: 2SC3585)
(Q5: 2SC5107)
APC amplifier
(IC4: TC75S51F)
TX, RX switch
(D5, D4: MA77)
TX/RX VCO circuit
3.58 MHz crystal
(X4: CR-563
3.579545 MHz)
PTT/MD1 switch
(IC28: TC7W53FK)
2nd IF filter (450 kHz
(FI2: SFPCA450KE4A)
(FI3: SFPCA450KG1A)
IF discreminator
(X2: CDBCB450KCAY24 450 kHz)
T5 regulator
(Q29: 2SA1362)
R5 regulator
(Q30: 2SA1362)
S5 regulator
(Q31: 2SA1362)
+5 regulator
(Q32: 2SB1132)
Crystal oscillator
for CPU clock
(X3: CR-681 12.288 MHz)
IF amplifier
(Q18: 2SC4215)
AF amplifier
(IC5: TA7368F)
RF amplifier
(Q20: 3SK293)
1st mixer
(Q19: 3SK206)
1st IF filter
(FI1: FL-296 47.250 MHz)
Splatter filter
(IC8: TA75S51F)
(IC7: TA75S01F)
2nd mixer/IF detect
/SQL amplifier
(IC3: TA31136FN-D)
D/A converter
(IC13: M62364FP)
DTMF decoder
(IC17: LC73872M)
CPU
(IC14: HD64F2238)
Expander IC
(IC23: BU4094BCFV)
EEPROM
(IC16, IC24: HN58X2464TI)
Microphone amplifier/mute
/compander
(IC9: TC35453F)
TCXO
(X1: CR-667
15.600 MHz )

3-1
SECTION 3 DISASSEMBLY INSTRUCTIONS
1 Removing the chassis panel
2 Removing the shield plate
3 Removing the MAIN unit
4 Removing the FRONT unit
qRemove 2 knobs A, and unscrew 1 nut B.
wUnscrew 1 screw C(ICOM screw), and 2 screws D(2 ×
4 mm, black) from the 9-pin connector.
eUnscrew 2 screws E(2 ×8 mm, silver) from the chassis.
rTake off the chassis in the direction of the arrow.
qUnplug the flexible cable from J1 on the FRONT unit to
separate the chassis.
wTake off the flexible cable in the direction of the arrow.
eUnscrew 10 screws F(2 ×3 mm, black) to separate the
shield plate.
qUnsolder 1 point Gat the antenna lead.
wUnscrew 2 nuts H.
eUnscrew 6 screws I(2 ×4 mm, silver), and 2 screws J
from the MAIN unit.
rTake off the MAIN unit in the direction of the arrow.
qUnplug the LCD flexible cable from J2 on the FRONT unit
to separate the front panel.
wUnscrew 6 screws K(2 ×3.5 mm, silver) from the FRONT
unit.
eUnsolder the leads of speaker.
A
B
C
D
E
Chassis
Front panel
9-pin connector
Shield plate
MAIN unit
Chassis
Flexible cable
F
F
F
F
MAIN unit
Chassis
Nut
H
J
I
G
I
Front panel
Front unit
J2
J1
LCD flexible cable
K
K

4-1 RECEIVER CIRCUITS
4-1-1 ANTENNA SWITCHING CIRCUIT
The antenna switching circuit functions as a low-pass filter
while receiving and a resonator circuit while transmitting.
This circuit does not allow transmit signals to enter the
receiver circuits.
Received signals enter the antenna connector (CHASSIS;
MP44) and pass through the low-pass filter (L1, L2, C1, C2,
C420). The filtered signals are passed through the λ⁄4type
antenna switching circuit (D25, L39, D24) and then applied
to the RF circuit.
4-1-2 RF CIRCUIT
The RF circuit amplifies signals within the range of frequen-
cy coverage and filters out-of-band signals.
The signals from the antenna switching circuit pass through
the tunable bandpass filter (D21, L37). The filtered signals
are amplified at the RF amplifier (Q20) and then passed
through the another three-stage bandpass filters (D20–D18,
L36, L34, L33) to suppress unwanted signals. The filtered
signals are applied to the 1st mixer circuit.
D18–D21 employ varactor diodes, that are controlled by the
CPU via the D/A converter (IC27), to track the bandpass fil-
ter. These varactor diodes tune the center frequency of an
RF pass band for wide bandwidth receiving and good image
response rejection.
4-1-3 1ST MIXER AND 1ST IF CIRCUITS
The 1st mixer circuit converts the received signal into fixed
frequency of the 1st IF signal with the PLL output frequency.
By changing the PLL frequency, only the desired frequency
passes through a monolithic filter at the next stage of the 1st
mixer.
The RF signals from the bandpass filter are mixed with the
1st LO signals, where come from the RX VCO circuit via the
attenuator (R108–R106), at the 1st mixer circuit (Q19) to
produce a 47.25 MHz 1st IF signal. The 1st IF signal is
passed through a monolithic filter (FI1) in order to obtain
selection capability and to pass only the desired signals. The
filtered signal is applied to the 2nd IF circuit after being
amplified at the 1st IF amplifier (Q18).
4-1-4 2ND IF AND DEMODULATOR CIRCUITS
The 2nd mixer circuit converts the 1st IF signal into a 2nd IF
signal. The double-conversion superheterodyne system
(which convert receive signals twice) improves the image
rejection ratio and obtains stable receiver gain.
The 1st IF signal from the IF amplifier (Q18) is applied to the
2nd mixer section of the FM IF IC (IC3, pin 16), and is mixed
with the 2nd LO signal to be converted into a 450 kHz 2nd
IF signal.
The FM IF IC (IC3) contains the 2nd mixer, 2nd local oscil-
lator, limiter amplifier, quadrature detector, active filter and
noise amplifier circuits. A 2nd LO signal (46.8 MHz) is pro-
duced at the PLL circuit by tripling it’s reference frequency
(15.6 MHz).
The 2nd IF signal from the 2nd mixer (IC3, pin 3) passes
through the ceramic filters (FI2, FI3) during narrow channel
spacing selection or FI2 only (bypassing FI3) during wide
channel spacing selection to remove unwanted heterodyned
frequencies. It is then amplified at the limiter amplifier sec-
tion (IC3, pin 5) and applied to the quadrature detector sec-
tion (IC3, pins 10, 11) to demodulate the 2nd IF signal into
AF signals.
The demodulated AF signals are output from pin 9 (IC3) and
applied to the AF circuit via the receiver mute circuit.
4 - 1
SECTION 4 CIRCUIT DESCRIPTION
• 2nd IF and demodulator circuits
Mixer
16
Limiter
amp.
2nd IF filter
450 kHz X1
15.6 MHz
46.8 MHz
IC3 TA31136FN
12 1st IF from the IF amplifier (Q18)
"RSSI" signal to the CPU (IC14, pin 50)
11109
87
AF signal "DSIN"
R5
X2
Squelch level
controller IC13
2
Active
filter
Noise
detector
FM
detector
13
"NOIS" signal to the CPU (IC14, pin 75)
RSSI
Noise
comp.
×3
Tripler
Q15
23
24
FI2
5
FI3
3

4 - 2
4-1-5 AF AMPLIFIER CIRCUIT
The AF amplifier circuit amplifies the demodulated AF sig-
nals to drive a speaker.
The AF signals from the FM IF IC (IC3, pin 9) are amplified
at the AF amplifier section of the compander IC (IC9, pins 5,
4) and are then applied to the high-pass filter circuit (IC10).
The high-pass filter characteristics are controlled by the
FSW signal from the I/O expander IC (IC23, pin 14). When
FSW signal is high, the cut-off frequency is shifted higher to
remove CTCSS or DTCS signals.
The filtered AF signals from the high-pass filter (IC10, pin 4)
are applied to the de-emphasis section of compander IC
(IC9, pin 3) with frequency characteristics of –6 dB/octave,
and are then passed through the low-pass filter, high-pass
filter, expander sections of compander IC (IC9). The output
signal from IC9 (pin 38) is applied to the electronic volume
controller (IC13, pin 1).
The output AF signals from the electronic volume controller
(IC13, pin 2) are applied to the AF power amplifier (IC5) to
drive the speaker.
4-1-6 RECEIVE MUTE CIRCUITS
• NOISE SQUELCH
A squelch circuit cuts out AF signals when no RF signals are
received. By detecting noise components in the AF signals,
the squelch circuit switches the AF mute switch.
Some noise components in the AF signals from the FM IF IC
(IC3, pin 9) are passed through the level controller (IC13,
pins 24, 23). The level controlled signals are applied to the
active filter section in the FM IF IC (IC3, pin 8). Noise com-
ponents about 10 kHz are amplified and output from pin 7.
The filtered signals are converted into the pulse-type signals
at the noise detector section and output from pin 13 (NOIS).
The NOIS signal from the FM IF IC is applied to the CPU
(IC14, pin 75). The CPU then analyzes the noise condition
and controls the AF mute signal via “AFMT”line (IC23, pin
13) to the AF regulator (Q23, Q24).
•CTCSS AND DTCS
The tone squelch circuit detects AF signals and opens the
squelch only when receiving a signal containing a matching
subaudible tone (CTCSS or DTCS). When tone squelch is in
use, and a signal with a mismatched or no subaudible tone
is received, the tone squelch circuit mutes the AF signals
even when noise squelch is open.
A portion of the AF signals from the FM IF IC (IC3, pin 9)
passes through the low-pass filter (IC20b/a) to remove AF
(voice) signals and is applied to the CTCSS or DTCS
decoder inside of the CPU (IC14, pin 46) via the “RXDT”line
to control the AF mute switch via the I/O expander IC (IC23).
4-2 TRANSMITTER CIRCUITS
4-2-1 MICROPHONE AMPLIFIER CIRCUIT
The microphone amplifier circuit amplifies audio signals
within +6 dB/octave pre-emphasis characteristics from the
microphone to a level needed for the modulation circuit.
The AF signals (MIC+) from the FRONT unit via J3 (pin 22)
are passed through the internal/extenal microphone switch
(IC19, pins 7, 1) and level controller (IC13, pins 9, 10) to the
microphone amplifier circuit.
The AF signals from the level controller (IC13) are applied to
the microphone amplifier section of compander IC (IC9, pin
12). The amplified signals are passed through the compres-
sor, low-pass filter and high-pass filter sections of IC9.
The filtered AF signals are amplified at the buffer amplifier
(Q47) and pre-emphasized with +6dB/octave at the pre-
emphasis circuit (C203, R166), and are then applied to the
IDC amplifier section of IC9 (pin 8).
The amplified AF signals are passed through the limitter
amplifier and low-pass filter sections of IC9 after being
passed through the AF mute switch inside of IC9.
The output signals from pin 6 are passed through the splat-
ter filter (IC8) and level controller (IC13, pins 21, 22), and
are then applied to the modulation circuit (D7).
4-2-2 MODULATION CIRCUIT
The modulation circuit modulates the VCO oscillating signal
(RF signal) using the microphone audio signals.
The AF signals from the level controller (IC13) change the
reactance of varactor diode (D7) to modulate the oscillated
signal at the TX VCO circuit (Q12, D8). The modulated VCO
signal is amplified at the buffer amplifiers (Q8, Q6) and is
then applied to the drive amplifier circuit via the T/R switch
(D4).
The CTCSS/DTCS signals from the CPU (IC14, pin 44) are
passed through the low-pass filter (IC21), level controller
(IC13, pins 12, 11) and mixer (IC7), and are then applied to
the VCO circuit via the splatter filter (IC8).
•APC circuit
Q1
Power
amp.
Q2
Driver
amp.
IC4
+
–
T5V
RF signal
from PLL to antenna
T4
TMUT
Q22
S5V
APC control circuit
Power detector
circuit (D3, D2)
D3 D2
L5
Q3
YGR
amp.
IC-F41GT/GS only

4 - 3
4-2-3 DRIVE/POWER AMPLIFIER CIRCUITS
The drive/power amplifier circuits amplify the VCO oscillat-
ing signal to an output power level.
The signal from the VCO circuit passes through the T/R
switch (D4), and is amplified at the YGR (Q5, Q3), drive
(Q2), power (Q1) amplifiers to obtain 4 W of RF power (at
7.2 V DC).
The amplified signal is passed through the APC detector,
antenna switching circuit (D1) and low-pass filter, and is
then applied to the antenna connector.
The bias current of the YGR (Q3; IC-F41GT/GS only), drive
(Q2) and power (Q1) amplifiers is controlled by the APC cir-
cuit.
4-2-4 APC CIRCUIT
The APC circuit (IC4, Q22) protects the YGR (IC-F41GT/GS
only), drive and power amplifiers from excessive current
drive, and selects output power of HIGH, LOW2 or LOW1.
The APC detector circuit detects forward signals and reflec-
tion signals at D3 and D2 respectively. The combined volt-
age is at a minimum level when the antenna impedance is
matched at 50 Ωand is increased when it is mismatched.
The detected voltage is applied to the differential amplifier
(IC4, pin 3), and the “T4”signal from the D/A converter
(IC27, pin 4), controlled by the CPU (IC14), is applied to the
other input for reference. When antenna impedance is mis-
matched, the detected voltage exceeds the power setting
voltage. Then the output voltage of the differential amplifier
(IC4, pin 4) controls the input current of the YGR amplifer
(Q3; IC-F41GT/GS only), drive amplifier (Q2) and power
amplifier (Q1) to reduce the output power.
4-3 PLL CIRCUITS
4-3-1 PLL CIRCUIT
A PLL circuit provides stable oscillation of the transmit fre-
quency and receive 1st LO frequency. The PLL output com-
pares the phase of the divided VCO frequency to the refer-
ence frequency. The PLL output frequency is controlled by
the divided ratio (N-data) of a programmable divider.
The PLL circuit contains the TX/RX VCO circuit (Q12, Q11).
The oscillated signal is amplified at the buffer amplifiers (Q8,
Q7) and then applied to the PLL IC (IC1, pin 5).
The PLL IC contains a prescaler, programmable counter,
programmable divider and phase detector, etc. The entered
signal is divided at the prescaler and programmable counter
section by the N-data ratio from the CPU. The divided signal
is detected on phase at the phase detector using the refer-
ence frequency.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
4-3-2 VCO CIRCUIT
The VCO circuit contains a separate RX VCO (Q11, D6) and
TX VCO (Q12, D7, D8). The oscillated signal is amplified at
the buffer amplifiers (Q8, Q6) and is then applied to the T/R
switch (D5, D4). Then the receive 1st LO (Rx) signal is
applied to the 1st mixer (Q19) and the transmit (Tx) signal to
the YGR amplifier circuit (Q5).
A portion of the signal from the buffer amplifier (Q8) is fed
back to the PLL IC (IC1, pin 5) via the buffer amplifier (Q7)
as the comparison signal.
•PLL circuit
Shift register
×3
Prescaler
Phase
detector
Loop
filter
Programmable
counter
Programmable
divider
X1
15.6 MHz
46.8 MHz signal
to the FM IF IC 8
Buffer
Q8
Buffer
Q6
Buffer
Q7
Tripler
1
2
3
SCK
SO
PLST
to transmitter circuit
to 1st mixer circuit
D4
D5
14 5
Q15
IC1 SA7025DK-T
Q12, D7, D8
TX VCO
Q11, D6
RX VCO

4 - 4
4-4 POWER SUPPLY CIRCUIT
VOLTAGE LINE
4-5 PORT ALLOCATIONS
4-5-1 CPU (IC14)
4-5-2 I/O EXPANDER (IC23)
LINE
HV
VCC
CPU5V
+5V
S5V
T5V
R5V
DESCRIPTION
The voltage from the attached battery pack.
The same voltage as the HV line (battery volt-
age) which is controlled by the power swtich
([VOL] control).
Common 5 V converted from the VCC line by the
reference regulator circuit (IC12). The output volt-
age is applied to the CPU (IC14), 5 V regulator
circuit (Q32, Q33), reset circuit (IC15), and etc.
Common 5 V converted from the VCC line by the
+5V regulator circuit (Q32, Q33).
Common 5 V converted from the +5V line by the
S5V regulator circuit (Q31).
5 V for transmitter circuits regulated by the T5V
regulator circuit (Q29).
5 V for receiver circuits regulated by the R5V
regulator circuit (Q30).
Outputs data signals for the PLL IC
(IC1), compamder IC (IC9), expander
IC (IC23), D/A converter (IC13), etc.
Outputs strobe signals to the D/A con-
verter (IC13).
Output clock signal to the DTMF
decoder (IC17).
Outputs single tone signal.
Outputs CTCSS/DTCS tone signal.
Single tone signal input port for decod-
ing.
CTCSS/DTCS signals input port for
decoding.
Input port for the volume control [VOL].
High : [VOL] is maximum clockwise.
Input port for the PLL lock voltage.
Input port for the RSSI detection.
Input port for the reset signal.
Outputs serial data signals to the
DTMF decoder IC (IC17).
Outputs transmit mute signal.
Low : During unlock or while muted
Outputs R5 regulator control signal.
Low: While receiving
Outputs T5 regulator control signal.
Low: While transmitting
Input port for noise signals (pulse-
type) for noise squelch operation.
I/O port for data signals from/to the
D/A converter (IC27).
I/O port for data signals from/to
EEPROMs (IC16, IC24).
Outputs beep audio signals.
Outputs clock signal to EEPROMs
(IC16, IC24).
Outputs clock signal to the D/A con-
verter (IC27).
SO
DAST
DTAC
SENC
CTDA
SDEC
RXDT
AFVI
LVIN
RSSI
RES
DTSD
TMUT
R5C
T5C
NOIS
SDA
MSO
BEEP
MSCK
SCL
35
36
39
43
44
45
46
47
49
50
59
68
70
71
73
75
81
82
87
94
95
4
5
6
7
13
15
16
17,
18,
19,
21
22–
25
26
28
29
34
RESB
RMUT
MMUT
PTOT
EXST
APST
DIN
RGS1,
RGS2,
MSKE,
FCLR
CB10–
CB13
VCOS
PLST
ULCK
SCK
Outputs reset signal for the expader IC
(IC23).
Input port for AF mute signal from the
optional units via J1 or J2.
Input port for MIC mute signal from the
optional units via J1 or J2.
Input port for the [PTT] switch
Low : While [PTT] switch is pushed.
Outputs strobe signals to the expander
IC (IC23).
Outputs strobe signals to the compan-
der IC (IC9).
Outputs serial data signals to the com-
pander IC (IC9).
Output control signal for the compan-
der IC (IC9).
Outputs reset signal for the compan-
der IC (IC9).
Input ports for rotary selector [SEL].
Outputs TX VCO/RX VCO switching
signal for the VCO switch (Q9, Q10).
High : While transmitting
Outputs strobe signals to the PLL IC
(IC1).
Input port for the PLL unlock signal.
Low : PLL is unlocked.
Outputs clock signal for the PLL IC
(IC1), compamder IC (IC9), expander
IC (IC23), D/A converter (IC13), etc.
PIN PORT DESCRIPTION
NO. NAME
PIN PORT DESCRIPTION
NO. NAME
4
6
7
11
12
13
14
BUSY
DUSE
W/N
S5C
SPCN
AFMT
FSW
Outputs BUSY detection.
Low : The channel is busy.
Outputs low-pass filter cut-off frequen-
cy control signal when DTCS is acti-
vated.
Outputs IF bandwidth control signal.
High : While IF bandwidth is narrow.
Outputs S5 regulator control signal.
Outputs internal speaker select signal.
Outputs control signal for the AF
amplifier regulator circuit.
High: While AF amp. is activated.
Outputs high-pass filter’s characteris-
tics select signal.
Pin Port Description
number name

5 - 1
5-1 PREPARATION
5-1-1 CONVENTIONAL VERSION
When you adjust the contents on pages 5-7 to 5-9, SOFTWARE ADJUSTMENT, the optional CS-F30G ADJ ADJUSTMENT SOFT-
WARE (Rev. 1.0 or later), *OPC-966 JIG CABLE (modified OPC-966 CLONING CABLE) are required.
■REQUIRED TEST EQUIPMENT
SECTION 5 ADJUSTMENT PROCEDURES
■SYSTEM REQUIREMENTS
•IBM PC compatible computer with an RS -232C serial port
(38400 bps or faster).
•Microsoft Windows 95 or Windows 98
•Intel i486DX processor or faster (Pentium 100 MHz or
faster recommended)
•At least 16 MB RAM and 10 MB of hard disk space
•640×480 pixel display (800×600 pixel display recommend-
ed)
■ADJUSTMENT SOFTWARE INSTALLATION
qBoot up Windows.
- Quit all applications when Windows is running.
wInsert the ‘CS-F30G’into the appropriate drive.
eSelect ‘Run’from the [Start] menu.
rType the setup program name using the full path name,
then push [Enter] key.
(ex. D:\CSF30GADJ\disk1\Setup.exe)
tFollow the prompts.
yProgram group ‘CS-F30G ADJ’appears in the ‘Programs’
folder of the [Start] menu.
■STARTING SOFTWARE ADJUSTMENT
qConnect IC-F40GT, F40GS, F41GT or F41GS and PC
with *OPC-966 JIG CABLE.
wTurn the transceiver power ON.
eBoot up Windows, and click the program group ‘CS-F30G
ADJ’in the ‘Programs’folder of the [Start] menu, then
CS-F30G ADJ’s window appears.
rClick ‘Connect’on the CS-F30G’s window, then appears
IC-F40GT, F40GS, F41GT or F41GS’s up-to-date condi-
tion.
tSet or modify adjustment data as desired.
•High power transmittion
When you adjust the output power (high power), the battery
type detector must be connected to GND (see illustration at
below). Otherwise the transceiver does not transmit high
power, the output power will be low.
IBM is a registered trademark of International Bussiness
Machines Corporation in the U.S.A. and other countries.
Microsoft and Windows are registered trademarks of
Microsoft Corporation in the U.S.A. and other countries.
Screen shots produced with permission from Microsoft
Corporation. All other products or brands are registered
trademarks or trademarks of their respective holders.
EQUIPMENT
DC power supply
FM deviation meter
Frequency counter
Digital multimeter
RF power meter
(terminated type)
GRADE AND RANGE
Output voltage : 7.5 V DC
Current capacity : 5 A or more
Frequency range : DC–600 MHz
Measuring range : 0 to ±10 kHz
Frequency range : 0.1–600 MHz
Frequency accuracy : ±1 ppm or better
Sensitivity : 100 mV or better
Input impedance : 10 MΩ/V DC or better
Measuring range : 1–10 W
Frequency range : 300–600 MHz
Impedance : 50 Ω
SWR : Less than 1.2 : 1
EQUIPMENT
Audio generator
Attenuator
Standard signal
generator (SSG)
DC voltmeter
Oscilloscope
AC millivoltmeter
GRADE AND RANGE
Frequency range : 300–3000 Hz
Output level : 1–500 mV
Power attenuation : 40 or 50 dB
Capacity : 10 W or more
Frequency range : 300–600 MHz
Output level : 0.1 µV–32 mV
(–127 to –17 dBm)
Input impedance : 50 kΩ/V DC or better
Frequency range : DC–20 MHz
Measuring range : 0.01–20 V
Measuring range : 10 mV–10 V
Battery type detector
+
–
DC power supply
7.5 V/5.0 A
Battery type detector
Connect to GND

5 - 2
CS-F30G ADJ Rev.1.0
File
COM 1: OPEN
Option
Connect Reload (F5) Disp para
[A / D]
VIN : 197 : C5h : 7.73 V
TEMPS : 190 : BEh : 32.23 'C
LVIN : 67 : 43h : 1.31 V
SD : 27 : 1Bh : 0.53 V
BDET : 0 : 00h : 0.00 V (Ni-Cd, Ni-MH)
Power (Hi) : 98 [ # # # # # # # # –––––––––––]
Power (L2) : 54 [ # # # # –––––––––––––––]
Power (L1) : 54 [ # # –––––––––––––––––]
Ballance : 132 [ # # # # # # # # # # –––––––––]
MOD W : 95 [ # # # # # # # ––––––––––––]
MOD N : 47 [ # # # # –––––––––––––––]
CTCS/DTCS : 113 [ # # # # # # # # # ––––––––––]
SQL : 0 [ –––––––––––––––––––]
BPF ALL : [Enter] to sweep
BPF T1 : 23 [ # # # # # # # # # # # # –––––––] [Enter] to sweep
BPF T2 : –22 [ # # # # # # # # –––––––––––] [Enter] to sweep
BPF T3 : 9 [ # # # # # # # # # # # ––––––––] [Enter] to sweep
BPF T4 : –7 [ # # # # # # # # # ––––––––––] [Enter] to sweep
TXF : [Enter] to start
S-METER : [Enter] to start
[D / A]
BPF T1 : 90 : 5Ah : 1.76 V
BPF T2 : 45 : 2Dh : 0.88 V
BPF T3 : 76 : 4Ch : 1.49 V
T4/POW : 60 : 3Ch : 1.18 V
REF : 112 : 70h : 2.20V
MOD BAL : 90 : 5Ah : 1.76 V
Dev : 45 : 2Dh : 0.88 V
CTCSS : 76 : 4Ch : 1.49 V
SQL Lev : 0 : 00h : 1.18 V
CH No. : 01 RX Freq = 450.000, TX Freq = <–RF Power: Low1 Mode: Wide
: Transceiver's connection state
: Reload adjustment data
: Receive sensitivity measurement
: Connected DC voltage
: PLL lock voltage
: Operating channel select
: RF output power
: Modulation balance
NOTE:
•Screen display exampe (for conventional version)
1
5
4
6
10
11
12
15
9
14
16
1
2
3
4
5
6
9
10
7
8
11
12
13
: FM deviation
: CTCSS/DTCS deviation
: Squelch level
: Receive sensitivity (automatically)
: Receive sensitivity (manually)
: Reference frequency
: S-meter
: Adjustment items
14
15
16
The above values for settings are example only.
Each transceiver has its own specific values for each setting.
3
2
8
7
13

5 - 3
5-1-2 MPT VERSION
When you adjust the contents on pages 5-7 to 5-9 SOFTWARE ADJUSTMENT, the optional CS-F40G ADJ ADJUSTMENT SOFT-
WARE (Rev. 1.0 or later), *OPC-966 JIG CABLE (modified OPC-966 CLONING CABLE) are required. And all adjustments in this sec-
tion must be performed at conventional mode.
■REQUIRED TEST EQUIPMENT
■SYSTEM REQUIREMENTS
•IBM PC compatible computer with an RS -232C serial port
(38400 bps or faster).
•Microsoft Windows 95 or Windows 98
•Intel i486DX processor or faster (Pentium 100 MHz or
faster recommended)
•At least 16 MB RAM and 10 MB of hard disk space
•640×480 pixel display (800×600 pixel display recommend-
ed)
■ADJUSTMENT SOFTWARE INSTALLATION
qBoot up Windows.
- Quit all applications when Windows is running.
wInsert the ‘CS-F40G’into the appropriate drive.
eSelect ‘Run’from the [Start] menu.
rType the setup program name using the full path name,
then push [Enter] key.
(ex. D:\CSF40GADJ\disk1\Setup.exe)
tFollow the prompts.
yProgram group ‘CS-F40G ADJ’appears in the ‘Programs’
folder of the [Start] menu.
■STARTING SOFTWARE ADJUSTMENT
qConnect IC-F40GT, F40GS, F41GT or F41GS and PC
with *OPC-966 JIG CABLE.
wWhen “MAP27”setting is [Disable], turn the transceiver
power ON.
When “MAP27”setting is [Enable], turn the transceiver
power ON with holding [P0] and [Up] keys.
eBoot up Windows, and click the program group ‘CS-F40G
ADJ’in the ‘Programs’folder of the [Start] menu, then
CS-F40G ADJ’s window appears.
rClick ‘Connect’on the CS-F40G’s window, then appears
IC-F40GT, F40GS, F41GT or F41GS’s up-to-date condi-
tion.
tSet or modify adjustment data as desired.
•High power transmittion
When you adjust the output power (high power), the battery
type detector must be connected to GND (see illustration at
below). Otherwise the transceiver does not transmit high
power, the output power will be low.
IBM is a registered trademark of International Bussiness
Machines Corporation in the U.S.A. and other countries.
Microsoft and Windows are registered trademarks of
Microsoft Corporation in the U.S.A. and other countries.
Screen shots produced with permission from Microsoft
Corporation. All other products or brands are registered
trademarks or trademarks of their respective holders.
EQUIPMENT
DC power supply
FM deviation meter
Frequency counter
Digital multimeter
RF power meter
(terminated type)
GRADE AND RANGE
Output voltage : 7.5 V DC
Current capacity : 5 A or more
Frequency range : DC–600 MHz
Measuring range : 0 to ±10 kHz
Frequency range : 0.1–600 MHz
Frequency accuracy : ±1 ppm or better
Sensitivity : 100 mV or better
Input impedance : 10 MΩ/V DC or better
Measuring range : 1–10 W
Frequency range : 300–600 MHz
Impedance : 50 Ω
SWR : Less than 1.2 : 1
EQUIPMENT
Audio generator
Attenuator
Standard signal
generator (SSG)
DC voltmeter
Oscilloscope
AC millivoltmeter
GRADE AND RANGE
Frequency range : 300–3000 Hz
Output level : 1–500 mV
Power attenuation : 40 or 50 dB
Capacity : 10 W or more
Frequency range : 300–600 MHz
Output level : 0.1 µV–32 mV
(–127 to –17 dBm)
Input impedance : 50 kΩ/V DC or better
Frequency range : DC–20 MHz
Measuring range : 0.01–20 V
Measuring range : 10 mV–10 V
Battery type detector
+
–
DC power supply
7.5 V/5.0 A
Battery type detector
Connect to GND

5 - 4
CS-F40G ADJ Rev.1.0
File
COM 1: OPEN
Option
Connect Reload (F5) Disp para
[A / D]
VIN : 197 : C5h : 7.73 V
TEMPS : 190 : BEh : 32.23 'C
LVIN : 67 : 43h : 1.31 V
SD : 27 : 1Bh : 0.53 V
BDET : 0 : 00h : 0.00 V (Ni-Cd, Ni-MH)
Power (Hi) : 98 [ # # # # # # # # –––––––––––]
Power (L2) : 54 [ # # # # –––––––––––––––]
Power (L1) : 54 [ # # –––––––––––––––––]
Ballance : 132 [ # # # # # # # # # # –––––––––]
MOD W : 95 [ # # # # # # # ––––––––––––]
MOD N : 47 [ # # # # –––––––––––––––]
CTCS/DTCS : 113 [ # # # # # # # # # ––––––––––]
SQL : 0 [ –––––––––––––––––––]
BPF ALL : [Enter] to sweep
BPF T1 : 23 [ # # # # # # # # # # # # –––––––] [Enter] to sweep
BPF T2 : –22 [ # # # # # # # # –––––––––––] [Enter] to sweep
BPF T3 : 9 [ # # # # # # # # # # # ––––––––] [Enter] to sweep
BPF T4 : –7 [ # # # # # # # # # ––––––––––] [Enter] to sweep
TXF : [Enter] to start
RSSI : [Enter] to start
[D / A]
BPF T1 : 90 : 5Ah : 1.76 V
BPF T2 : 45 : 2Dh : 0.88 V
BPF T3 : 76 : 4Ch : 1.49 V
T4/POW : 60 : 3Ch : 1.18 V
REF : 112 : 70h : 2.20V
MOD BAL : 90 : 5Ah : 1.76 V
Dev : 45 : 2Dh : 0.88 V
CTCSS : 76 : 4Ch : 1.49 V
SQL Lev : 0 : 00h : 1.18 V
CH No. : 01 RX Freq = 450.000, TX Freq = <–RF Power: Low1 Mode: Wide
: Transceiver's connection state
: Reload adjustment data
: Receive sensitivity measurement
: Connected DC voltage
: PLL lock voltage
: Operating channel select
: RF output power
: Modulation balance
NOTE:
•Screen display exampe (for MPT version)
1
5
4
6
10
11
12
15
9
14
16
1
2
3
4
5
6
9
10
7
8
11
12
13
: FM deviation
: CTCSS/DTCS deviation
: Squelch level
: Receive sensitivity (automatically)
: Receive sensitivity (manually)
: Reference frequency
: RSSI L0/L2
: Adjustment items
14
15
16
The above values for settings are example only.
Each transceiver has its own specific values for each setting.
3
2
8
7
13

5 - 5
+
+
–
Audio generator
300 Hz to 3 kHz
AC
millivoltmeter
SP+
SP–
MICE
MIC
PTT
PTTE
Add a jumper wire here
•*OPC-966 (JIG CABLE)
Electrolytic capacity
47 µF
OPC-966
(Cloning cable)
SINAD meter
Speaker (8 Ω)
Audio generator
•Connection (common)
to the antenna connector
RF power meter
0.1–10 W/50 Ω
Frequency
counter
Attenuator
40 dB or 50 dB
FM
deviation meter
Standard signal generator
0.1 µV to 32 mV
(–127 dBm to –17 dBm)
CAUTION:
DO NOT transmit while
SSG is connected to the
antenna connector.
to an RS-232C port
DB9 female plug
Personal
computer
RS-232C cable (straight) *OPC-966
(JIG CABLE)

5 - 6
5-2 PLL ADJUSTMENT
PLL LOCK
VOLTAGE
1
2
3
4
•Operating freq. : 400.000 MHz [L]
440.000 MHz [ML]
450.000 MHz [MH]
480.000 MHz [H]
•Receiving
•Transmitting
•Operating freq. : 430.000 MHz [L]
480.000 MHz [ML]
490.000 MHz [MH]
520.000 MHz [H]
•Receiving
•Transmitting
MAIN Connect a digital multi-
meter or an oscillo-
scope to the check
point, “CP7”.
1.3 V
1.3 V
2.5–4.0 V [L]
3.0–4.5 V other
3.0–4.5 V
MAIN C372
C373
Verify
ADJUSTMENT ADJUSTMENT CONDITIONS
UNIT LOCATION
VALUE
UNIT ADJUST
MEASUREMENT ADJUSTMENT
CP7 (LV)
PLL lock voltage
check point
C372
PLL lock voltage
adjustment for RX
C373
PLL lock voltage
adjustment for TX
•MAIN unit

5 - 7
5-3 SOFTWARE ADJUSTMENT
Select an operation using [↑] / [↓] keys, then set specified value using [←] / [→] keys on the connected computer keyboard.
1
1
2
3
1
1
2
•Operating freq. : 430.000 MHz [L]
480.000 MHz [ML]
490.000 MHz [MH]
512.000 MHz [H1]
520.000 MHz [H2]
•Output power : Low1
•Connect the RF power meter or 50 Ω
dummy load to the antenna connector.
•Transmitting
•Operating freq. : 400.000 MHz [L]
440.000 MHz [ML]
450.000 MHz [MH]
480.000 MHz [H]
•Output power : High
•Transmitting
•Output power : Low2
•Transmitting
•Output power : Low1
•Transmitting
•Operating freq. : 415.000 MHz [L]
460.000 MHz [ML]
470.000 MHz [MH]
496.000 MHz [H1]
500.000 MHz [H2]
•Output power : Low1
•Set the FM deviation meter as:
HPF : OFF
LPF : 20 kHz
De-emphasis: OFF
Detector : (P–P)/2
•Push [P0] key while transmitting
•Operating freq. : 400.000 MHz [L]
440.000 MHz [ML]
450.000 MHz [MH]
480.000 MHz [H]
•Output power : Low1
•IF bandwidth : Wide
•Set the FM deviation meter as:
HPF : OFF
LPF : 20 kHz
De-emphasis: OFF
Detector : (P–P)/2
•Connect the audio generator to the multi
connector through the JIG cable (*OPC-
966) and set as: 1.0 kHz/150 mVrms
•Transmitting
•IF bandwidth : Narrow
•Transmitting
REFERENCE
FREQUENCY
[TXF]
OUTPUT
POWER
[Power (Hi)]
[Power (L2)]
[Power (L1)]
MODULATION
BALLANCE
[Ballance]
FM
DEVIATION
[MOD W]
[MOD N]
Top
panel
Top
panel
Top
panel
Top
panel
Loosely couple a frequnecy
counter to the antenna connec-
tor.
Connect an RF power meter to
the antenna connector.
Connect an FM deviation meter
with an oscilloscope to the
antenna connector through an
attenuator.
Connect an FM deviation meter
to the antenna connector
through the attenuator.
430.0000 MHz [L]
480.0000 MHz [ML]
490.0000 MHz [MH]
512.0000 MHz [H1]
520.0000 MHz [H2]
4.0 W
2.0 W
1.0 W
±4.1 kHz
±2.1 kHz
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
UNIT LOCATION
Set to square wave
form

5 - 8
*The output level of the standard signal generator (SSG) is indicated as the SSG’s open circuit.
NOTE: After “RX SENSITIVITY”adjustment is finished, “S-METER (or RSSI L0/L2—[MPT])”adjustment
(at page 5-9) must be re-adjusted.
SOFTWARE ADJUSTMENT –continued
Select an operation using [↑] / [↓] keys, then set specified value using [←] / [→] keys on the connected computer keyboard.
0.70 kHz [Wide]
0.35 kHz [Narrow]
Minimum distortion
level
1
1
•Operating freq. : 400.000 MHz [L]
440.000 MHz [ML]
450.000 MHz [MH]
480.000 MHz [H]
•Output power : Low1
•CTCSS : 88.5 Hz
•DTCS code : 007
•Set the FM deviation meter as:
HPF : OFF
LPF : 20 kHz
De-emphasis: OFF
Detector : (P–P)/2
•No audio applied to the [MIC] input.
•Transmitting
•Operating freq. : 400.000 MHz [L]
440.000 MHz [ML]
450.000 MHz [MH]
480.000 MHz [H]
•IF bandwidth : Wide
•Connect a standard signal generator to
the antenna connector and set as:
Frequency : 400.000 MHz [L]
440.000 MHz [ML]
450.000 MHz [MH]
480.000 MHz [H]
Level : 10 µV* (–87 dBm)
Modulation : 1 kHz
Deviation : ±3.5 kHz
•Receiving
CTCSS/DTCS
DEVIATON
[CTCS/DTCS]
RX
SENSITIVITY
[BPF T1] –
[BPF T4]
Top
panel
MAIN
Connect an FM deviation meter
to the antenna connector
through the attenuator.
Connect a SINAD meter with an
8 Ωload to the multi connector
through the JIG cable (*OPC-
966).
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
UNIT LOCATION
CONVENIENT:
The BPF T1–BPF T4 can be adjusted automatically.
q-1: Set the cursol to “BPF ALL”on the adjustment program and then push [ENTER] key.
q-2: The connected PC tunes BPF T1–BPF T4 to peak levels.
or
w-1: Set the cursol to one of BPF T1, T2, T3, or T4 as desired.
w-2: Push [ENTER] key to start tuning.
w-3: Repeat w-1 and w-2 to perform additional BPF tuning.

5 - 9
SOFTWARE ADJUSTMENT –continued
Select an operation using [↑] / [↓] keys, then set specified value using [←] / [→] keys on the connected computer keyboard.
“S-METER (or RSSI L0/L2—[MPT])”adjustment must be performued after “RX SENSITIVITY”adjustment (at page 5-8) is finished.
*The output level of the standard signal generator (SSG) is indicated as the SSG’s open circuit.
Push [ENTER] key
on the connected
computer keyboard
to set “S3 level (or
L2 level—[MPT])”.
Push [ENTER] key
on the connected
computer keyboard
to set “S1 level (or
L0 level—[MPT])”.
Set “SQL level”to
close squelch.
Then set “SQL level”
at the point where
the audio signals
just appears.
1
2
1
•Operating freq. : 400.000 MHz [L]
440.000 MHz [ML]
450.000 MHz [MH]
480.000 MHz [H]
•IF bandwidth : Wide
•Connect an SSG to the antenna con-
nector and set as:
Frequency : 400.000 MHz [L]
440.000 MHz [ML]
450.000 MHz [MH]
480.000 MHz [H]
Level : 14 µV* (–84 dBm)
Modulation : 1 kHz
Deviation : ±3.5 kHz
•Receiving
•Set an SSG as :
Level : 0.45 µV* (–114 dBm)
Modulation : 1 kHz
Deviation : ±3.5 kHz
•Receiving
•Operating freq. : 415.000 MHz [L]
460.000 MHz [ML]
470.000 MHz [MH]
496.000 MHz [H1]
500.000 MHz [H2]
•IF bandwidth : Wide
•Connect an SSG to the antenna con-
nector and set as:
Frequency : 415.000 MHz [L]
460.000 MHz [ML]
470.000 MHz [MH]
496.000 MHz [H1]
500.000 MHz [H2]
Level : 0.2 µV* (–121 dBm)
Modulation : 1 kHz
Deviation : ±3.5 kHz
•Receiving
S-METER
[S-METER]
RSSI L0/L2—[MPT]
[RSSI]
SQUELCH
LEVEL
[SQL]
MAIN
Front
panel
Internal speaker
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
UNIT LOCATION

[FRONT UNIT][FRONT UNIT]
IC1 1130009860 S.IC TC74VHC373FT (EL)
IC2 1110002750 S.IC TA75S01F (TE85R)
Q1 1530002850 S.TRANSISTOR 2SC4116-BL (TE85R)
Q2 1530002850 S.TRANSISTOR 2SC4116-BL (TE85R)
Q3 1590002150 S.TRANSISTOR DTC144TE TL
Q4 1590002150 S.TRANSISTOR DTC144TE TL
Q5 1590002150 S.TRANSISTOR DTC144TE TL
Q6 1560001130 S.FET CPH3403-TL
Q7 1560001130 S.FET CPH3403-TL
Q8 1530002060 S.TRANSISTOR 2SC4081 T106 R
Q9 1590000430 S.TRANSISTOR DTC144EUA T106
D1 1790001280 S.DIODE MA111 (TX)
D2 1790001280 S.DIODE MA111 (TX)
D3 1790001200 S.DIODE MA6S121 (TX)
D4 1790001280 S.DIODE MA111 (TX)
R1 7030007300 S.RESISTOR ERJ2GEJ 332 X (3.3 kΩ)
R2 7030005030 S.RESISTOR ERJ2GEJ 152 X (1.5 kΩ)
R3 7030007250 S.RESISTOR ERJ2GEJ 220 X (22 Ω)
R4 7030009150 S.RESISTOR ERJ2GEJ 824 X (820 kΩ)
R5 7030009150 S.RESISTOR ERJ2GEJ 824 X (820 kΩ)
R6 7030006610 S.RESISTOR ERJ2GEJ 394 X (390 kΩ)
R7 7030008310 S.RESISTOR ERJ2GEJ 564 X (560 kΩ)
R8 7030008370 S.RESISTOR ERJ2GEJ 561 X (560 Ω)
R9 7030004990 S.RESISTOR ERJ2GEJ 221 X (220 Ω)
R10 7030005030 S.RESISTOR ERJ2GEJ 152 X (1.5 kΩ)
R11 7030007300 S.RESISTOR ERJ2GEJ 332 X (3.3 kΩ)
R12 7030005060 S.RESISTOR ERJ2GEJ 333 X (33 kΩ)
R13 7030007280 S.RESISTOR ERJ2GEJ 331 X (330 Ω)
R14 7030005090 S.RESISTOR ERJ2GEJ 104 X (100 kΩ)
R17 7030005090 S.RESISTOR ERJ2GEJ 104 X (100 kΩ)
R18 7410000750 S.ARRAY EXB-V4V 104JV (100 kΩ)
R20 7030005170 S.RESISTOR ERJ2GEJ 474 X (470 kΩ)
R21 7030005090 S.RESISTOR ERJ2GEJ 104 X (100 kΩ)
R22 7030005170 S.RESISTOR ERJ2GEJ 474 X (470 kΩ)
R23 7030005050 S.RESISTOR ERJ2GEJ 103 X (10 kΩ)
R24 7030005240 S.RESISTOR ERJ2GEJ 473 X (47 kΩ)
R25 7030008300 S.RESISTOR ERJ2GEJ 184 X (180 kΩ)
R26 7030007340 S.RESISTOR ERJ2GEJ 153 X (15 kΩ)
R27 7030008010 S.RESISTOR ERJ2GEJ 123 X (12 kΩ)
C1 4030016930 S.CERAMIC ECJ0EB1A104K
C2 4030016930 S.CERAMIC ECJ0EB1A104K
C3 4030016930 S.CERAMIC ECJ0EB1A104K
C4* 4550006150 S.TANTALUM ECST1CY105R
C6* 4550006150 S.TANTALUM ECST1CY105R
C7* 4550006150 S.TANTALUM ECST1CY105R
C8* 4550006150 S.TANTALUM ECST1CY105R
C9* 4550006150 S.TANTALUM ECST1CY105R
C10* 4550006150 S.TANTALUM ECST1CY105R
C11* 4550006150 S.TANTALUM ECST1CY105R
C12 4030014180 S.CERAMIC ECUE1H470JCQ
C13 4030014180 S.CERAMIC ECUE1H470JCQ
C14 4030014180 S.CERAMIC ECUE1H470JCQ
C15 4030014180 S.CERAMIC ECUE1H470JCQ
C16 4030013850 S.CERAMIC ECUE1E102KBQ
C17 4030014180 S.CERAMIC ECUE1H470JCQ
C18 4030014180 S.CERAMIC ECUE1H470JCQ
C19 4030016930 S.CERAMIC ECJ0EB1A104K
C20 4030014180 S.CERAMIC ECUE1H470JCQ
C21* 4550006150 S.TANTALUM ECST1CY105R
C22 4030016930 S.CERAMIC ECJ0EB1A104K
C23* 4550006150 S.TANTALUM ECST1CY105R
C24 4030009820 S.CERAMIC C1005 JB 1E 103K-T-A
C25 4030014180 S.CERAMIC ECUE1H470JCQ
C26 4030016930 S.CERAMIC ECJ0EB1A104K
C27 4030017230 S.CERAMIC ECUE1E271KBQ
C28 4030009820 S.CERAMIC C1005 JB 1E 103K-T-A
C29 4030013850 S.CERAMIC ECUE1E102KBQ
C30 4030016930 S.CERAMIC ECJ0EB1A104K
J1 6510022360 S.CONNECTOR 26FLZ-SM1-TB
J2 6510022200 S.CONNECTOR 40FLZ-SM1-R-TB
DS1 5010000160 S.LED LNJ310M6URA
DS2 5010000160 S.LED LNJ310M6URA
DS3 5010000160 S.LED LNJ310M6URA
DS4 5010000160 S.LED LNJ310M6URA
DS5 5040002170 S.LED LNJ210C6ARA
DS6 5010000120 S.LED LN1371G-(TR) [GT] only
DS7 5010000120 S.LED LN1371G-(TR) [GT] only
DS8 5010000120 S.LED LN1371G-(TR) [GT] only
DS9 5010000120 S.LED LN1371G-(TR) [GT] only
DS10 5030001870 LCD EDMMUD1FA0
DS11 5010000120 S.LED LN1371G-(TR) [GT] only
DS12 5010000120 S.LED LN1371G-(TR) [GT] only
DS13 5010000160 S.LED LNJ310M6URA
DS14 5010000120 S.LED LN1371G-(TR) [GS] only
DS15 5010000120 S.LED LN1371G-(TR) [GS] only
MC1 7700002310 MICROPHONE EM-140
S1 2230001060 S.SWITCH EVQ-PUL 02K
S2 2230001060 S.SWITCH EVQ-PUL 02K
S3 2230001060 S.SWITCH EVQ-PUL 02K
S4 2230001060 S.SWITCH EVQ-PUL 02K
S5 2230001060 S.SWITCH EVQ-PUL 02K
SP1* 2510001060 SPEAKER K036NA500-47
W1 7120000470 JUMPER ERDS2T0
W3 7030003860 S.JUMPER ERJ3GE JPW V
EP1 0910055267 PCB B 5489G
6 - 1
SECTION 6 PARTS LIST
REF ORDER DESCRIPTION
NO. NO.
REF ORDER DESCRIPTION
NO. NO.
[L]: L-band, [ML]: ML-band, [MH]: MH-band, [H]: H-band, [M]: ML and MH bands,
[GT]: IC-F40GT/F41GT, [GS]: IC-F40GS/F41GS, [F40G]: IC-F40GT/F40GS,
[F41G]: IC-F41GT/F41GS, [IS]: Intrinsically safe version
*=Safety critical components S.=Surface mount