Icom IC-F70DT User manual

SERVICE
MANUAL
VHF TRANSCEIVER

INTRODUCTION
This service manual describes the latest service information
for the IC-F70DT/DS and IC-F70T/S VHF TRANSCEIVER
at the time of publication.
DANGER
NEVER connect the transceiver to an AC outlet or to a DC
power supply that uses more than 7.2 V. This will ruin the
transceiver.
DO NOT reverse the polarities of the power supply when
connecting the transceiver.
DO NOT apply an RF signal of more than 20 dBm (100 mW)
to the antenna connector. This could damage the
transceiver’s front end.
ORDERING PARTS
Be sure to include the following four points when ordering
replacement parts:
1. 10-digit order numbers
2. Component part number and name
3. Equipment model name and unit name
4. Quantity required
<SAMPLE ORDER>
1130010100 S.IC LMX2352TM IC-F70DS MAIN UNIT 5 pieces
8810010120 Screw
PH B0 M2×8 SUS ZK IC-F70DS CHASSIS 10 pieces
Addresses are provided on the inside back cover for your
convenience.
REPAIR NOTES
1. Make sure a problem is internal before disassembling the transceiver.
2. DO NOT open the transceiver until the transceiver is disconnected from its power source.
3. DO NOT force any of the variable components. Turn them slowly and smoothly.
4. DO NOT short any circuits or electronic parts. An insulated tuning tool MUST be used for all adjustments.
5. DO NOT keep power ON for a long time when the transceiver is defective.
6. DO NOT transmit power into a signal generator or a sweep generator.
7. ALWAYS connect a 50 dB to 60 dB attenuator between the transceiver and a deviation meter or spectrum analyzer when
using such test equipment.
8. READ the instructions of test equipment thoroughly before connecting equipment to the transceiver.
To upgrade quality, any electrical or mechanical parts and
internal circuits are subject to change without notice or
obligation.
Icom, Icom Inc. and are registered trademarks of Icom Incorporated (Japan) in the United States, the United Kingdom,
Germany, France, Spain, Russia and/or other countries.
IC-F70DT/T
MODEL 10-KEYPAD APCO25
IC-F70DS No
Compatible
Not compatible
IC-F70S FM only
IC-F70DT Ye s
Compatible
Not compatible
IC-F70T FM only

TABLE OF CONTENTS
SECTION 1 SPECIFICATIONS
SECTION 2 INSIDE VIEWS
SECTION 3 DISASSEMBLY INSTRUCTIONS
SECTION 4 CIRCUIT DESCRIPTION
4 - 1 RECEIVE CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 1
4 - 2 TRANSMITTER CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 3
4 - 3 PLL CIRCUITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 4
4 - 4 POWER SUPPLY CIRCUITS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 4
4 - 5 DIGITAL CIRCUIT (IC-F70DT/DS only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 5
4 - 6 PORT ALLOCATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 - 5
SECTION 5 ADJUSTMENT PROCEDURES
5 - 1 PREPARATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 - 1
5 - 2 SOFTWARE ADJUSTMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 - 4
SECTION 6 PARTS LIST
SECTION 7 MECHANICAL PARTS AND DISASSEMBLY
SECTION 8 SEMICONDUCTOR INFORMATION
SECTION 9 BOARD LAYOUTS
9 - 1 FRONT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 1
9 - 2 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 3
9 - 3 FUSE BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 3
9 - 4 ANT BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 3
9 - 5 DSP UNIT (IC-F70DT/DS only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 5
9 - 6 VR BOARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 - 5
SECTION 10 BLOCK DIAGRAM
SECTION 11 VOLTAGE DIAGRAMS
11 - 1 FRONT UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 - 1
11 - 2 MAIN UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 - 2
11 - 3 DSP UNIT (IC-F70DT/DS only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 - 4

1 - 1
SECTION 1 SPECIFICATIONS
MGENERAL
• Frequency coverage : 136–174 MHz
• Type of emission : 11K0F3E (Narrow)
16K0F3E (Wide)
• Number of conventional channels : 256 channels (Max.)
• Antenna impedance : 50 Ω(Nominal)
• Operating temperature range : −22°F to 140°F
• Power supply requirement : Specified Icom's battery pack only
(Operatable voltage; 7.2 V DC negative ground)
• Current drain (At 7.2 V DC ; approx.) :RECEIVING TRANSMITTING
Stand-by Max.audio High (5 W) Low (1 W)
150 mA 450 mA 2.2 A 1.5 A
• Dimensions (Projections not included) : 2 5/16 (W)× 5 31/32 (H)× 1 1/2(D) in
• Weight (Except anntena, battery pack) : 8 13/16 oz (Approx.)
MTRANSMITTER
• Output power (At 7.2 V DC) : High; 5 W, Low; 1 W
• Modulation : Variable reactance frequency modulation
• Maximum permissible deviation : ±2.5 kHz (Narrow)
±5.0 kHz (Wide)
• Frequency error : ±2.00 ppm
• Spurious emissions : 70 dB typ.
• Adjacent channel power : 60 dB min. (Narrow)
70 dB min. (Wide)
• Audio harmonic distortion : 3% typ. at 40% deviation
• Limiting charactor of modulator : 60–100% of max. deviation
• FM hum and noise (Without CCITT filter) : 34 dB min. (40 dB typ. ; Narrow)
40 dB min. (45 dB typ. ; Wide)
• Audio frequency response : +2 dB to −8 dB of 6 dB/octave from 300 Hz to 2550 Hz (Narrow)
+2 dB to −8 dB of 6 dB/octave from 300 Hz to 3000 Hz (Wide)
• Microphone impedance : 2.2 kΩ
MRECEIVER
• Receive system : Double conversion superheterodyne system
• Intermediate frequencies : 1st IF; 46.35 MHz, 2nd IF; 450 kHz
• Sensitivity : 0.25 µV typ. at 12 dB SINAD
• Squelch sensitivity (At threshold) : 0.25 µV typ.
• Adjacent channel selectivity : 60 dB min. (70 dB typ. ; Narrow)
70 dB min. (75 dB typ. ; Wide)
• Spurious response : 70 dB min. (80 dB typ.)
• Intermodulation rejection ratio : 70 dB min. (73 dB typ.)
• Hum and Noise (Without CCITT filter) : 34 dB min. (40 dB typ. ; Narrow)
40 dB min. (45 dB typ. ; Wide)
• Audio output power : 0.5 W typ. at 10% distortion with an 8 Ωload
• Output impedance (Audio) : 8 Ω
Specifications are measured in accordance with EIA-152-C/204D, TIA-603
All stated specifications are subject to change without notice or obligation.

SECTION 2 INSIDE VIEWS
• FRONT UNIT
Speaker control
Q207: DTC144EU
Q208: 2SC4116
Q209: RSR025N03
Q210: RSR025N03
AF muting
(IC205: TC4S66F)
AF amplifier
(IC201: TA7368F)
Expander
(IC1, IC2: M62320FP)
3.0V regulator
(IC101: S-812C30AMC-C2K)
Mic switch
(IC204: TC4S66F)
Mic amplifier
(IC203: NJM12902V)
AF MUTE
Q209: RSR025N03
Q210: RSR025N03
AF mute switch
(IC205: TC4S66F)
AF amplifier
(IC201: TA7368F)
Expanders
(IC1, IC2: M62320FP)
3.0V regulator
(IC101: S-812C30AMC-C2K)
Mic switch
(IC204: TC4S66F)
Mic amplifier
(IC203: NJM12902V)
Microphone
(MC201: EM-140)
LCD
(DS2: M4-0078TAY-2)
TOP VIEW BOTTOM VIEW
• MAIN UNIT
Power amplifier
(Q13: RD07MVS1) APC amplifier
(IC5: TA75S01F)
RF amplifier
(Q18: 3SK293)
D/A converter
(IC310: M62334FP)
VCO circuit
D/A converter
(IC303: M62364FP)
DSP unit
[IC-F70DS/DT] only
Power amplifier
(Q13: RD07MVS1) ALC amplifier
(IC5: TA75S01F)
RF amplifier
(Q18: 3SK293)
D/A converter
(IC310: M62334FP)
VCO circuit
AF volume
(IC303: M62364FP)
DSP unit
[IC-F70DT/DS] only
TOP VIEW BOTTOM VIEW
CPU5V regulator
(IC311: TK11250CM)
YGR amplifier
(Q11: 2SC5110-O)
PLL IC
(IC1: LMX2352TM)
IF IC
(IC3: TA31136FN)
Audio processor
(IC301: AK2346)
Digital/Analog switch
(IC302: BU4053BCFV)
CPU
(IC307: HD64F2268TF)
Decode IC
(IC300: LC73872M)
EEPROM
(IC308: HN58X24128FPI)
Antenna switch
(D12, D22: 1SV307)
CPU5V regulator
(IC311: TK11250CM)
YGR amplifier
(Q11: 2SC5110-O)
PLL IC
(IC1: LMX2352TM)
FM IF IC
(IC3: TA31136FN)
Audio processor
(IC301: AK2346)
Digital/Analog switch
(IC302: BU4053BCFV)
CPU
(IC307: HD64F2268TF)
Mixer
(IC4: SPM5001)
DTMF DECODE
(IC300: LC73872M)
EEPROM
(IC308: HN58X24128FPI)
2 - 1

SECTION 3 DISASSEMBLY INSTRUCTIONS
• REMOVING THE CHASSIS UNIT
1Unscrew the ANT nut Aand remove the ANT washer B.
2Unscrew the screw C, and remove the rear panel Din
the direction of the arrow.
3Unscrew 4 screws Eand 2 screws F.
• REMOVING THE MAIN UNIT
1Disconnect the cable Hfrom J3.
2Remove the DSP unit from J2.
3Unsolder 14 points Iand remove the shield plate J.
4Unscrew 10 screws Kand remove the MAIN unit from the
CHASSIS.
• REMOVING THE FRONT UNIT
1Disconnect the speaker cable Lfrom J201.
2Disconnect the cable Mfrom J2.
3Unscrew 5 screws Nand remove the FRONT unit from
the front panel.
3 - 1
5Disconnect the cable Gfrom J1 and remove the CHASSIS
unit from the front panel.
C
E
E
E
A
B
D
F
*O-ring
* Be careful not to
lost the O-rings.
ANT
G
CHASSIS unit
Front panel
J1
K
K
K
K
J
J2
MAIN unit
DSP unit
J3
I
I
H
I
×2
×3
×9
L
J201
J2
FRONT unit
Front panel
M
N

4 - 1
SECTION 4 CIRCUIT DESCRIPTION
4-1 RECEIVER CIRCUITS
4-1-1 ANTENNA SWITCHING CIRCUIT
The antenna switching circuit toggles the receive line and
the transmit line. This circuit does not allow transmit signals
to enter the receiver circuits.
Received signals from the antenna connector (CHASSIS
UNIT; J1) are passed through a two-stage low-pass filter
(LPF; L22, L23, C204–C207, C209) and applied to the λ/4
type antenna switching circuit (D12, D22).
While receiving, no voltage is applied to D12 and D22.
Thus, the receive line and the ground are disconnected and
L41, L42, C199–C202 function as a two-stage LPF which
leads received signals to the RF circuits via the limiter (D20, D21).
4-1-2 RF CIRCUITS
The RF circuits amplify received signals within the range of
frequency coverage and filters off out-of-band signals.
The signals from the antenna switching circuit are passed
through the two-stage tunable bandpass filters (BPF; D18,
D19, L38, L39, C191, C193, C194, C197, C232, C233) to
suppress unwanted signals. The filtered signals are ampli-
fied at the RF amplifier (Q18).
The amplified signals are passed through another two-
stage tunable BPF (D15, D16, L49, L52–L55, C171, C173,
C174, C176) to suppress unwanted signals again. The fil-
tered signals are then applied to the 1st IF circuit.
4-1-3 1st IF CIRCUITS
The 1st mixer circuit converts the received signals into fixed
frequency of the 1st intermediate frequency (IF) signal
by mixing with the local oscillator (LO) signals which con-
trolled by the PLL circuit. The IF is shifted by changing LO
frequency to track the receive signal. The converted 1st IF
signal is filtered at the 1st IF filter, then amplified at the 1st
IF amplifier.
The signals from the two-stage tunable BPF are converted
into the 46.35 MHz 1st IF signal at the double-balanced
type 1st mixer (IC14, L30, L31, L33) by being mixed with
the 1st LO signal generated at the RX VCOs (Q4, D4, D5,
D24, D26 or Q20, D27 to D30).
The 1st IF signal from the 1st mixer is passed through the
crystal filter (FI3) to suppress unwanted signals, and then
amplified at the 1st IF amplifier (Q17). The amplified 1st IF
signal is applied to the FM IF IC (IC3, pin 16).
4-1-4 2nd IF AND FM DEMODULATOR CIRCUITS
The 1st IF signal is converted into the 2nd IF signal and
demodulated at the detector section in the FM IF IC. The
FM IF IC contains 2nd mixer, limiter amplifier, quadrature
detector, etc. in its package.
The 1st IF signal from the 1st IF amplifier (Q17) is applied
to the mixer section in FM IF IC (IC3, pin 16). The applied
1st IF signal is mixed with the 45.9 MHz 2nd LO signal gen-
erated by tripling the 15.3 MHz PLL reference frequency to
be converted into the 450 kHz 2nd IF signal.
The 2nd IF signal from the mixer section is output from pin
3 and passed through the N/W switches (D13, D14) and
ceramic filter (FI1 or FI2) to suppress the heterodyne noise.
The N/W switches (D13, D14) toggle the receive mode
wide and narrow according to “NWC” signal from the CPU
(IC307, pin 19). FI1 is used for wide, and FI2 is used for
narrow mode operation.
The filtered signal is applied to IC3 (pin 5) again, and
amplified at the limiter amplifier section and demodulated
by the quadrature detector.
Mixer
RSSI
Quadrature
detector
1st IF from the IF amplifier (Q6)
16
Noise
detector
5V
X2
1110
IC3
TA31136FN
Filter
amp.
Limiter
amp.
“DET” signal
to the D/A convertor (IC303; pin 1)
“SQL” signal
from the D/A convertor (IC303; pin 2)
• 2ND IF AND DEMODULATOR CIRCUITS
9
“NOIS” signal to the CPU (IC307: pin 37)
“RSSI” signal to the CPU (IC307: pin 50)
“DFIL” signal to the digital IF filter (FI1: DSP UNIT)
1312
Q14
X3
15.3 MHz
45.9 MHz BPF
2
3
Q303
D-IF
8735
FI2
FI1
N/W
SW
N/W
SW
D14 D13

4 - 2
The quadrature detector is a detection method which uses a
ceramic discriminator (X2).
The demodulated AF signals are output from pin 9, and
applied to the AF cricuits.
4-1-5 AF CIRCUITS
The demodulated AF signals from the FM IF IC are ampli-
fied and filtered at AF circuit. This transceiver employs the
base band IC for audio signal processing for both transmit
and receive. The base band IC is an audio processor and
composed of pre-amplifier, compressor, expander, scram-
bler, etc. in its package.
The AF signals from FM IF IC (IC3, pin 9) are applied to the
base band IC (IC301, pin 23) via the digital/analog switch
(IC302, pins 12, 14).
The applied AF signals are amplified at the amplifier section
and level adjusted at the volume control section, and then
suppressed unwanted 3 kHz and higher audio signals at
LPF section. The filtered AF signals are applied or bypassed
the TX/RX HPF, scrambler, de-emphasis, sections in
sequence, then applied to another volume controller.
The TX/RX HPF filters out 250 Hz and lower audio signals,
and the de-emphasis obtains –6 dB/oct of audio character-
istics. The expander expands the compressed audio signals
and also noise reduction function is provided.
The AF signals are level adjusted at the volume controller
and amplified at the amplifier section. The amplified AF sig-
nals are output from pin 20 and applied to the D/A coverter
(IC303, pin 16) to be adjusted its level, and then applied to
the FRONT UNIT via J3 (pin 28).
The level controlled AF signals from the MAIN UNIT are
passed through the mute switch (FRONT UNIT; IC205,
pins 1, 3) and applied to the AF power amplifier (IC201,
pin 4: FRONT UNIT) to obtain 500 mW of AF output power.
The power amplified AF signals are applied to the internal
speaker (CHASSIS UNIT; SP1).
4-1-6 SQUELCH CIRCUITS
• NOISE SQUELCH
Noise squelch circuit mutes AF output signals when no RF
signals are received. By detecting noise components in the
demodulated AF signals, the squelch circuit switches the
AF mute swithch and AF power amplifier controller ON and
OFF.
A portion of the demodulated AF signals from the FM IF IC
(IC3, pin 9) are applied to the converter (IC303, pin 1) to
be adjusted its level. The level controlled signals are output
from pin 2 and applied to the active filter (IC3, pins 7, 8;
R74, R75, R77 C137–C139). The filtered signals are applied
to the filter amplifier section to amplify the noise components
only.
The amplified noise components are converted into the
pulse-type signal at the noise detector section, and output
from pin 13 as the “NOIS” signal and applied to the CPU
(IC307, pin 37). Then the CPU outputs “AFON” signal from
pin 18 according to the “NOIS” signal level to toggle the AF
mute circuit (FRONT UNIT; IC205) and AF amplifier control-
ler (FRONT UNIT; Q202, Q203) ON/OFF.
• CTCSS AND DTCS
The tone squelch circuit detects tone signals and opens the
squelch only when receiving a signal containing a matched
sub audible tone (CTCSS or DTCS). When the tone squelch
is in use, and a signal with a mismatched or no sub audible
tone is received, the tone squelch circuit mutes the AF sig-
nals even when the noise squelch is open.
A portion of the demodulated AF signals are passed through
the LPF (IC12, pins 12, 14) to filters CTCSS/DTCS signal.
The filtered signal is applied to the CPU (IC307, pin 46)
after being amplified at the buffer amplifier (IC2, pins 1, 3).
The CPU compares the applied signal and the set CTCSS/
DTCS, then output the AF mute switch (IC205) AF amplifier
controller (Q202, Q203) control signal from pin 18.
Scrambler/
De-scrambler
TX/RX
HPF
Pre-
emphasis Limiter Splatter VR2
Expander VR4
RXA2
SMF
De-
emphasis
Com-
pressor
VR1
(HPF)
RX
LPF
VR3
(HPF)
7 MOD
18
19
20 SIGNAL
3TXIN
• BASE BAND IC BLOCK DIAGRAM
23RXIN
21SDEC
10
14MDIR
9
MTDT
MTCK
13MSCK
11MDIO
12MRDF
MSK
Modulator
MSK
Demodulator
MSK
BPF
Control
Register
TXA1
RXA1
IC301 AK2346

4 - 3
4-2 TRANSMITTER CIRCUITS
4-2-1 MICROPHONE AMPLIFIER CIRCUIT
The microphone amplifier circuit amplifies the audio signals
from microphone within +6 dB/oct pre-emphasis characteris-
tic. The microphone signals are processed in the base band
IC which contains microphone amplifier, compressor, scram-
bler, limiter, splatter filter, etc. in its package.
The audio signals from the microphone (FRONT UNIT;
MC201) are passed through the microphone mute switch
(FRONT UNIT; IC204). The switched signals are amplified at
the microphone amplifiers (FRONT UNIT; IC203, pins 1, 2,
13, 14) to obtain within +6 dB/oct pre-emphasis characteris-
tics. The amplified signals are applied to the MAIN UNIT via
J1 (pin 2).
The amplified MIC signals from the FRONT UNIT are
applied to the base band IC (IC301, pin 3). The applied
MIC signals are amplified at the amplifier section, and level
adjusted at the volume control section. The level adjusted
MIC signals are applied or bypassed the compressor sec-
tion, pre-emphasis section, TX/RX HPF, de-scrambler, lim-
iter, splatter, in sequence, then applied to another volume
controller.
The compressor compresses the MIC signals to provide
high S/N ratio for receive side, and the pre-emphasis obtains
+6 dB/oct audio characteristics. The TX/RX HPF filters out
250 Hz and lower audio signals, the limiter limits its level
and the splatter filters out 3 kHz and higher audio signals.
The filtered MIC signals are level adjusted at another vol-
ume control section and amplified at the amplifier section,
and then output from pin 7 via smoothing section (SMF).
4-2-2 MODULATION CIRCUIT
The modulation circuit modulates the VCO oscillating signal
with the audio signals from the microphone.
MIC signals from the base band IC (IC301) are passed
through the MIC switch (IC302, pins 5, 4), PM filter (C338,
R327), FM/PM switch (IC302, pins 1, 15), and then applied
to the AF mixer (IC12, pin 2) to be mixed with CTCSS/DTCS
signals.
The mixed MIC signals are applied to the D/A converter
(IC303, pin 4) to be adjusted its level. The level adjusted AF
signals are output from pin 3 and applied to the modulation
circuit (D8) to modulate the VCO oscillating signal by chang-
ing the reactance of D8 at the TX VCO (Q5, D6, D7, D25).
The CTCSS/DTCS signals are generated by the CPU (IC307)
and output from pins 89–91 (“CENC0,” “CENC1,” ”CENC2”).
The CTCSS/DTCS signals are passed through 3 regis-
ters (R374–R376) to change its wave form. The wave form
changed CTCSS/DTCS signals are then passed through the
LPF (IC12, pins 8, 10) and applied to the converter (IC303,
pin 9) to be adjusted its level, and output from pin 10.
The level adjusted CTCSS/DTCS signals are applied to
the AF mixer (IC12, pin 2) to be mixed with MIC signals.
The mixed CTCSS/DTCS signals are output from pin 1 and
applied to the D/A converter (IC303, pin 4) to be adjusted its
level again, then output from pin 3. The CTCSS/DTCS sig-
nals from the D/A converter are applied to the both of refer-
ence frequency oscillator (X1) and modulation circuit (D8) to
modulate the reference frequency signal and VCO oscillating
signal.
The modulated VCO output signal is amplified at the buffer
amplifiers (Q6, Q10) and is then applied to the YGR ampli-
fier (Q11) via the TX/RX switch (D10).
4-2-3 TRANSMIT AMPLIFIERS
The VCO output signal is amplified to transmit output power
level by the transmit amplifiers .
The buffer-amplified signal from the TX/RX switch is applied
to the YGR (Q11), the driver (Q12), and power (Q13)
amplifiers, to be amplified to the transmit output power level.
The power amplified transmit signal is passed through the
power detector (D11), antenna switch (D12), and two-stage
LPFs (L22, L23, C204–C207, C209), and then applied to the
antenna connector (CHASSIS UNIT; J1).
4-2-4 ALC CIRCUIT
The ALC (Automatic Level Control) circuit stabilizes transmit
output power and controls transmit output power High or Low.
The power detector circuit (D11) detects the transmit output
signal and converts it into DC voltage.
The detected voltage is applied to the ALC amplifier (IC5,
pin 3). The “T2” signal from the D/A converter (IC310, pin
2), controlled by the CPU (IC307), is applied to the another
input (pin 1) for reference, and the "T2" signal also controls
transmit output power (5 W or 1 W).
The output voltage from the ALC amplifier controls the bias
of the YGR (Q11), driver (Q12) and power amplifier (Q13) to
reduce the output power by comparing the detected voltage
and the reference voltage. Thus the ALC circuit maintains a
constant transmit output power.
Power
amp.
ALC
amp.
Drive
amp.
+
–
VCC
• ALC CIRCUIT
to anntena switch
(D12, D22)
T2
TMUT
from TX/RX switch
(D9, D10)
T5V
Q12
YGR
amp.
Q11
IC5
Q13
LPF LPF
D11
Power detecter

4-3 PLL CIRCUITS
4-3-1 PLL CIRCUIT (MAIN UNIT)
The PLL circuit provides stable oscillation of the transmit
frequency and receive 1st LO frequency. The PLL circuit
compares the phase of the divided VCO frequency with the
reference frequency. The PLL output frequency is controlled
by the divided ratio (N-data) of the programmable divider.
The PLL circuit contains the two RX VCOs (Q4, D4, D5,
D24, D26 for 154–174 MHz, Q20, D27–D30 for 136–
153.995 MHz) and one TX VCO (Q5, D6, D7, D25). The
oscillated signal is amplified at the buffer amplifiers (Q6, Q9)
and applied to the PLL IC (IC1, pin 6) after being passed
through the BPF (Q1, D1, D2, L2, L56, L57, L302, C12,
C15, C20, C22, C25–C28, C32).
Q1, D1 and D2 compose of a BPF switch which toggles the
filtering frequencies for TX and RX, controlled by “T5C” sig-
nal from the CPU (IC307 pin 16).
The applied signal is divided at the prescaler and program-
mable divider section by the N-data ratio from the CPU.
The divided signal is detected at the phase detector sec-
tion via divided ratio adjustment section using the reference
frequency passed through the reference divider and output
from pin 4 after being passed through the charge pump sec-
tion. The output signal is passed through the loop filter (R16,
R17, C17, C24, C29, C31) and is then applied to the VCO
circuits.
If the oscillated signal drifts, its phase changes from that of
the reference frequency, causing a lock voltage change to
compensate for the drift in the oscillated frequency.
4-3-2 VCO CIRCUITS
The VCO circuits contain separate two RX VCOs (Q4, D4,
D5, D24, D26 for 154–174 MHz, Q20, D27–D30 for 136–
153.995 MHz) and one TX VCO (Q5, D6, D7, D25). The
oscillated signal is amplified at the buffer amplifiers (Q6,
Q10) and is then applied to the TX/RX switch (D9, D10).
Then the receive 1st LO (RX) signal is applied to the 1st
mixer (IC14, L30, L31, L33), and the transmit (TX) signal is
applied to the YGR amplifier (Q11).
4 - 4
Loop
filter
PLST
SSO
SCK
4
Q20, D27–D30
RX VCO (136–153 MHz)
Q4, D4, D5, D24, D26
RX VCO (154–174 MHz)
TX VCO
Q5, D6, D7, D25
6
10
14
15
16 PLL control signals from CPU (IC307)
15.3 MHz reference signal
from reference frequency osciilator (X3)
IC1 LMX2352TM
• PLL CIRCUIT
Shift register
Prescaler
Phase
detector
Divide
ratio
adjustment
Charge
pump
Programmable
divider
Reference
divider
Buffer
Q6
Buffer
Q10
Buffer
Q9
to transmitter circuit
to 1st mixer circuit
D3
D4
LPF
LINE DESCRIPTION
VCC The voltage from the attached battery pack passed
through the power switch (Q309).
CPU5V Common 5 V for the CPU (IC307) converted from the
VCC line at the CPU5V regulator (IC311).
+5V Common 5 V line converted from the VCC line at the
+5V regulator (Q307, Q308).
T5V
5 V for the transmit circuits regulated from the +5V line
by the T5V switch (Q305).
The switch is controlled by the "T5C" signal from the
CPU (IC307, pin 16).
S5V
5 V for the power save line regulated from the +5V line
by the S5V switch (Q304).
The switch is controlled by the "S5C" signal from the
CPU (IC307, pin 27).
R5V
5 V for the receive circuits regulated from the +5V line
by the R5V switch (Q306).
The regulator is controlled by the "R5C" signal from
the CPU (IC307, pin 26).
4-4 POWER SUPPLY CIRCUITS
4-4-1 VOLTAGE LINES (MAIN UNIT)
LINE DESCRIPTION
DVDD3.3V
3.3 V for the CPU (IC12; DSP UNIT), DSP IC (IC7)
and EEPROM (IC17) regulated from the +5V line by
the +3VC regulator (IC1).
CVDD1.5V 1.5 V for the DSP IC (IC7) converted from the +5V
line at the +1.5VA regulator (IC2).
+3VD 3.3 V for the A/D converter (IC8) and LINER CODEC
IC (IC9) from the +5V line at the +3VD regulator (IC3).
4-4-2 VOLTAGE LINES (DSP UNIT)
A portion of the signal from the buffer amplifier (Q6) is fed
back to the PLL IC (IC1, pin 6) via the buffer amplifier (Q9)
and the BPF (Q1, D1, D2, L2, L56, L57, L302, C12, C15,
C20, C22, C25 to C28, C32) as the comparison signal.

4 - 5
BPF
From FM IF IC
(IC3, pin 11) To AF volume
From
MIC amplifier
(IC203; FRONT UNIT)
To FM/PM SW
(IC302, pin 5)
• DIGITAL MODE BLOCK DIAGRAM
DSP UNIT
AMP AMP
Q303
IC302
RECEIVED SIGNAL
FI1 IC5 IC8
IC7
IC9
IC9IC4
IC302
IC301
A/D LINER
CODEC
IC
LINER
CODEC
IC
BASE
BAND
IC
DIG/ANA
SW
DSP
IC
MIC SW LPF
TRANSMIT SIGNAL
4-5 DIGITAL CIRCUIT (IC-F70DT/DS only)
• WHILE RECEIVING
A portion of the 2nd IF sigal from the limiter amplifier section
in the FM IF IC (IC3) is output from pin 11 and is applied to
the 2nd IF amplifier (Q303). The amplified 2nd IF signal is
applied to the DSP UNIT via J2 (pin 11).
The 2nd IF signal from the MAIN UNIT is passed through
the ceramic BPF (DSP UNIT; FI1) to suppress heterodyne
noise, and amplified again at the digital IF amplifier (DSP
UNIT; IC5, pin 4). The amplified 2nd IF signal is applied to
the A/D converter (DSP UNIT; IC8, pin 3) to be converted
into digital IF data, then applied to the DSP IC (DSP UNIT;
IC7). The DSP IC converts the digital IF into the digital audio
signal.
The digital audio signal from the DSP IC are converted into
analog audio signals at the LINER CODEC IC (IC9) and out-
put from pin 16. The audio signals from the LINER CODEC
IC are applied to the MAIN UNIT via J1 (pin 22).
The audio signals from the DSP UNIT are applied to the
base band IC (MAIN UNIT; IC301, pin 20) after being
passed through the digital/analog switch (MAIN UNIT; IC302 ).
• WHILE TRANSMITTING
The microphone signals from the base band IC (IC301, pin 7)
are applied to the DSP UNIT via J2 (pin 4).
The microphone signals from the MAIN UNIT are applied
to the LINER CODEC IC (DSP UNIT; IC9, pin 2) to convert
into the digital audio signal.
The converted digital audio signal is processed by the DSP
IC (DSP UNIT; IC7), and applied to the LINER CODEC IC
(DSP UNIT; IC9) again. The signal from the LINER CODEC
IC (IC9, pin 15) is passed through the LPFs (DSP UNIT;
IC4, pins 3, 4, 5, 7) and applied to the MAIN UNIT via J1,
and then passed through the microphone switch (MAIN
UNIT; IC302, pins 3, 4), FM filter (R328, C335), FM/PM
switch (IC302, pins 2, 15).
4-6 PORT ALLOCATIONS
4-6-1 CPU (IC307)
Pin
number
Port
name Description
4–7 R1, R2,
R4, R8
Input ports for rotary selector (VR
UNIT; S1).
10 SSO Outputs serial data to the PLL IC (IC1,
pin 15) and D/A converter (IC303, pin 8).
11 SCK Outputs clock signal to the PLL IC (IC1
pin 14) and D/A converter (IC303, pin 7), etc.
13 PLST Outputs strobe signals to the PLL IC
(IC1, pin 16).
15 DASW
Outputs control signal to the digital
/analog switch (IC302).
Low: While analog mode is selected.
16 TXC
Outputs the T5V switch (Q305) con-
trol signal.
Low: During transmit.
17 TMUT
Outputs the ALC amplifier (IC5) con-
trol signal.
Low: During receive.
18 AFON
Outputs control signal for AF mute
circuit (FRONT UNIT; IC205) and AF
power amplifier (FRONT UNIT; IC201).
High: AF amplifier (IC201) is activated.
19 NWC
Outputs wide/narrow switch (D13,
D14) control signal.
High: When narrow mode is selected.
Pin
number
Port
name Description
20 DDSD Input port for serial data from the
DTMF decoder IC (IC300, pin 9).
21 DDAC Outputs clock signals to the DTMF
decoder IC (IC300, pin 10).
26 R5C Outputs R5V switch (Q306) control signal.
High:While receiving.
27 S5C
Outputs S5V switch (Q304) control
signal.
High:In power save mode..
29 PTTO Input port for optional unit.
Low: Switch ON.
30 EM
Input port for the emegency switch
(FRONT UNIT; S117).
Low: While emegency switch is
pushed.
32 RMUT
Input port for the AF mute signal from
the optional unit via J1 or J2.
Low: While RX audio is muted.
33 MMUT
Input port for the microphone mute
signal from the optional unit via J1 or
J2.
Low: While microphone audio is
muted.
34–36 OPT1–
OPT3
I/O ports for the connected optional
unit to J1.

4 - 6
Pin
number
Port
name Description
37 NOIS Input port for the noise signal from
the FM IF IC (IC3, pin 13).
38 PWRSW
Input port for the [VOL] control (VR
UNIT; R1).
Low: While power is ON.
39 DDST
Input port for the decodedDTMF sig-
nals from the DTMF decoder IC (IC300,
pin 11).
40 CIRQ
Inputs offering signal from the optional
unit and DSP unit.
Low: Offering signal is output.
41 PWRO
Outputs control signal for the power
switch circuit (Q309, Q310).
High: Power ON.
43 SENC Outputs single tone encode signal.
44 BEEP Outputs beep audio signals.
45 SDEC
Input port for single tone decode sig-
nal from the base band IC (IC301,
pin 1).
46 CDEC Input port for CTCSS/DTCS signal
from the LPF (IC12, pin 7).
47 ULCK Input port for the PLL unlock signal.
Low: The PLL circuit is unlocked.
48 BATV
Input port for the connected battery pack
for the low battery voltage detection.
Low: The battery voltage is low.
49 LVIN Input port for the PLL lock voltage.
50 RSSI Input port for the "RSSI" signal from
the FM IF IC (IC3, pin 12).
51 TEMP/
OPTV
• Input port for the transceiver’s internal
temperature detecting signal.
High: Internal temperature is high.
• Input port for the optional unit detecting
signal.
High: While connecting optional unit
to the multiconnector.
55 SIDE1 Input port for [UP] switch (MAIN UNIT; S1).
Low: While [UP] switch is pushed.
68 DAST Outputs strobe signals to the D/A
converter (IC303, pin 6).
69 DSDA I/O port for data signal to the D/A con-
verter (IC310, pin 6).
72 SPCON Outputs "SPCON" signal.
Low: Audio output.
78 MTCK
Input port for transmitting MSK clock
signal from the base band IC (IC301,
pin 9).
79 KR
Input port for key matrix.
Low: While any of key on the 10-keypad
(including [P0]–[P3]) is pushed.
80 FSDA I/O port for the serial data signal for
the expander (FRONT UNIT; IC2).
81 FSCL Outputs clock signal to the expander
(FRONT UNIT; IC2).
88 SIDE2
Input port for [DOWN] switch (MAIN UNIT;
S2).
Low: While [DOWN] switch is pushed.
Pin
number
Port
name Description
89–91 CENC0–
CENC2 Output the CTCSS/DTCS signals.
92 SIDE3
Input port for [MONITOR] switch (MAIN
UNIT; S4).
Low: While [MONITOR] switch is pushed.
93 MTDT Outputs the MSK data to the base
band IC (IC301, pin 10).
94 MDIR Outputs serial data control signal to
the base band IC (IC301, pin 14 ).
95 MDIO
I/O port for the serial data signals
from/to the base band IC (IC301,
pin 11).
96 MSCK Outputs clock signal for the base
band IC (IC301, pin 13).
97 PMFM
Outputs the the FM/PM switch (IC302,
pin 11) control signal.
High:While PM is selected.
98 ESDA I/O port for data signals from/to the
EEPROM (IC308, pin 5).
99 ESCL Outputs clock signal to the EEPROM
(IC308, pin 6).
100 CODE8 Output port for "CODE8" signal.
4-6-2 D/A CONVERTER (MAIN UNIT; IC303)
Pin
number
Port
name Description
2 SQL Outputs AF signals to the squelch cir-
cuit (IC3, pin 8).
3 MOD Outputs modulation signals to the
modulation circuit (D8).
10 TENC Outputs CTCSS/DTCS signals.
11 BAL Outputs deviation balance control signal.
14 BEPV
Outputs beep audio signals to the
speaker via the AF amplifier (FRONT
UNIT; IC201).
15 SIGNAL Outputs AF signals to the speaker via
the AF amplifiers (FRONT UNIT; IC201).
22 TONE Outputs single tone signal.
23 REF Outputs reference oscillator control signal.
4-6-3 D/A CONVERTER (MAIN UNIT; IC310)
Pin
number
Port
name Description
1T1
Outputs the bandpass filters (D18,
D19) tuning signal.
2T2
• While receiving:
Outputs the bandpass filters (D15, D16)
tuning signal.
• While transmitting:
Outputs the TX power control signal
which selects TX output power of HIGH
or LOW. The output signal is applied to
the ALC amplifier (IC5, pin 1).
3 TXLVA Outputs TX VCO lock voltage.
4 RXLVA Outputs RX VCO lock voltage.
4-6-1 CPU (continued)

▄ REQUIRED TEST EQUIPMENT
EQUIPMENT GRADE AND RANGE EQUIPMENT GRADE AND RANGE
DC power supply Output voltage
Current capacity
: 7.2 V DC
: 3 A or more Audio generator Frequency range
Measuring range
: 300–3000 Hz
: 1–500 mV
FM deviation meter Frequency range
Measuring range
: DC–300 MHz
: 0 to ±10 kHz Attenuator Power attenuation
Capacity
: 50 or 60 dB
: 10 W
Frequency counter
Frequency range
Frequency accuracy
Sensitivity
: 0.1–300 MHz
: ±1 ppm or better
: 100 mV or better
Standard signal
generator (SSG)
Frequency range
Output level
: 0.1–300 MHz
: 0.1 µV to 32 mV
(–127 to –17 dBm)
Digital multimeter Input impedance : 10 MΩ/V DC or more AC millivoltmeter Measuring range : 10 mV to 10 V
RF power meter
Measuring range
Frequency range
Impedance
SWR
: 1–10 W
: 100–300 MHz
: 50 Ω
: Better than 1.2 : 1
Oscilloscope Frequency rang
Measuring range
: DC–20 MHz
: 0.01–20 V
External speaker Input impedance
Capacity
: 8 Ω
: 1 W or more
SECTION 5 ADJUSTMENT PROCEDURES
5 - 1
5-1 PREPARATION
When adjusting IC-F70DS/DT/S/D, the optional CS-F70/F1700 ADJ ADJUSTMENT SOFTWARE (Rev. 1.1 or later), OPC-966 JIG
CABLE (modified OPC-966 CLONING CABLE; see illustration page 5-2) are required.
▄SYSTEM REQUIREMENTS
• Microsoft®Windows®98/98SE/Me/2000/XP
• RS-232C serial port (D-sub 9 pin)
▄ ADJUSTMENYT SOFTWARE INSTALLATION
qQuit all applications when Windows is running.
wInsert the CD into the appropriate CD drive.
eDouble-click the “Setup.exe” contained in the ‘CS-F70/
F1700 ADJ’ folder in the CD drive.
rThe “Welcome to the InstallShield Wizard for CS-F70/
F1700 ADJ” will appear. Click [Next>].
tThe “Choose Destination Location” will appear. Then click
[Next>] to install the software to the destination folder. (e.g.
C:\Program Files\Icom\CS-F70/F1700 ADJ)
y
After the installation is completed, the “InstallShield Wiz-
ard Complete” will appear. Then click [Finish].
uEject the CD.
iProgram group ‘CS-F70/F1700 ADJ’ appears in the ‘Pro-
grams’ folder of the start menu, and ‘CS-F70/F1700 ADJ’
icon appears on the desk top screen.
▄ BEFORE STARTING SOFTWARE ADJUSTMENT
Clone the adjustment frequencies into the transceiver, and-
set the configuration using with the CS-F70/F1700 CLONING
SOFTWARE before starting the software adjustment. Other-
wise, the transceiver can not start software adjustment.
CAUTION!: BACK UP the originally programmed mem-
ory data in the transceiver before program-
ming the adjustment frequencies.
When program the adjustment frequencies into
the transceiver, the transceiver’s memory data
will be overwritten and lose original memory
data at the same time.
Microsoft and Windows are registered trademarks of
Microsoft Corporation in the U.S.A. and other countries.
▄STARTING SOFTWARE ADJUSTMENT
qConnect the transceiver and PC with OPC-966 JIG CABLE.
wTurn the transceiver power ON.
eBoot up Windows, and click the program group ‘CS-F70/
F1700 ADJ’ in the ‘Programs’ folder of the [Start] menu,
then CS-F70/F1700 ADJ’s window appears.
rClick ‘Connect’ on the CS-F70/F1700 ADJ’s window, then
appears transceiver’s up-to-date condition.
tSet or modify adjustment data as desired.
• ADJUSTMENT FREQUENCY LIST
CH FREQUENCY ADJUSTMENT ITEM
1 153.900 MHz TX power
Mode : Low1 : Wide
2 174.000 MHz TX power
Mode : Low1 : Narrow
3 155.000 MHz TX power
Mode : High : Wide
4 155.000 MHz TX power
Mode : Low2 : Wide
5 155.000 MHz TX power
Mode : Low1 : Wide
6 136.000 MHz TX power
Mode : Low1 : Wide
7 174.000 MHz TX power
Mode : Low1 : Wide
8 136.000 MHz TX power
Mode : Low1 : Narrow
9* 155.000 MHz
TX power
Mode
Preamble Length†
: Low1
: Digital
: 270
10* 136.000 MHz
TX power
Mode
Preamble Length†
: Low1
: Digital
: 270
11* 174.000 MHz TX power
Mode : Low1 : Digital
12 155.000 MHz
TX power
Mode
CTCSS
: Low1
: Wide
: 151.4 Hz
13 155.000 MHz TX power
Mode : Low1 : Narrow
*; IC-F70DT/DS only
†; [USA-02] only

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5 - 2
• CONNECTION
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• JIG cable

5 - 3
• PC SCREEN EXAMPLE
r
t
y
e
u
q
w
i
!0
!2
@5
@6 @7
@8 @9
!5
!6
!7
o
!8
!9
@1
@0
@2
@3
@4
!1
!3
!4
q: Reload adjustment data
w: Transceiver's connection state
e: Connected DC voltage measurement
r: PLL lock voltage measurement
t: RF output power
y: FM modulation balance
u: FM modulation preset
i: CTCSS/DTCS deviation
o: Squelch level
!0: Reference frequency
!1: Receive sensitivity for center (automatic)
!2: Receive sensitivity for center (manual)
!3: Receive sensitivity for low edge (automatic)
!4: Receive sensitivity for low edge (manual)
!5: Receive sensitivity for high edge (automatic)
!6: Receive sensitivity for high edge (manual)
!7: PLL lock voltage adjust for RX (manual)
!8: PLL lock voltage adjust for TX (manual)
!9: PLL lock voltage preset for RX (automatic)
@0: PLL lock voltage preset for TX (automatic)
@1: S-meter
@2: S-meter (digital)
@3: Deviation (narrow)
@4: Deviation (wide)
@5: Deviation (digital)
@6: DSP reference frequency
@7: Base band center voltage
@8: Digital mode
@9: 2/5 TONE, DTMF deviation
NOTE: The above values for settings are example only.
Each transceiver has its own specific values for each setting.

5 - 4
5-2 SOFT WARE ADJUSTMENT
Select an operation using [↑] / [↓] keys, then set specified value using [←] / [→] keys on the connected computer keyboard
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
UNIT OPERATION
PLL LOCK
VOLTAGE
[RX LVA1]
1 • Operating CH.
• Preset [LV (RX1)]
• Receiving
: CH 2
: 169 [3.30 V]
PC
screen
Click [Reload (F5)] button, then
check the "LVIN" item on the
CS-F70/F1700 ADJ's screen.
3.3 V
[RX LVA2] 2 • Operating CH.
• Preset [LV (RX2)]
• Receiving
: CH 1
: 179 [3.50 V] 3.5 V
[TX LVA] 3 • Operating CH.
• Preset [LV (TX)]
• Transmitting
: CH 2
: 179 [3.50 V] 3.5 V
CONVENIENT:
The PLL lock voltage can be adjusted automatically.
Put the cursor on each items "RX LVA1"/"RX LVA2"/"TX LVA" and then push [ENTER] key of the connected
PC's keyboard.
PLL LOCK
VOLTAGE
1 • Operating CH.
• Receiving
: CH 2 PC
screen
Click [Reload (F5)] button, then
check the "LVIN" item on the
CS-F70/F1700 ADJ's screen.
3.2–3.4 V
(Verify)
2 • Operating CH.
• Receiving
: CH 1 3.4–3.6 V
(Verify)
3 • Operating CH.
• Transmitting
: CH 2 3.4–3.6 V
(Verify)
REFERENCE
FREQUENCY
[REF]
• Operating CH. : CH 2 Top
panel
Loosely couple a frequency
counter to the antenna connec-
tor.
174.000000 MHz
±100 Hz
• Connect an RF power meter or 50 Ω
dummy load to the antenna connector.
• Transmitting
DSP
REFERENCE
FREQUENCY*
[Dig REF]
• Operating CH. : CH 9 DSP
unit
Connect a frequency counter
to the pin 4 of IC13 on the DSP
unit through a 1000 pF capacitor.
(see the illust below)
12.288000 MHz
• Receiving
BASE BAND
CENTER
VOLTAGE*
[Dig DA]
• Operating CH.
• Receiving
: CH 9 PC
screen
Set the "Dig DA" item to 70.
*; IC-F70DT/DS only
DSP REFERENCE FREQUENCY
CHECK POINT (IC-13, pin 4)
DSP UNIT
MAIN UNIT

5 - 5
SOFTWARE ADJUSTMENT (Continued)
Select an operation using [↑] / [↓] keys, then set specified value using [←] / [→] keys on the connected computer keyboard
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
UNIT OPERATION
OUTPUT
POWER
[Power (Hi)]
1 • Operating CH.
• Transmitting
: CH 3 Top
panel
Connect an RF power meter to
the antenna connector.
5.0 W
[Power (L2)] 2 • Operating CH.
• Transmitting
: CH 4 2.0 W
[Power (L1)] 3 • Operating CH.
• Transmitting
: CH 5 1.0 W
MODULATION
BALANCE
[BAL]
1 • Operating CH.
• Preset [MOD N]
: CH 5
: 100
Top
panel
Connect an FM deviation meter
with an oscilloscope to the
antenna connector through an
attenuator.
Set to square wave
form
• No audio applied to the JIG cable.
• Set an FM deviation meter as;
HPF
LPF
De-emphasis
Detector
: OFF
: 20 kHz
: OFF
: (P–P)/2
• Push [P0] while transmitting.
FM
DEVIATION
(NARROW)
[MOD N C]
1• Operating CH. : CH 13 Top
panel
Connect an FM deviation meter to
the antenna connector through
an attenuator.
±2.00 to ±2.10 kHz
• Connect an audio generator to the JIG
cable and set as;
: 1.0 kHz/150 mV rms
• Set an FM deviation meter as;
HPF
LPF
De- emphasis
Detector
• Transmitting
: OFF
: 20 kHz
: OFF
: (P–P)/2
(NARROW)
[MOD N L]
2• Operating CH.
• Transmitting
: CH 8
(NARROW)
[MOD N H]
3• Operating CH.
• Transmitting
: CH 2
(WIDE)
[MOD W C]
4• Operating CH.
• Transmitting
: CH 5 ±3.95 to ±4.05 kHz
(WIDE)
[MOD W L]
5• Operating CH.
• Transmitting
: CH 6
(WIDE)
[MOD W H]
6• Operating CH.
• Transmitting
: CH 7

5 - 6
SOFTWARE ADJUSTMENT (Continued)
Select an operation using [↑] / [↓] keys, then set specified value using [←] / [→] keys on the connected computer keyboard
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
UNIT OPERATION
DIGITAL
DEVIATION*
[MOD Dig C]
1• Preset [Dig Mode] : 7 Top
panel
Connect an FM deviation meter to
the antenna connector through
an attenuator.
±2.83 to ±2.87 kHz
2• Operating CH. : CH 9
• Set an FM deviation meter as;
HPF
LPF
De- emphasis
Detector
• Transmitting
: OFF
: 20 kHz
: OFF
: (P–P)/2
[MOD Dig L] 3 • Operating CH.
• Transmitting
: CH 10
[MOD Dig H] 4 • Operating CH.
• Transmitting
: CH 11
DIGITAL
DEVIATION*
[MOD Dig C]
1• Preset [Dig Mode] : 6 Top
panel
Connect an FM deviation meter to
the antenna connector through
an attenuator.
±0.91 to ±1.01 kHz
(Verify)
2• Operating CH.
• Transmitting
CH 9
[MOD Dig L] 3 • Operating CH.
• Transmitting
CH 10
[MOD Dig H] 4 • Operating CH.
• Transmitting
CH 11
CTCSS/DTCS
DEVIATION
[CTCSS/DTCS]
1• Operating CH. : CH 12 Top
panel
Connect an FM deviation meter to
the antenna connector through
an attenuator.
±0.68 to ±0.72 kHz
• No audio applied to the JIG cable.
• Set an FM deviation meter as;
HPF
LPF
De- emphasis
Detector
• Transmitting
: OFF
: 20 kHz
: OFF
: (P–P)/2
2/5 TONE
/DTMF
DEVIATION
[S.Tone]
1• Operating CH. : CH 5 Top
panel
Connect an FM deviation meter to
the antenna connector through
an attenuator.
±1.50 kHz
• No audio applied to the JIG cable.
• Set an FM deviation meter as;
HPF
LPF
De- emphasis
Detector
: OFF
: 20 kHz
: OFF
: (P–P)/2
• Push [P3] while transmitting.
*; [IC-F70DT/DS] only

5 - 7
SOFTWARE ADJUSTMENT (continued)
• Select an operation using [↑] / [↓]keys, then set specified value using [←] / [→] keys on the connected computer keyboard
ADJUSTMENT ADJUSTMENT CONDITION MEASUREMENT VALUE
UNIT LOCATION
RX
SENSITIVITY
[BPF C]
NOTE:
Need to adjust "S-METER ADJUSTMENT" after "RX SENSITIVITY ADJUSTMENT" is adjusted.
Otherwise, "S-METER ADJUSTMENT" will not be adjusted properly.
1• Operating CH : CH 5 PC
screen
Connect the SINAD meter with
an 8 Ωload to the JIG cable.
Minimum distortion
level
• Connect the SSG to the antenna connec-
tor and set as;
Frequency
Level
Modulation
Deviation
• Receiving
: 155.000 MHz
: +20 dBµ†(–87 dBm)
: 1 kHz
: ±3.5 kHz
[BPF L] 2• Operating CH
Frequency
• Receiving
: CH 6
: 136.000 MHz
[BPF H] 3• Operating CH
Frequency
• Receiving
: CH 7
: 174.000 MHz
CONVENIENT:
The BPF C/L/H can be adjustment automatically.
q-1: Put the cursor on "BPF C/L/H ALL" and then push [ENTER] key.
q-2: The connected PC tunes BPF C/L/H to peak levels.
or
w-1: Put the cursor on the one of "BPF C/L/H" as desired.
w-2: Push [ENTER] key to start tuning.
w-3: Repeat w-1 and w-2 to perform additional BPF tuning.
Digital RSSI*
[Dig RSSI]
1• Operating CH. : CH 9 Put the cursor on "Dig RSSI" and push the [ENTER] key to
set the Digial RSSI level.
• Connect the SSG to the antenna connec-
tor and set as;
Frequency
Level
Modulation
• Receiving
: 155.000 MHz
: –20 dBµ† (–127 dBm)
: No modulation
S-METER
[RSSI]
1• Operating CH. : CH 5 Push the [ENTER] key on the connected computer's keyboard
to set "S3" level.
• Connect the SSG to the antenna connec-
tor and set as;
Frequency
Level
Modulation
Deviation
• Receiving
: 155.000 MHz
: +23 dBµ† (–84 dBm)
: 1 kHz
: ±3.5 kHz
2• Set the SSG as;
Level
• Receiving
: –7dBµ† (–114 dBm)
Push the [ENTER] key on the connected computer's keyboard
to set "S1" level.
SQUELCH
LEVEL
[SQL]
1 • Operating CH. : CH 5 Top
panel
Connect speaker to the JIG
cable.
Set the SQL level to
close squelch.
Then set SQL level
at the point where
the audio signals
just appears.
• Connect the SSG to the antenna connec-
tor and set as;
Frequency
Level
Modulation
Deviation
• Receiving
: 155.000 MHz
: –14dBµ† (–121 dBm)
: 1 kHz
: ±3.5 kHz
*; [IC-F70DT/DS] only
†; The output level of the standard signal generator (SSG) is indicated as the SSG's open circuit.

6 - 1
SECTION 6 PARTS LIST
M.=Mounted side (T: Mounted on the Top side, B: Mounted on the Bottom side)
[MAIN UNIT]
REF ORDER DESCRIPTION M. H/V
NO. NO.
LOCATION
[MAIN UNIT]
IC1 1130010100 S.IC LMX2352TMX B 8.3/75.8
IC2 1110005340 S.IC NJM12902V-TE1 T 8/75.7
IC3 1110003490 S.IC TA31136FN B 14.6/57.6
IC4 1190002050 S.IC SPM5001 B 31.4/78.3
IC5 1110002750 S.IC TA75S01F (TE85R) T 24.8/101.4
IC6 1130004200 S.IC TC4S66F (TE85R) B 17.7/85.4
IC12 1110005340 S.IC NJM12902V-TE1 T 31.9/56.5
IC300 1130009700 S.IC LC73872M-TRM B 34.9/29.5
IC301 1110006220 S.IC AK2346-E2 B 15/39.8
IC302 1130008230 S.IC BU4053BCFV-E2 B 13.9/29.3
IC303 1190001350 S.IC M62364FP 600D T 20.2/71.7
IC304 1110006260 S.IC BD5242G-TR B 4.7/8.6
IC305 1130008230 S.IC BU4053BCFV-E2 B 33.4/66.4
IC307 1140010190 S.IC HD64F2268TF20 B 20.2/15
IC308 1140009240 S.IC HN58X24128FPI B 38.2/17.7
IC310 1190001340 S.IC M62334FP 600C T 32.5/84.4
IC311 1180002270 S.REG TK11250CMCL B 8.6/119.6
IC312 1190001860 S.IC EW-460-FT B 30.1/43.8
IC313 1130006220 S.IC TC4W53FU (TE12L) T 8.5/38.2
Q1 1590001940 S.TR DTC144EE TL B 8.4/88.3
Q2 1560000540 S.FET 2SK880-Y (TE85R) T 24.2/80.5
Q3 1530002850 S.TR 2SC4116-BL (TE85R) B 9.1/96.8
Q4 1530002920 S.TR 2SC4226-T1 R25 T 19.3/95.8
Q5 1530002920 S.TR 2SC4226-T1 R25 T 25.2/93.8
Q6 1530003310 S.TR 2SC5107-O (TE85R) T 22.3/97
Q7 1590001400 S.TR XP1214 (TX) B 26.6/96
Q8 1590001940 S.TR DTC144EE TL B 18.4/93
Q9 1530003310 S.TR 2SC5107-O (TE85R) B 14.8/94.8
Q10 1530003310 S.TR 2SC5107-O (TE85R) B 24/99.4
Q11 1530003420 S.TR 2SC5110-O (TE85R) B 14/100.9
Q12 1560001240 S.FET RD01MUS1 T 14.9/109.8
Q13 1560001230 S.FET RD07MVS1 T 21/109.4
Q14 1530002380 S.TR 2SC4215-Y (TE85R) B 8.9/64.9
Q15 1590002430 S.TR DTA144EE TL T 21.3/64.7
Q16 1590001940 S.TR DTC144EE TL T 19.3/64.7
Q17 1560000670 S.FET 2SK1771 (TE85R) B 15.3/64.3
Q18 1580000730 S.FET 3SK293 (TE85L) T 34.3/96.3
Q19 1560000840 S.FET 2SK1829 (TE85R) T 33/93.5
Q20 1530002920 S.TR 2SC4226-T1 R25 T 19.3/92.1
Q21 1590001400 S.TR XP1214 (TX) B 18.6/95.3
Q300 1590001940 S.TR DTC144EE TL T 36.7/49.7
Q302 1590001940 S.TR DTC144EE TL B 7.2/5.9
Q303 1530002380 S.TR 2SC4215-Y (TE85R) T 19.4/49
Q304 1510000920 S.TR 2SA1577 T106 Q B 3.9/106
Q305 1510000920 S.TR 2SA1577 T106 Q B 7.3/101.7
Q306 1510000920 S.TR 2SA1577 T106 Q B 5.6/84.6
Q307 1590001190 S.TR XP6501-(TX) AB B 3.4/110.6
Q308 1520000450 S.TR 2SB1132 T100 Q B 4.1/119.1
Q309 1590003320 S.FET TPC6103 (TE85L) B 12.3/120.1
Q310 1590001940 S.TR DTC144EE TL B 8.9/9.6
Q311 1590002430 S.TR DTA144EE TL B 33.3/45.1
D1 1790001260 S.DIO MA2S077-(TX) B 12.9/87.1
D2 1790001260 S.DIO MA2S077-(TX) B 12.9/88.9
D3 1790001250 S.DIO MA2S111-(TX) B 10/93.3
D4 1750000770 S.VCP HVC376BTRF T 10.9/89.3
D5 1750000770 S.VCP HVC376BTRF T 12.1/89.3
D6 1750000770 S.VCP HVC376BTRF T 27.2/85.4
D7 1750000770 S.VCP HVC376BTRF T 25/85.3
D8 1720000470 S.VCP 1SV239 (TPH3) B 26.3/90.2
D9 1790001260 S.DIO MA2S077-(TX) B 24.9/101.4
D10 1790001260 S.DIO MA2S077-(TX) B 19.6/101.3
D11 1790001670 S.DIO RB706F-40T106 B 30.5/104.3
D12 1750000580 S.DIO 1SV307 (TPH3) B 35.3/108.7
D13 1750001070 S.DIO DAN235ETL B 20/60
D14 1750001070 S.DIO DAN235ETL B 21.6/55.4
D15 1750000710 S.VCP HVC350BTRF T 40.1/89.5
D16 1750000710 S.VCP HVC350BTRF T 39.4/92.1
D17 1790001250 S.DIO MA2S111-(TX) T 35.1/89.7
D18 1750000720 S.VCP HVC375BTRF T 40.3/98.6
D19 1750000720 S.VCP HVC375BTRF T 39.1/104.1
D20 1790001260 S.DIO MA2S077-(TX) T 35.2/105.5
D21 1790001240 S.DIO MA2S728-(TX) T 35.2/109
D22 1750000580 S.DIO 1SV307 (TPH3) B 40.4/106.3
D23 1790001250 S.DIO MA2S111-(TX) T 28.1/102.4
D24 1720000640 S.VCP 1SV284 (TPH3) T 13.5/91.3
D25 1750000720 S.VCP HVC375BTRF T 21.9/88.8
D26 1720000640 S.VCP 1SV284 (TPH3) T 13.8/90.1
D27 1720000640 S.VCP 1SV284 (TPH3) T 17.4/89.3
D28 1720000640 S.VCP 1SV284 (TPH3) T 16.2/89.5
D29 1750000770 S.VCP HVC376BTRF T 13.3/85.5
D30 1750000770 S.VCP HVC376BTRF T 13.3/88
D31 1790001250 S.DIO MA2S111-(TX) T 26.2/105.3
D301 1160000050 S.DIO DAP202U T106 T 33.6/26
D302 1160000050 S.DIO DAP202U T106 B 32.4/5.4
D303 1160000050 S.DIO DAP202U T106 T 39.7/27
D304 1160000050 S.DIO DAP202U T106 T 36.5/27.3
D306 1730002320 S.ZEN MA8051-M (TX) B 11.1/5.2
D307 1790001260 S.DIO MA2S077-(TX) B 9/24.5
D308 1790001250 S.DIO MA2S111-(TX) B 21.9/27.1
D309 1790001250 S.DIO MA2S111-(TX) T 37.8/29.3
D310 1750000270 S.DIO 1SS301 (TE85R) B 35.9/5
D311 1750000270 S.DIO 1SS301 (TE85R) B 11.3/7.5
D312 1790001250 S.DIO MA2S111-(TX) B 27.4/44.7
D313 1160000050 S.DIO DAP202U T106 B 23.3/3
FI1 2020001930 S.CER CFWCA450KFFA-R0 T 21.5/57.1
FI2 2020002120 S.CER CFWCA450KGFA-R0 B 28.2/56.7
FI3 2030000410 S.MLH FL-380 MFT46.3P B 20.3/69.6
X1 6050012060 S.XTL CR-796 (15.300 MHz) B 5.4/68.4
X2 6070000190 S.DCR CDBCB450KCAY24-R0 T 12.5/55.5
X300 6050012100 S.XTL CR-800 (3.579545 MHz) B 34.6/38.3
X301 6050012090 S.XTL CR-799 (3.6864 MHz) B 5.4/39.2
X302 6050012110 S.XTL CR-803 (19.6608 MHz) B 7.4/19.5
L1 6200004930 S.COL MLF1608E 8R2K-T B 9.7/68.9
L2 6200011250 S.COL LLQ1608-A18NG B 11.5/85.9
L3 6200007170 S.COL MLF1608A 3R3K-T T 23.2/84.4
L4 6200007170 S.COL MLF1608A 3R3K-T T 10.9/86.7
L6 6200008090 S.COL LQW2BHN68NJ01L T 22.3/86.6
L7 6200003640 S.COL MLF1608E 100K-T T 12.7/92.5
L8 6200003640 S.COL MLF1608E 100K-T T 26.1/87.1
L9 6200011110 S.COL 0.40-2.00-9TL 80.2N T 12.1/95.7
L10 6200007760 S.COL LQW2BHN82NJ01L T 25.9/90.3
L11 6200009180 S.COL ELJRE R10J-F3 T 24.3/96.4
L12 6200011240 S.COL LLQ1608-A33NG B 12.4/94.7
L13 6200011280 S.COL C1608CB-R10G B 20.4/99.2
L14 6200005740 S.COL ELJRE 47NG-F B 13.1/102.9
L15 6200003590 S.COL EXCCL3225U1 B 15.9/117.1
L16 6200005690 S.COL ELJRE 18NG-F T 16.6/115.7
L17 6200008210 S.COL 0.45-1.5-5TL 23.2N B 21.2/117.7
L18 6200009710 S.COL 0.30-0.9-4TL 10.5N B 25.2/117.8
L19 6200008490 S.COL 0.30-0.9-3TR 7.5N B 30.7/117.5
L20 6200008280 S.COL 0.30-1.7-7TL 50N B 32.4/111
L21 6200002860 S.COL NL 252018T-4R7J B 33.3/106
L22 6200009800 S.COL 0.26-1.1-7TR 30N B 38.3/112.7
L23 6200008580 S.COL 0.30-1.4-6TL 32N B 36.8/117.2
L24 6200003540 S.COL MLF1608D R22K-T B 6.9/63.2
L25 6200004480 S.COL MLF1608D R82K-T B 7.8/61
L26 6200002690 S.COL MLF1608A 1R0M-T B 11.5/63.3
L27 6200004660 S.COL MLF1608A 1R8K-T B 20.2/64.6
L29 6200004790 S.COL MLF1608D R47K-T B 20.9/75.5
L30 6130003000 S.COL 617DB-1714=P3 B 26.1/79.2
L31 6130003000 S.COL 617DB-1714=P3 B 31.4/85.1
L32 6200004780 S.COL MLF1608A 1R5K-T B 12.8/63.3
L33 6130003000 S.COL 617DB-1714=P3 B 36.6/79.2
L34 6200011260 S.COL C1608CB-15NG B 30.3/93.5
L35 6200011260 S.COL C1608CB-15NG B 29.5/96.3
L37 6200009920 S.COL C2012C-R10G B 33.4/96.5
L38 6200011050 S.COL C2012C-R12G B 36.6/100
L39 6200011050 S.COL C2012C-R12G B 38.3/103
L40 6200011150 S.COL C1608CB-68NG B 36.5/85.6
L41 6200010400 S.COL ELJRE 39NJ-F B 36/105.8
L42 6200008280 S.COL 0.30-1.7-7TL 50N B 38.1/106.4
L43 6200007170 S.COL MLF1608A 3R3K-T B 15.1/91
L44 6200007170 S.COL MLF1608A 3R3K-T B 25.1/88
L45 6200011130 S.COL C1608CB-12NG B 39.6/82
L46 6200004660 S.COL MLF1608A 1R8K-T B 13.1/80.2
L47 6200007170 S.COL MLF1608A 3R3K-T T 12.1/86.7
L48 6200007170 S.COL MLF1608A 3R3K-T B 16.3/89
L49 6200010100 S.COL C2012C-33NG B 39.3/87.2
L50 6200003640 S.COL MLF1608E 100K-T T 14.5/87.6
L51 6200011120 S.COL 0.40-2.00-10TL 90.5N T 18.2/86.3
L52 6200011150 S.COL C1608CB-68NG T 36.5/87
L53 6200011140 S.COL C1608CB-39NG T 38.4/87.5
L54 6200011150 S.COL C1608CB-68NG T 36.5/89.7
L55 6200010310 S.COL C2012C-27NG B 37.1/91.7
L56 6200011230 S.COL LLQ1608-A22NG B 8.5/85
L57 6200011230 S.COL LLQ1608-A22NG B 8.5/82.4
L58 6200011060 S.COL C1608CB-18NG B 21.8/100.3
L60 6200009890 S.COL C2012C-82NG T 37.9/108.6
L61 6200009920 S.COL C2012C-R10G B 42.1/77.3
L301 6200002860 S.COL NL 252018T-4R7J B 25.7/28.8
S.=Surface mount
REF ORDER DESCRIPTION M. H/V
NO. NO.
LOCATION