Infineon XDPP1100 Product manual

User Manual Please read the Important Notice and Warnings at the end of this document V 1.0
www.infineon.com/xdpp1100 page 1 of 562 2021-08-25
UM_2102_PL88_2103_193611
XDPP1100 technical reference manual
Digital power controller
About this document
Scope and purpose
This document focuses on the XDPP1100 hardware (HW) implementation, and it can be used as a reference
document for firmware (FW) developers. The aim is to describe high-level functions and provide block diagram
illustrations of the implemented HW. Furthermore, the purpose is to demonstrate how the XDPP1100 interacts
with external components within applications, and show how the sensed information from the analog input
pins is processed by the HW.
Intended audience
Power supply design and FW engineers, isolated digital brick module designers, telecom and server power
system designers.
Table of contents
About this document....................................................................................................................... 1
Table of contents............................................................................................................................ 1
1Introduction .......................................................................................................................... 7
1.1 Applications.............................................................................................................................................7
1.2 Control registers and PMBus commands...............................................................................................7
1.3 Naming conventions ...............................................................................................................................8
1.3.1 Loops and phases...............................................................................................................................8
1.3.2 Symbols and abbreviations...............................................................................................................8
1.3.3 Binary number format convention..................................................................................................11
1.4 Structure of this document...................................................................................................................12
2Voltage sense........................................................................................................................13
2.1 VS module configuration ......................................................................................................................14
2.2 Voltage sense analog-to-digital converter...........................................................................................17
2.2.1 Analog front end and front-end compensation..............................................................................18
2.2.2 Tracking ADC ....................................................................................................................................18
2.3 Voltage sense processor .......................................................................................................................20
2.3.1 Output voltage processing ..............................................................................................................20
2.3.2 Rectification voltage processing .....................................................................................................21
2.3.2.1 VRECT timing for single PWM signal...............................................................................................22
2.3.2.2 VRECT watchdog timer...................................................................................................................23
2.3.2.3 Deglitcher ....................................................................................................................................23
2.3.2.4 VRECT timing for two PWM signals ................................................................................................24
2.3.2.5 VIN transient response .................................................................................................................24
2.3.2.6 VRECT start-up programming ........................................................................................................25
2.3.2.7 Same cycle response...................................................................................................................26
2.3.2.8 VRECT delay counters.....................................................................................................................27
2.3.3 VIN processing ...................................................................................................................................28

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2.4 VS registers ............................................................................................................................................28
3Current sense (IS)..................................................................................................................37
3.1 Current sense module configuration....................................................................................................38
3.2 Current sense analog to digital converter............................................................................................40
3.2.1 Current sense analog front end.......................................................................................................41
3.2.2 Current estimator.............................................................................................................................42
3.2.2.1 PWM state....................................................................................................................................43
3.2.2.2 Slope estimator...........................................................................................................................48
3.2.2.3 Error tracking ..............................................................................................................................51
3.2.2.4 Trace inductance of the PCB current sensing............................................................................52
3.3 Current sense processor .......................................................................................................................52
3.3.1 ADC codes to amps...........................................................................................................................53
3.3.2 Peak current limiting........................................................................................................................54
3.3.3 Negative current limiting.................................................................................................................54
3.3.4 Short-circuit protection...................................................................................................................54
3.3.5 Error tracking fault detection ..........................................................................................................55
3.4 Current sense registers .........................................................................................................................56
3.5 Current sense PMBus commands.........................................................................................................64
4Telemetry sense....................................................................................................................66
4.1 Telemetry sense ADC.............................................................................................................................66
4.2 TS input mux and sequencing ..............................................................................................................66
4.3 Telemetry sense current DAC................................................................................................................69
4.4 Telemetry sense processor...................................................................................................................69
4.4.1 Sequencer.........................................................................................................................................70
4.4.2 Gain and offset correction ...............................................................................................................70
4.4.3 VIN computation................................................................................................................................71
4.4.4 Internal temperature (ITSEN) computation....................................................................................71
4.4.5 X-valent measurement.....................................................................................................................72
4.5 Telemetry sense registers .....................................................................................................................73
5Voltage control .....................................................................................................................80
5.1 PMBus commands to HW parameters..................................................................................................81
5.2 Ramp generator.....................................................................................................................................81
5.3 Interrupts...............................................................................................................................................83
5.4 Multi-segment droop (load-line)...........................................................................................................83
5.4.1 Droop voltage computation ............................................................................................................84
5.4.2 Droop voltage filtering.....................................................................................................................86
5.5 Output summation and clamping ........................................................................................................87
5.6 Voltage control registers.......................................................................................................................88
5.7 Voltage control PMBus commands.......................................................................................................95
6Compensator........................................................................................................................98
6.1 Compensation filter ..............................................................................................................................98
6.1.1 Pre-filter............................................................................................................................................99
6.1.2 PID term computation ...................................................................................................................102
6.1.3 Post-filter and summation.............................................................................................................110
6.1.4 Input/output clamping of the compensation filter ......................................................................111
6.1.5 Output override –forced duty cycle..............................................................................................112
6.1.6 Coefficient scaling..........................................................................................................................112
6.1.7 Freeze, reset accumulator .............................................................................................................112
6.2 Input voltage feed-forward.................................................................................................................113

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6.2.1 Output voltage target computation..............................................................................................113
6.2.2 Input voltage source select and computation..............................................................................114
6.2.3 Override and adjustment options for FF .......................................................................................115
6.3 Control mode selection –peak current mode ...................................................................................117
6.4 Open sense fault detection.................................................................................................................117
6.5 Compensation filter registers .............................................................................................................118
7Digital pulse width modulator ..............................................................................................125
7.1 PWM ramp generator ..........................................................................................................................126
7.1.1 PWM ramp modulation schemes...................................................................................................128
7.1.2 PWM ramp synchronization...........................................................................................................130
7.2 PWM pulse generator ..........................................................................................................................132
7.2.1 Pulse generator enable..................................................................................................................132
7.2.2 Ramp selection (loop/phase) ........................................................................................................133
7.2.3 Edge selection (t1/t2).....................................................................................................................133
7.2.4 Dead time programming................................................................................................................135
7.2.5 Force high force low.......................................................................................................................137
7.3 Feedback control modes ....................................................................................................................137
7.3.1 Voltage mode control.....................................................................................................................137
7.3.2 Peak current mode control............................................................................................................139
7.3.3 Maximum and minimum pulse width enforcement .....................................................................140
7.3.4 Forced duty cycle T1, T2 ................................................................................................................141
7.4 Burst mode ..........................................................................................................................................142
7.5 Fast-transient response ......................................................................................................................143
7.5.1 Fast-transient response –load step ..............................................................................................143
7.5.2 Fast-transient response –load release .........................................................................................145
7.6 PWM interrupts....................................................................................................................................146
7.7 PWM registers......................................................................................................................................147
7.8 PWM PMBus commands......................................................................................................................185
8Telemetry ..........................................................................................................................190
8.1 Output voltage (VOUT) telemetry..........................................................................................................190
8.2 Input voltage (VIN) telemetry...............................................................................................................191
8.3 Output current (IOUT) telemetry...........................................................................................................193
8.4 Input current (IIN) telemetry ................................................................................................................193
8.5 Input CE ...............................................................................................................................................194
8.6 Output and input power telemetry ....................................................................................................195
8.7 Temperature telemetry.......................................................................................................................195
8.8 Duty-cycle telemetry...........................................................................................................................197
8.9 Switching frequency (Fswitch) telemetry...............................................................................................197
8.10 General-purpose ADC telemetry.........................................................................................................198
8.11 Telemetry interrupts ...........................................................................................................................200
8.12 Telemetry high/low watermark detect...............................................................................................201
8.13 Telemetry registers .............................................................................................................................202
8.14 PMBus ..................................................................................................................................................228
9Fault handler......................................................................................................................232
9.1 Loop faults...........................................................................................................................................232
9.1.1 Output voltage faults .....................................................................................................................233
9.1.2 Input voltage faults ........................................................................................................................235
9.1.3 Output current faults .....................................................................................................................236
9.1.4 Input current faults ........................................................................................................................238

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9.1.5 Power warnings..............................................................................................................................238
9.1.6 Temperature faults ........................................................................................................................239
9.1.7 Current sharing fault......................................................................................................................240
9.1.8 VOUT_MAX, VOUT_MIN warning.................................................................................................................240
9.1.9 Sync fault........................................................................................................................................240
9.1.10 TON_MAX, TOFF_MAX faults ......................................................................................................................240
9.1.11 Loop fault latching.........................................................................................................................241
9.2 Common faults....................................................................................................................................242
9.2.1 Current sense tracking fault ..........................................................................................................242
9.2.2 Peak current limit fault ..................................................................................................................242
9.2.3 SCP fault .........................................................................................................................................243
9.2.4 Flux balance fault...........................................................................................................................243
9.2.5 Open VS fault protection................................................................................................................243
9.2.6 Common fault latching ..................................................................................................................243
9.3 Fault interrupts (IRQ) ..........................................................................................................................245
9.4 Faults priority encoding......................................................................................................................245
9.5 Fault shutdown ...................................................................................................................................246
9.6 Fault pin mapping ...............................................................................................................................247
9.7 Fault registers......................................................................................................................................248
9.8 Fault PMBus commands .....................................................................................................................271
10 Current sharing (ISHARE) .........................................................................................................285
10.1 Current sharing circuit ........................................................................................................................285
10.2 Current sharing PI filter.......................................................................................................................287
10.3 Current sharing FW override...............................................................................................................288
10.4 Current sharing pin, DAC and ADC configuration...............................................................................289
10.5 Rishare FW patch.....................................................................................................................................289
10.6 Current sharing registers ....................................................................................................................290
10.7 Current sharing PMBus commands ....................................................................................................293
11 Current balance (IBAL)...........................................................................................................294
11.1 Current balance circuit........................................................................................................................294
11.2 Current balance PI filter......................................................................................................................295
11.3 Current balance FW override ..............................................................................................................296
11.4 Current balance registers....................................................................................................................297
12 Flux balance (FBAL) ...............................................................................................................298
12.1 Flux balance circuit .............................................................................................................................298
12.2 Flux balance PI filter............................................................................................................................300
12.3 Flux balance FW override....................................................................................................................301
12.4 Flux balance DCM operation...............................................................................................................301
12.5 Flux balance fault detection ...............................................................................................................302
12.6 Flux balance registers .........................................................................................................................303
13 Fan support........................................................................................................................307
13.1 Fan PWM output ..................................................................................................................................307
13.1.1 Duty-cycle mode ............................................................................................................................308
13.1.2 Current mode .................................................................................................................................308
13.2 Fan speed input...................................................................................................................................309
13.3 Fan registers ........................................................................................................................................310
13.4 Fan PMBus commands........................................................................................................................312
14 IO muxing...........................................................................................................................314

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14.1 Multipurpose digital IO muxing ..........................................................................................................314
14.2 Digital input priority............................................................................................................................316
14.3 GPIO deglitch.......................................................................................................................................316
14.4 Digital IO buffer programming............................................................................................................317
14.5 IO muxing registers .............................................................................................................................317
15 Central processing unit subsystem........................................................................................328
15.1 CPUS bus matrix..................................................................................................................................329
15.2 Cortex®-M0 CPU...................................................................................................................................329
15.2.1 CPU interrupt sources....................................................................................................................330
15.2.2 Cortex®-M0 memory map...............................................................................................................332
15.2.3 Remapping feature ........................................................................................................................333
15.3 Clock and system controller ...............................................................................................................335
15.3.1 System controller unit ...................................................................................................................335
15.3.1.1 SCU registers.............................................................................................................................335
15.3.2 Clock generator unit ......................................................................................................................343
15.3.2.1 Clock dividers............................................................................................................................345
15.3.2.2 Clock gating...............................................................................................................................346
15.3.2.3 Primary-source clock gating.....................................................................................................347
15.3.2.4 CGU registers.............................................................................................................................348
15.3.3 Reset generator unit ......................................................................................................................379
15.3.3.1 Reset sources ............................................................................................................................380
15.3.3.2 Software power-down ..............................................................................................................381
15.3.3.3 Software reset...........................................................................................................................382
15.3.3.4 RGU registers.............................................................................................................................382
15.4 Memory................................................................................................................................................390
15.4.1 Read-only memory.........................................................................................................................390
15.4.2 Random-access memory ...............................................................................................................391
15.4.3 One-time programmable memory ................................................................................................391
15.4.3.1 OTP memory map.....................................................................................................................392
15.4.3.2 OTP configuration interface .....................................................................................................393
15.4.3.3 Indirect OTP access...................................................................................................................393
15.4.3.4 OTP timing configuration .........................................................................................................395
15.4.3.5 OTP direct access......................................................................................................................396
15.4.3.6 OTP module registers ...............................................................................................................399
15.5 Memory management unit .................................................................................................................404
15.5.1 MMU registers.................................................................................................................................405
15.6 DMA controller.....................................................................................................................................476
15.6.1 DMA block diagram ........................................................................................................................477
15.6.2 DMA memory map..........................................................................................................................477
15.6.3 DMA channel assignment...............................................................................................................478
15.6.4 DMA registers..................................................................................................................................479
15.7 General-purpose input output (GPIO) module ..................................................................................485
15.7.1 GPIO registers.................................................................................................................................485
15.8 WDT module ........................................................................................................................................490
15.8.1 Watchdog block diagram...............................................................................................................491
15.8.2 Watchdog registers ........................................................................................................................491
15.9 Dual-timer (DTIMER) modules.................................................................................................................494
15.9.1 Dual-timer block diagram..............................................................................................................495
15.9.2 Dual-timer registers .......................................................................................................................495

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15.10 PMBus module.....................................................................................................................................499
15.10.1 PMBus clock scheme......................................................................................................................501
15.10.2 Interrupt generation ......................................................................................................................501
15.10.3 PMBus operation............................................................................................................................501
15.10.3.1 Configuration ............................................................................................................................502
15.10.3.2 Write transaction.......................................................................................................................503
15.10.3.3 Read byte transaction...............................................................................................................505
15.10.3.4 PMBus ARA command...............................................................................................................508
15.10.4 PMBus registers..............................................................................................................................509
15.11 I2C module ...........................................................................................................................................527
15.11.1 I2C operating modes.......................................................................................................................527
15.11.1.1 Status information....................................................................................................................527
15.11.1.2 Master transmit.........................................................................................................................529
15.11.1.3 Master receive ...........................................................................................................................531
15.11.1.4 Slave transmit ...........................................................................................................................533
15.11.1.5 Slave receive .............................................................................................................................533
15.11.2 I2C registers.....................................................................................................................................534
15.12 CRC module .........................................................................................................................................539
15.12.1 CRC registers ..................................................................................................................................540
15.13 UART ....................................................................................................................................................541
15.13.1 UART block diagram.......................................................................................................................542
15.13.2 UART registers................................................................................................................................542
15.14 Debugger port .....................................................................................................................................557
15.14.1 Serial wire debugger interface.......................................................................................................558
Revision history...........................................................................................................................561

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Introduction
1Introduction
This document focuses on XDPP1100 HW implementation, and it can be used as a reference document by FW
developers. The aim is to describe high-level functions and provide block diagram illustrations of the
implemented HW. Furthermore, the purpose is to demonstrate how the XDPP1100 interacts with external
components within certain applications, and show how the sensed information from the analog input pins is
processed by the HW. Relevant registers and their settings for each HW function are also included in this
document.
This chapter first introduces the applications and topologies where XDPP1100 can be used. Next there is a brief
overview of the PMBus and register programming through the XDP1100 graphical user interface (GUI). General
naming conventions are then summarized, including loop and phase definitions, symbols and abbreviations,
signal naming and binary number formatting. The final section describes the structure of the rest of this
document.
1.1 Applications
The XDPP1100 is versatile digital controller that can be employed in various applications, including isolated
and non-isolated DC-DC brick converters, intermediate bus converters and telecom power supplies, as well as
point-of-load converters. The controller provides flexibility through FW, and the same HW can be configured for
various topologies such as:
•Active clamp forward (ACF)
•Full-bridge (FB) primary with full-wave or center-tap (CT) secondary
•Half-bridge (HB) primary with full-wave or CT secondary
•Buck
•Boost
•Buck-boost
•Unregulated LLC
Independent application notes provide more details regarding certain product features and applications. These
application notes are referenced in the text. Two specific documents of interest are:
•XDPP1100 datasheet
•XDPP1100 digital power supply controller application note
1.2 Control registers and PMBus commands
The XDPP1100 controller is configured by application-specific parameter settings loaded into control registers.
Access to the control register map can be achieved over I2C and PMBus. Module manufacturers can use I2C to
set up controller features and parameters. PMBus commands enable the end user to customize system
applications. Access to the register map is supported by the XDPP1100 GUI. A full listing of the control registers
and their descriptions can be found in the XDPP1100 register descriptions document. Registers associated with
a HW function discussed in this document are also described at the end of the relevant chapter.
For typical applications, the control registers are pre-programmed at the factory and stored in the on-chip non-
volatile memory (NVM), which is then downloaded to the control registers during initialization of the controller
as it powers up. Control registers can be reprogrammed in the field via the serial communication (I2C) bus and
stored in the NVM. The XDPP1100 controllers support multiple reprogramming cycles, and this is easily
accomplished with the XDPP1100 GUI.
In addition to supporting multiple reprogramming cycles, the XDPP1100 controllers also support storing
multiple configurations in NVM, where the initialization setting is selected from one of these stored

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configurations depending on the value of an external resistor connect to the XADDR pin. This capability is
referred to as “multi-config”. This allows a single configuration file to support multiple applications, which is
useful when multiple controllers are used in a system but require different configurations because they support
multiple types of output rails. With multi-config, the XDPP1100 controllers are capable of storing up to 16
configurations, and these 16 configurations may be reprogrammed once if needed. The controller identifies the
proper configuration to load based on information stored in the configuration; this means an indicator bit
identifying a multi-config should be used, with a pointer to the location of the multi-config space in the NVM.
1.3 Naming conventions
Within this document certain naming conventions are used as described in the sections below.
1.3.1 Loops and phases
The XDPP1100 controller supports regulation of up to two output voltages. The two control loops are referred
to as Loop 0 and Loop 1. Loop 0 is associated with voltage sense (VS) input pair VSEN/VREF as well as HW blocks
Voltage Control 0, PID 0 and typically PWM ramp0. PMBus commands relevant to Loop 0 are found on PMBus
PAGE 0. Loop 1 is associated with VS input pair BVSEN/BVREF as well as HW blocks Voltage Control 1, PID 1 and
typically PWM ramp1. PMBus commands relevant to Loop 1 are found on PMBus PAGE 1.
The XDPP1100 controller supports current sense on up to two phases through input pairs ISEN/IREF and
BISEN/BIREF. In a single-loop, dual-phase (interleave) system, these pairs may be referred to as Phase 1
(ISEN/IREF) and Phase 2 (BISEN/BIREF) throughout this and other XDPP1100 documentation.
1.3.2 Symbols and abbreviations
Abbreviations
A Ampere
ACF Active clamp forward
ADC Analog-to-digital converter
AFE Analog front end
APC Amps per code
BOM Bill of materials
BW Bandwidth
CDR Current doubler topology on the secondary
CE Current estimator
CPUS Central processing unit subsystem
DAC Digital-to-analog converter
dc Delta code
DCM Discontinuous conduction mode
DE Dual edge
FB Full-bridge
FBAL Flux balance
FBFB Full-bridge full-bridge rectifier
FEC Front-end compensation
FF Feed-forward
FW Firmware
GPIO General-purpose input output
GUI Graphical user interface
HB Half-bridge
HBCT Half-bridge center tap
HIZ High impedance

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HPF High-pass filter
HW Hardware
IADC Current sense analog-to-digital converter
IBAL Current balance
IO Input output
IPS Integrated power stage
IS AFE Current sense analog front end
ISHARE Current sharing
ISP Current sense processor
LE Leading edge
LPF Low-pass filter
LSB Least significant bit
LUT Look-up table
NLC Negative current limiting
NVM Non-volatile memory
OC Overcurrent
OSP Open voltage sense fault protection
OT Overtemperature
OTA Operational transconductance amplifier
OTP One-time programmable
OV Overvoltage
PCB Printed circuit board
PCL Peak current limiting
PCMC Peak current mode control
PI Proportional-integral
PID Proportional-integral-derivative
PPR Pulses per revolution
PW Pulse width
PWM Pulse width modulation
RO Read-only
ROM Read-only memory
RPM Revolutions per minute
RW Read write
SEG Segment
SCP Short-circuit protection
SR Synchronous rectification
SW Software
TACH Tachometer
TE Trailing edge
TS Telemetry sense
TSADC Telemetry sense analog-to-digital converter
TS IDAC Telemetry sense current digital-to-analog converter
TSP Telemetry sense processor
UC Undercurrent
UV Undervoltage
VMC Voltage mode control
VS Voltage sense
VSADC Voltage sense analog-to-digital converter
VSP Voltage sense processor
XV X-valent

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Latin characters
B Magnetic flux density
BVREF_BVRREF XDPP1100 input pin
BVSEN_BVRSEN XDPP1100 input pin
BVOUT Output voltage, Loop 1
BIREF XDPP1100 input pin for current sensing
BISEN XDPP1100 input pin for current sensing
C Capacitor
COUT Output filter capacitor
fzFrequency of the compensator zero
fpFrequency of the compensator pole
Fsample Sampling frequency
Fswitch Switching frequency
HPI Filter magnitude response
IREF XDPP1100 input pin for current sensing
IRQ Interrupt
ISEN XDPP1100 input pin for current sensing
IIN Input current
ILInductor current
ILOAD Load current
IOUT Output current
KD Derivative term of the compensator
KFP Filter coefficient
KI Integral term of thecompensator
KPProportional term of the compensator
L Inductor
Llk Transformer leakage inductance
LmTransformer magnetizing inductance
LOUT Output filter inductance
LPCB PCB trace inductance
Loop 0 Control Loop 0 associated with PMBus PAGE 0 and VSEN input
Loop 1 Control Loop 1 associated with PMBus PAGE 1 and BVSEN input
NpNumber of primary turns
Ns Number of secondary turns
Phase 1 First interleave phase associated with ISEN input
Phase 2 Second interleave phase associated with BISEN input
PID0 Compensator for Loop 0
PIN Input power
POUT Output power
Q1…n FET
RH Upper sense resistor
Rishare Current share summing resistor
RLLower sense resistor
RLoad Load resistance
RPCB PCB trace resistance
rWWinding resistance
SR1…n Synchronous rectification FET
Toff Off-time
Ton On-time
Tsw Switching period
Vbody Voltage across the body diode

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Vcontrol Internal reference voltage
Verrn Error voltage
VIMON Voltage at the IMON pin
VLInductor voltage
VIN Input voltage
VOUT Output voltage, Loop 0
VPRIMARY Primary-side voltage
VRECT Rectified voltage
VREF XDPP1100 input pin for voltage sensing
VRREF XDPP1100 input pin for voltage sensing
VRSEN XDPP1100 input pin for voltage sensing
VSEN XDPP1100 input pin for voltage sensing
VSEN Sensed voltage
1.3.3 Binary number format convention
Throughout this document in figures and text and in other XDPP1100-related documentation binary numbers
are often referred to as having the form Ux.y for unsigned numbers or Sx.y for signed numbers. The definitions
of these references are given below.
Ux.y indicates an unsigned number, with “x”indicating the bit position of the MSB and “y”indicating the bit
position of the LSB, each relative to the binary point. Sx.y indicates a signed number in two’s compliment
format with “x”and “y”defined as described above for the unsigned case. Figure 1 illustrates the x and y
meanings.
Figure 1 Binary number format x, y definitions
Some unsigned and signed number examples are given below.
•U8.3 is an 11-bit unsigned number with 8 bits to the left of the binary point (MSB weight 27) and 3 bits to the
right of the binary point (LSB weight 2-3).
•U7.0 is a 7-bit unsigned number with 7 bits to the left of the binary point (MSB weight 26) and 0 bits to the
right of the binary point (LSB weight 20).
•U-4.10 is a 6-bit unsigned number with all bits to the right of the binary point. The MSB is offset by 4 bits to
the right of the binary point (MSB weight 2-5) and the LSB is 10 bits to the right of the binary point (LSB
weight 2-10).
•S9.3 is a 12-bit signed number with 9 bits to the left of the binary point (MSB weight 28) and 3 bits to the right
of the binary point (LSB weight 2-3).
•S8.-2 is a 6-bit signed number with all bits to the left of the binary point. The MSB is 8 bits to the left of the
binary point (MSB weight 27) and the LSB is offset by 2 bits to the left of the binary point (LSB weight 22).
.... ...
Bit weight
X = MSB position
Y = LSB position
1234 -3-2-10
0-1-2-3 4321
20
21
22
232-1 2-2 2-3 2-4

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1.4 Structure of this document
The remaining document is divided into 14 chapters, which describe the implemented HW of XDPP1100. Each
chapter presents an independent part of the HW functionality. At the end of each chapter, relevant registers
and PMBus commands related to the described functionality are summarized. Throughout every chapter, the
recommended register programming as well as PMBus commands are provided. Below, the chapter contents
are summarized.
The most important analog functions are discussed within Chapters 2, 3and 4, which describe voltage, current
and telemetry sense, respectively. These chapters specify how XDPP1100 interfaces with the external
environment. System feedback-related functionalities are described in Chapters 5, 6and 7, focusing on the
following topics:
•Chapter 5 illustrates how the control voltage is set for the feedback system as well as the droop voltage
computation.
•Chapter 6 describes the compensation filter and its relevant settings as well as feed-forward (FF) and
control mode selection functionalities.
•Chapter 7 focuses on the implementation of the digital pulse width modulation (PWM) and the
programming of voltage and peak current mode controls (VMC and PCMC), including fast transient
response.
Various submodules for HW computed telemetry are explained in Chapter 8, while Chapter 9 describes the
fault detection and reporting. Current sharing as well as current and flux balancing are all part of the same
block and are discussed in Chapters 10, 11 and 12, respectively. Fan support is implemented as a combination
of HW and FW, and it is explained in Chapter 13. Chapter 14 focuses on the programming of multiple digital IO
pins and Chapter 15 describes the CPU subsystem in detail.

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Voltage sense
2Voltage sense
This chapter describes the VS module and its submodules, voltage sense ADC (VSADC) and voltage sense
processor (VSP) in detail. In addition, the user-programmable settings for configuring the features of the sensed
voltages are described and relevant registers provided.
The XDPP1100 controller has three following analog input pin pairs for voltage sensing:
•VSEN/VREF, for VOUT sensing
•VRSEN/VRREF, for VRECT sensing or primary-side VIN sensing
•BVSEN_BVRSEN/BVREF_BVRREF, for VOUT sensing in dual-loop operation or VRECT sensing for interleaved
topology
Typical connection of VSEN/VREF and VRSEN/VRREF in a FB converter with CT rectifier for VOUT and VRECT sensing
is shown in Figure 2, where the sensed voltage connections are illustrated in red. Both voltages are sensed
through a resistive divider, which introduces gain and needs to be considered in the computations, as will be
discussed further.
Figure 2 VOUT and VRECT sensing in FBCT converter with VMC
Q1
Q2
Llk
Aux supply:
controller VDD
primary-side drive
secondary-side drive
PWM6
Q4
Q3
VD12
VDD
PRISEN
PWRGD
PWM3 PWM1 PWM4
SYNC
TSEN
PWM2
SDA
SCL
EN
XADDR1
SMBALERT#
IMON
To System
PWM5
VREF
VRREF
VRSEN
ISEN
IREF
VSEN
VIN
Driver
Driver
VIN
S2
+
VOUT
-
LOUT
COUT
Driver Copper
Lm
NTC
VRECT

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2.1 VS module configuration
The XDPP1100 controller contains three VS modules, VS0, VS1 and VS2. Each of them is connected to the above-
mentioned analog input pin pairs as follows:
•Input pin pair VSEN/VREF is connected to VS0
•Input pin pair VRSEN/VRREF is connected to VS1
•Input pin pair BVSEN_BVRSEN/BVREF_BVRREF is connected to the module VS2
Depending on the application requirements these input pins can be configured to sense the relevant voltages
and provide the necessary information for further computing. As an example, the following topologies require
different voltage information for different purposes:
•Interleaved single-loop topology (Loop 0)
•Dual-loop topology (Loop 0 and Loop 1)
VS configuration for interleaved single-loop topology
This topology has two phases (Phase 1 and Phase 2) and one control loop. Simplified voltage module
configuration for this topology is shown in Figure 3. The tasks of different VS modules can be summarized as
follows:
•VS0 senses and processes VOUT through the input pins VSEN/VREF and computes the error voltage for Loop 0
compensator (PID0) as well as providing the digitalized VOUT for telemetry and fault processing, as described
in detail in subsection 2.3.1.
•VS1 senses and processes the VRECT of Phase 1 or the input voltage through the input pins VRSEN/VRREF. It
computes their digital representation for VIN telemetry, fault processing, Phase 1 current sensing and flux
balancing as well as input voltage FF computation. VRECT processing is discussed in subsection 2.3.2.
•VS2 senses and processes the VRECT of Phase 2 through the input pins BVRSEN/BVRREF and computes the
digitalized VRECT for Phase 2 current sensing and flux balancing as well as input voltage FF computation.

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Figure 3 VS module configuration for single-loop, dual-phase topology
VS configuration for dual-loop topology
This topology has two control loops and the VS module VS0 is configured in a similar way as the interleaved
topology. The simplified voltage module configuration is presented in Figure 4. The tasks of different VS
modules for this topology can be summarized as:
•VS0 senses and processes Loop 0 output voltage through the input pins VSEN/VREF and computes the error
voltage for Loop 0 compensator (PID0) as well as providing the digitalized VOUT for telemetry and fault
processing, as described in detail in subsection 2.3.1.
•VS1 senses and processes Loop 0 VRECT or the input voltage through the input pins VRSEN/VRREF and
computes their digital representation for VIN telemetry, fault processing and Phase 2 current sensing and flux
balancing. VRECT processing is discussed in subsection 2.3.2.
•VS2 senses and processes Loop 1 output voltage through the input pins BVSEN/BVREF and computes the
error voltage for Loop 1 compensator (PID1) as well as providing the digitalized VOUT for telemetry and fault
processing, as described in detail in subsection 2.3.1.
In the dual-loop configuration, if the VOUT of Loop 0 is the input voltage of Loop 1, the digitalized voltage from
VS0 can be also used for Loop 1 VIN telemetry, fault processing and Phase 2 current sensing. An example of such
configuration is post-buck topology, discussed briefly in subsection 6.2.2.
Regarding the VS module VS1, it should be noted that if both loops (Loop 0 and Loop 1) share the input voltage,
the voltage information provided by the sense pins VRSEN/VRREF can be used also for Loop 1 VIN telemetry,
fault processing and current sensing. However, this information cannot be used for Loop 1 flux balance and so
dual-loop FB with flux balance on both loops is not supported.
VS0
VSEN
VREF VSP0 PID0
Loop 0 VOUT
telemetry,
faults
VS1
VRSEN
VRREF VSP1 Loop 0 VIN
telemetry,
faults
Phase 1 (ISEN)
current sense,
flux balance
Phase 2
(BISEN)
current sense,
flux balance
VS2
BVRSEN
BVRREF VSP2
(VOUT)
(VRECT)
(BVRECT)

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Voltage sense
Figure 4 VS module configuration for dual-loop topology
VS module block diagram for processing VOUT and VRECT
A simplified block diagram of the VS module is shown in Figure 5, while the VS module is processing the output
voltage. Every VS module (VS0, VS1 and VS2) consists of four submodules:
•Analog front end (AFE)
•Front end offset compensation (FEC)
•Tracking ADC
•VSP
Submodules AFE, FEC and ADC are collectively referred to as VSADC. The fourth module, VSP, receives the
VSADC output as its input and it provides a digital representation of either VOUT, VRECT or VIN depending which
voltage is being sensed.
Figure 6 shows the VS module block diagram while VRECT is being processed. The dotted lines illustrate the
additional features related to the VSP in this mode of operation. These additional features are discussed in
subsection 2.3.2. The main difference between the VOUT and VRECT modes is that in VRECT mode, the tracking ADC
only tracks the input when the input voltage is reflected to the secondary-side VRECT.
VS0
VSEN
VREF VSP0 PID0
Loop 0 VOUT
telemetry,
faults
VS1
VRSEN
VRREF VSP1 Loop 0/1 VIN
telemetry,
faults
Phase 1/2
current sense
VS2
BVSEN
BVREF VSP2 PID1
Loop 1 VOUT
telemetry,
faults
(VOUT)
(VRECT or VIN)
(BVOUT)

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Voltage sense
Figure 5 VS module block diagram while processing VOUT
Figure 6 VS module block diagram while processing VRECT
2.2 Voltage sense analog-to-digital converter
This section discusses the VSADC and its relevant submodules in more detail. It receives the sensed voltage as
its input and its output is the digitized version of the same voltage. This ADC consists of three submodules:
•AFE
•FEC
•Tracking ADC
A simplified VSADC block diagram is shown in Figure 7.
FEC
AFE VSP
Tracking
ADC
VSEN
VREF vsadc vout
VSADC
12 12
FEC
AFE
VSP
Tracking
ADC
V(R)SEN
V(R)REF
+
-
vrs_comp_ref
vrs_comp
vsadc vout
vrect
vrs_track
vrs_hold
VSADC

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Figure 7 VSADC block diagram
2.2.1 Analog front end and front-end compensation
AFE is composed of:
•A pair of level shifters connected to the sense and reference input pins (e.g., VSEN/VREF in the case of VS0)
•Unity gain buffers
The level shifters allow a wide input voltage range, 0.0 V to 2.1 V, as well as providing a high input impedance.
The unity gain buffers provide additional drive strength to the tracking ADC input stage.
The main objective of the FEC is to reduce the effects of:
•Temperature
•Stress
•Lifetime-induced offset drift in the AFE
It compares the differential voltages at the input and output of the AFE and compensates for the difference at
the reference path unity gain buffer via a 6-bit DAC. For the FEC module, it is strongly recommended to use the
factory settings, selected automatically when programming via the XDPP1100 GUI (although the FEC module
provides some programmability).
2.2.2 Tracking ADC
The last VSADC submodule, the tracking ADC, consists of:
•Summing amplifier
•Comparator
•Tracking integrator with programmable step size control
•DAC
vsadc
12
vref_buf
vsen_buf
vref_ls
Level
shift
vsen_ls
FEC 6
VSEN
0-2.1V
VREF
(0V)
+
-
+
-
Tracking
ADC
FEC
ADC
Level
shift +
-
+
-

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A simplified block diagram of the tracking ADC is shown in Figure 8. The summing amplifier amplifies the
difference between the buffered differential sensed voltage and the DAC output voltage.
The output of the summing amplifier drives the comparator, whose output determines the size and direction of
the next step for the tracking integrator. The tracking integrator output represents the ADC sensed voltage. It is
also used to drive the DAC, whose output is summed in the summing amplifier.
Figure 8 Tracking ADC block diagram
Tracking ADC resolution is 12 bits with an input-referred least significant bit (LSB) weight of 1.25 mV. Note that
the AFE input range is restricted to maximum of 2.1 V, meaning only the lower 11 bits of the ADC output are
actually used.
The ADC tracking loop integrator step size is programmable via registers:
•vsX_step_en enables user-definable step size control
•vsX_step sets a fixed integrator step size
The X in the register name denotes 0, 1 or 2, depending which VS module is being utilized. For the highest
accuracy, a fixed step size of 1 is recommended. If automatic step size is programmed by setting vsX_step_en =
0, the XDPP1100 automatically selects the step size between 1 and 7 based on the perceived distance from the
input voltage.
Table 1 shows the recommended settings for step size control for each VS module.
Table 1 Recommended settings for step size control of VS modules
VS module
Pin
Sensing
Recommended settings
VS0
VSEN
VOUT
vs0_step_en = 1,
vs0_step = 1
VS1
VRSEN
VRECT
vs1_step_en = 0,
vs1_step = 1
VS1
VRSEN
VIN
vs1_step_en = 1,
vs1_step = 1
VS2
BVSEN_BVRSEN
VOUT, VIN
vs2_step_en = 1,
vs2_step = 1
VS2
BVSEN_BVRSEN
VRECT
vs2_step_en = 0,
vs2_step = 1
+
-
vref_buf
vsen_buf Summing
amp
+
-100 MHz
Comparator Step
algorithm
DQ
100 MHz
D Q
100 MHz
12-bit
DAC
12 12 vsadc
Tracking integrator
++
+
-

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2.3 Voltage sense processor
The VSP receives the tracking ADC output (the digitized sensed voltage) as its input. Depending on the
assignment of the specific module, it processes the incoming data in order to produce:
•Output and error voltages
•Rectification voltage
•Primary-side input voltage
The VS module connected to the input pins VSEN/VREF is always assigned to the output voltage. However, for
the modules VS1 and VS2, the user can control the selection of VOUT or VRECT via registers vsp1_vrs_sel and
vsp2_vrs_sel.
In the following subsections detailed processing of VOUT, VRECT and VIN is described in more detail as well as the
relevant user-definable parameters.
2.3.1 Output voltage processing
For output voltage processing, the VS module is configured for VOUTvia register vsp1_vrs_sel or vsp2_vrs_sel,
depending on which input pins are used to sense the voltage. A simplified block diagram of the VOUT processing
function and error computing is shown in Figure 9.
Figure 9 Simplified block diagram of the output voltage processing
The tracking ADC output, VSADC, is received at the conversion rate of 100 MHz. It is decimated (downsampled)
to 50 MHz, and thereafter digital gain and offset trim is applied. The resulting registered output represents the
differential voltage applied to the sense and reference input pins. This is the digital representation of the
output voltage, and it is sent downstream for further processing by the following modules:
•Telemetry
•Fault
•Current sense
In addition to VOUT, the VSP also computes the error voltage, Verrn, used by the compensation filter. The error
voltage is defined in Equation (2.1)
 , (2.1)
where:
•Measured voltage is the gain and offset corrected ADC output
•Target voltage comes from the VCM
+
vsadc
412.0
12 12
vcontrol
412.3
vsp_verrn_clamp_thresh
vs_verrn_fs
58.3
vsp_vout_fs
412.0
50MHz
12
12 D Q
-
Clamp
15
3
12
Decimator
50MHz
100MHz
Gain &
Offset Trim