Abov MC97F6108A User manual

MC97F6108A
User’s Manual
16 MHz 8-bit Microcontroller
8KB Flash, 12-bit ADC, Analog Comparator and OP-AMP
User’s Manual Version 1.12
Global Top Smart MCU Innovator
www.abovsemi.com
Introduction
This user’s manual targets application developers who use MC97F6108A for their specific needs. This
document provides complete information of how to use MC97F6108A device. Standard functions and
blocks including corresponding register information of MC97F6108A are introduced in each chapter,
while instruction set is in Appendix.
MC97F6108A is based on M8051 core, and provides standard features of 8051 such as 8-bit ALU, PC,
8-bit registers, timers and counters, serial data communication, PSW, DPTR, SP, 8-bit data bus and
2x16-bit address bus, and 8/11/16-bit operations.
In addition, this device offers highly flexible and cost effective solutions with the following peripherals
inside: 8Kbytes of FLASH, 256bytes of IRAM, 256bytes of XRAM, General Purpose I/Os, Basic Interval
Timer, Watchdog Timer, 16-bit timer/counter, 16-bit PWM output, 16-bit PPG output, UART, I2C, 12-bit
A/D Converter, analog comparator, on-chip OP-AMP, buzzer driving port, on-chip POR, LVR, BOD, on-
chip oscillator and clock circuitry.
As a field proven best seller, MC97F6108A has been sold more than 3 billion units up to now, and
introduces rich features such as excellent noise immunity, code optimization, cost effectiveness, and
so on.
Reference document
MC97F6108A programming tools and manuals released by ABOV: They are available at
ABOV website, www.abovsemi.com.
SDK-51 User’s guide (System Design Kit) released by Intel in 1982: It contains all of
components of a single-board computer based on Intel’s 8051 single-chip microcomputer.
Information on Mentor Graphics 8051 microcontroller: The technical document is provided at
Mentorwebsite: https://www.mentor.com/products/ip/peripheral/microcontroller/

Contents MC97F6108A User’s manual
2
Contents
Introduction..............................................................................................................................................1
Reference document...............................................................................................................................1
1Description ...................................................................................................................................12
1.1 Device overview................................................................................................................12
1.2 MC97F6108A block diagram.............................................................................................14
2Pinouts and pin description..........................................................................................................15
2.1 Pinouts ..............................................................................................................................15
2.2 Pin description...................................................................................................................17
3Port structures..............................................................................................................................19
4Memory organization....................................................................................................................22
4.1 Program memory...............................................................................................................23
4.2 Data memory.....................................................................................................................24
4.3 External data memory.......................................................................................................26
4.4 SFR mapd.........................................................................................................................27
4.4.1 SFR map summary...............................................................................................27
4.4.2 SFR map...............................................................................................................29
4.4.3 Compiler compatible SFR.....................................................................................34
5I/O ports .......................................................................................................................................36
5.1 Port register.......................................................................................................................36
5.1.1 Data Register (Px)................................................................................................36
5.1.2 Direction Register (PxIO)......................................................................................36
5.1.3 Pull-up Register Selection Register (PxPU).........................................................36
5.1.4 Open-drain Selection Register (PxOD) ................................................................36
5.1.5 De-bounce Enable Register (PxDB).....................................................................36
5.1.6 Port Selection Register (psrx)...............................................................................36
5.1.7 Register map ........................................................................................................37
5.2 P0 port...............................................................................................................................38
5.2.1 P0 port description................................................................................................38
5.2.2 Register description for P0...................................................................................38
5.3 P1 port...............................................................................................................................42
5.3.1 P1 port description................................................................................................42
5.3.2 Register description for P1...................................................................................42
5.4 P2 port...............................................................................................................................44
5.4.1 P2 port description................................................................................................44
5.4.2 Register description for P2...................................................................................44
6Interrupt controller........................................................................................................................46
6.1 External interrupt...............................................................................................................48
6.2 Comparator Interrupt and Comparator Flag......................................................................49
6.3 Block diagram....................................................................................................................50
6.4 Interrupt vector table .........................................................................................................51
6.5 Interrupt sequence ............................................................................................................52
6.6 Effective timing after controlling interrupt bit.....................................................................53
6.7 Multi-interrupt ....................................................................................................................54
6.8 Interrupt enable accept timing...........................................................................................55
6.9 Interrupt service routine address.......................................................................................55
6.10 Saving/restore general purpose registers.........................................................................55
6.11 Interrupt timing ..................................................................................................................56
6.12 Interrupt register overview.................................................................................................57

MC97F6108A User’s manual Contents
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6.12.1 Interrupt Enable Register (IE, IE1, IE2, and IE3) .................................................57
6.12.2 Interrupt Priority Register (IP, IPH, IP1, IP1H, IP2, IP2H, IP3 and IP3H)............57
6.12.3 External Interrupt Flag Enable Register (EIENAB) ..............................................57
6.12.4 External Interrupt Flag Register (EIFLAG) ...........................................................57
6.12.5 External Interrupt Flag Edge Register (EIEDGE).................................................57
6.12.6 External Interrupt Polarity Register (EIPOLA)......................................................57
6.12.7 External Interrupt Flag Both Edge Enable Register (EIBOTH) ............................57
6.12.8 Comparator Interrupt Flag Enable Register (CIENAB) ........................................58
6.12.9 Comparator Interrupt Flag Register (CIFLAG).....................................................58
6.12.10Comparator Interrupt Flag Edge Register (CIEDGE)...........................................58
6.12.11Comparator Interrupt Polarity Flag Register (CIPOLA)........................................58
6.12.12Comparator Interrupt Flag Both Edge Enable Register (CIBOTH) ......................58
6.12.13Comparator Flag Enable Register (CFENAB)......................................................58
6.12.14Comparator Flag Register (CFFLAG) ..................................................................58
6.12.15Comparator Flag Edge Register (CFEDGE)........................................................59
6.12.16Comparator Flag Polarity Register (CFPOLA).....................................................59
6.12.17Comparator Flag Both Edge Enable Register (CFBOTH)....................................59
6.12.18Pin Change Interrupt Enable Register (PCI)........................................................59
6.12.19Register map ........................................................................................................60
6.12.20Interrupt register description.................................................................................61
7Clock generator............................................................................................................................75
7.1 Clock generator block diagram .........................................................................................75
7.2 Register map.....................................................................................................................76
7.3 Register description ..........................................................................................................76
8Basic Interval Timer (BIT) ............................................................................................................77
8.1 BIT block diagram .............................................................................................................77
8.2 BIT register map................................................................................................................77
8.3 BIT register description .....................................................................................................78
9Watchdog Timer (WDT) ...............................................................................................................79
9.1 WDT interrupt timing waveform.........................................................................................79
9.2 WDT block diagram...........................................................................................................80
9.3 Register map.....................................................................................................................80
9.4 Register description ..........................................................................................................81
10 Timer0/1/2/3.................................................................................................................................82
10.1 Capture and event counter source for timer0/1/2/3 and PPG...........................................82
10.2 16-bit timer/counter mode .................................................................................................83
10.3 16-bit capture mode ..........................................................................................................84
10.4 16-bit PWM mode..............................................................................................................85
10.5 Register map.....................................................................................................................88
10.6 Register description ..........................................................................................................90
11 PPG (Programmable Pulse Generator) .......................................................................................94
11.1 PPG block diagram ...........................................................................................................95
11.2 PPG start and one shot pulse ...........................................................................................96
11.3 PPG period/duty write .......................................................................................................98
11.4 Capture mode....................................................................................................................99
11.5 Disable PPG output by comparator 1..............................................................................100
11.6 Disable PPG output by comparator 3..............................................................................101
11.7 PPG period limitation ......................................................................................................102
11.8 Auto period mode by comparator 2.................................................................................103
11.8.1 PPG period decrease.........................................................................................104

Contents MC97F6108A User’s manual
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11.8.2 PPG period when ATPSEL = 2'b00....................................................................105
11.8.3 PPG period when ATPSEL = 2'b01....................................................................106
11.8.4 PPG period when ATPSEL = 2'b1x....................................................................107
11.8.5 PPG period when writing....................................................................................109
11.8.6 PPG period min/max limitation...........................................................................111
11.8.7 PPG off-time max/min limitation.........................................................................114
11.9 Register map...................................................................................................................116
11.10 Register description ........................................................................................................117
12 Analog comparator and OP-AMP ..............................................................................................125
12.1 Comparator and OP-AMP description.............................................................................126
12.2 Block diagram..................................................................................................................128
12.3 Register description ........................................................................................................129
13 Buzzer driver..............................................................................................................................136
13.1 Buzzer driver block diagram............................................................................................138
13.2 Register map...................................................................................................................138
13.3 Register description ........................................................................................................139
14 12-bit AD Converter (ADC) ........................................................................................................140
14.1 Conversion timing............................................................................................................140
14.2 Block diagram..................................................................................................................140
14.3 ADC operation.................................................................................................................142
14.4 Register map...................................................................................................................143
14.5 Register description ........................................................................................................144
15 USART.......................................................................................................................................147
15.1 Block diagram..................................................................................................................148
15.2 Clock generation .............................................................................................................149
15.3 External clock (XCK).......................................................................................................150
15.4 Synchronous mode operation.........................................................................................150
15.5 Data format......................................................................................................................151
15.6 Parity bit ..........................................................................................................................152
15.7 USART transmitter..........................................................................................................152
15.7.1 Sending Tx data .................................................................................................152
15.7.2 Transmitter flag and interrupt .............................................................................152
15.7.3 Parity generator..................................................................................................153
15.7.4 Disabling transmitter...........................................................................................153
15.8 USART receiver ..............................................................................................................153
15.8.1 Receiving Rx data ..............................................................................................153
15.8.2 Receiver flag and interrupt .................................................................................154
15.8.3 Parity checker.....................................................................................................154
15.8.4 Disabling receiver...............................................................................................155
15.8.5 Asynchronous data reception.............................................................................155
15.9 SPI mode.........................................................................................................................157
15.9.1 SPI clock formats and timing..............................................................................157
15.10 Register map...................................................................................................................160
15.11 Register description ........................................................................................................161
15.12 Baud rate settings (example) ..........................................................................................166
16 Inter Integrated Circuit (I2C) ......................................................................................................168
16.1 Block diagram..................................................................................................................168
16.2 I2C bit transfer.................................................................................................................169
16.3 Start/ Repeated Start/ Stop.............................................................................................169
16.4 Data transfer....................................................................................................................170

MC97F6108A User’s manual Contents
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16.5 Acknowledge...................................................................................................................171
16.6 Synchronization/ arbitration.............................................................................................172
16.7 Block Operation...............................................................................................................173
16.7.1 I2C block initialization process ...........................................................................174
16.7.2 I2C interrupt service ...........................................................................................175
16.7.3 Master transmitter...............................................................................................176
16.7.4 Slave receiver.....................................................................................................178
16.8 Register map...................................................................................................................179
16.9 I2C register description ...................................................................................................180
17 Power down operation ...............................................................................................................184
17.1 Peripheral operation in IDLE/ STOP mode.....................................................................184
17.2 IDLE mode ......................................................................................................................185
17.3 STOP mode.....................................................................................................................186
17.4 Released operation of STOP mode................................................................................188
17.5 Register map...................................................................................................................189
17.6 Register description ........................................................................................................189
18 Reset..........................................................................................................................................190
18.1 Reset block diagram .......................................................................................................190
18.2 RESET noise canceller ...................................................................................................191
18.3 Power on reset................................................................................................................191
18.4 External RESETB input...................................................................................................194
18.5 Brown out detector processor .........................................................................................195
18.6 Register map...................................................................................................................196
18.7 Register description for reset operation..........................................................................197
19 Memory programming................................................................................................................199
19.1 Flash control and status registers ...................................................................................199
19.1.1 Register map ......................................................................................................199
19.1.2 Register description............................................................................................200
19.2 Memory map ...................................................................................................................206
19.2.1 Flash memory map.............................................................................................206
19.3 Serial in-system program mode......................................................................................207
19.3.1 Flash operation...................................................................................................207
19.4 Parallel mode ..................................................................................................................214
19.4.1 Parallel mode instruction format.........................................................................215
19.4.2 Parallel mode timing diagram.............................................................................216
19.5 Mode entrance method of ISP mode ..............................................................................217
19.5.1 Mode entrance method for ISP ..........................................................................217
19.5.2 Mode entrance of byte-parallel...........................................................................217
19.6 Security ...........................................................................................................................218
19.7 Configure option..............................................................................................................219
20 Electrical characteristics.............................................................................................................220
20.1 Absolute maximum ratings..............................................................................................220
20.2 Recommended operating conditions ..............................................................................220
20.3 Internal RC oscillator characteristics...............................................................................221
20.4 Internal WDT oscillator characteristics............................................................................221
20.5 Voltage Dropout Converter characteristics .....................................................................221
20.6 A/D Converter characteristics .........................................................................................222
20.7 Low voltage reset characteristics....................................................................................222
20.8 Brown out Detector characteristics .................................................................................223
20.9 Power on Reset characteristics.......................................................................................223

Contents MC97F6108A User’s manual
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20.10 DC characteristics...........................................................................................................224
20.11 AC characteristics ...........................................................................................................225
20.12 Analog comparator characteristics..................................................................................226
20.13 Operational amplifier characteristics...............................................................................226
20.14 USART characteristics....................................................................................................227
20.15 SPI characteristics...........................................................................................................228
20.16 I2C characteristics...........................................................................................................229
20.17 Data retention voltage in STOP mode ............................................................................230
20.18 Internal Flash ROM characteristics.................................................................................231
20.19 Input/output capacitance.................................................................................................231
20.20 Operating voltage range..................................................................................................232
20.21 Recommended circuit and layout....................................................................................232
20.22 Typical characteristics.....................................................................................................233
21 Package information ..................................................................................................................235
21.1 20 SOP package information ..........................................................................................235
21.2 16 SOPN package information........................................................................................236
22 Ordering information ..................................................................................................................237
23 Development tools .....................................................................................................................238
23.1 Compiler..........................................................................................................................238
23.2 OCD II (On-chip debugger II) emulator and debugger....................................................238
23.3 Programmers...................................................................................................................239
23.3.1 E-PGM+..............................................................................................................239
23.3.2 OCD II emulator..................................................................................................240
23.3.3 Gang programmer ..............................................................................................240
23.4 Flash programming .........................................................................................................241
23.4.1 On-board programming......................................................................................241
23.4.2 Circuit design guide............................................................................................242
23.5 On-chip debug system ....................................................................................................243
23.5.1 Two-pin external interface..................................................................................245
Appendix .............................................................................................................................................249
Instruction table..........................................................................................................................249
Revision history...................................................................................................................................255

MC97F6108A User’s manual List of figures
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List of figures
Figure 1. MC97F6108A Block Diagram ................................................................................................14
Figure 2. MC97F6108A 20 SOP Pin Assignment .................................................................................15
Figure 3. MC97F6108A 16 SOPN Pin Assignment...............................................................................16
Figure 4. General Purpose I/O Port ......................................................................................................19
Figure 5. Secondary Function I/O Port .................................................................................................20
Figure 6. Analog Input I/O Port .............................................................................................................21
Figure 7. Program Memory Map ...........................................................................................................23
Figure 8. Data Memory Map .................................................................................................................24
Figure 9. Lower 128bytes of RAM ........................................................................................................25
Figure 10. XDATA Memory Area ...........................................................................................................26
Figure 11. Interrupt Group Priority Level ...............................................................................................47
Figure 12. External Interrupt Description ..............................................................................................48
Figure 13. Comparator Interrupt and Comparator Flag Description .....................................................49
Figure 14. Interrupt Controller Block Diagram ......................................................................................50
Figure 15. Interrupt Sequence Flow......................................................................................................52
Figure 16. Effective Timing of Interrupt Enable Register ......................................................................53
Figure 17. Effective Timing of Interrupt Flag Register...........................................................................53
Figure 18. Effective Timing of Multi-Interrupt ........................................................................................54
Figure 19. Interrupt Response Timing Diagram ....................................................................................55
Figure 20. Correspondence between Vector Table Address and the Entry Address of ISR .................55
Figure 21. Saving/Restore Process Diagram and Sample Source.......................................................55
Figure 22. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction ...............................56
Figure 23. Clock Generator Block Diagram ..........................................................................................75
Figure 24. Basic Interval Timer Block Diagram.....................................................................................77
Figure 25. Watchdog Timer Interrupt Timing Waveform .......................................................................79
Figure 26. Watchdog Timer Block Diagram ..........................................................................................80
Figure 27. 16-bit Timer/Counter Mode of Timer0/1/2/3 .........................................................................83
Figure 28. 16-bit Capture Mode of Timer0/1/2/3 ...................................................................................84
Figure 29. 16-bit PWM Mode of Timer0/1/2/3 .......................................................................................86
Figure 30. 16-bit PWM Example at 16MHz...........................................................................................86
Figure 31. 16-bit PWM Example at 16MHz (Period=Duty) ...................................................................87
Figure 32. PPG Block Diagram .............................................................................................................95
Figure 33. PPG Start and One Shot Pulse ...........................................................................................97
Figure 34. PPG Period/Duty Write ........................................................................................................98
Figure 35. PPG Period/Duty Load to Compare Registers ....................................................................98
Figure 36. Capture Mode ......................................................................................................................99
Figure 37. Disable PPG Output by Comparator 1 ..............................................................................100
Figure 38. Disable PPG Output by Comparator 1 (C1_FLAG) ...........................................................100
Figure 39. Disable PPG Output Block Diagram by Comparator 3 ......................................................101
Figure 40. Disable PPG Output by Comparator 3 (C3_FLAG) ...........................................................101
Figure 41. PPG Period Limitation .......................................................................................................102
Figure 42. Auto Period Mode Block Diagram......................................................................................103
Figure 43. Period Decrement Block Diagram in Auto Period Mode ...................................................104
Figure 44. Period Decrement in Auto Period Mode............................................................................104
Figure 45. Auto Period Mode Block Diagram (ATPSEL = 2'b00) .......................................................105
Figure 46. Auto Period Mode (ATPSEL = 2'b00)................................................................................105
Figure 47. Auto Period Mode Block Diagram (ATPSEL = 2'b01) .......................................................106
Figure 48. Auto Period Mode (ATPSEL = 2'b01)................................................................................106

List of figures MC97F6108A User’s manual
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Figure 49. Auto Period Mode Block Diagram (ATPSEL = 2'b1x)........................................................107
Figure 50. Auto Period Mode (ATPSEL = 2'b1x)................................................................................108
Figure 51. PPG Period Block Diagram When Writing.........................................................................109
Figure 52. PPG Period When Writing (ATPSEL = 2'b1x) ...................................................................110
Figure 53. Max and Min Period Limitation .......................................................................................... 111
Figure 54. PPG Period Block Diagram When Period Min/Max Matching...........................................112
Figure 55. When Max Period Matching...............................................................................................112
Figure 56. When Min Period Matching................................................................................................113
Figure 57. PPG Off-time Max/Min Limitation Block Diagram..............................................................114
Figure 58. PPG Off-time Max/Min Limitation ......................................................................................115
Figure 59. Analog Comparator and OP-AMP Block Diagram .............................................................128
Figure 60. Buzzer Driver Block Diagram.............................................................................................138
Figure 61. 12-bit ADC Block Diagram .................................................................................................141
Figure 62. A/D Analog Input Pin with a Capacitor ...............................................................................141
Figure 63. A/D Power (AVREF) Pin with a Capacitor..........................................................................141
Figure 64. Control Registers and Align Bits ........................................................................................142
Figure 65. ADC Operation Flow Sequence .........................................................................................143
Figure 66. USART Block Diagram ......................................................................................................148
Figure 67. Clock Generation Block Diagram.......................................................................................149
Figure 68. Synchronous Mode XCK Timing ........................................................................................150
Figure 69. A Frame Format .................................................................................................................151
Figure 70. Start Bit Sampling ..............................................................................................................155
Figure 71. Sampling of Data and Parity Bit.........................................................................................156
Figure 72. Stop Bit Sampling and Next Start Bit Sampling.................................................................156
Figure 73. SPI Clock Formats when UCPHA = 0................................................................................158
Figure 74. SPI Clock Formats when UCPHA = 1................................................................................159
Figure 75. I2C Block Diagram .............................................................................................................168
Figure 76. Bit Transfer on the I2C-Bus ...............................................................................................169
Figure 77. START and STOP Condition..............................................................................................169
Figure 78. Data Transfer on the I2C-Bus ............................................................................................170
Figure 79. Acknowledge on the I2C-Bus.............................................................................................171
Figure 80. Clock Synchronization during Arbitration Procedure .........................................................172
Figure 81. Arbitration Procedure of Two Masters................................................................................172
Figure 82. IDLE Mode Release Timing by an External Interrupt ........................................................185
Figure 83. IDLE Mode Release Timing by an RESETB......................................................................185
Figure 84. STOP Mode Release Timing by External Interrupt............................................................186
Figure 85. STOP Mode Release Timing by RESETB .........................................................................187
Figure 86. STOP1, 2 Mode Release Flow ..........................................................................................188
Figure 87. Reset Block Diagram .........................................................................................................190
Figure 88. Reset Noise Canceller Time Diagram................................................................................191
Figure 89. Fast VDD Rising Time .......................................................................................................191
Figure 90. Internal RESET Release Timing On Power-Up .................................................................192
Figure 91. Configuration Timing when Power-on................................................................................192
Figure 92. Boot Process Waveform ....................................................................................................193
Figure 93. Timing Diagram after RESET ............................................................................................194
Figure 94. Oscillator Generating Waveform Example.........................................................................194
Figure 95. BOD Block Diagram...........................................................................................................195
Figure 96. Internal Reset at Power Fail Situation ...............................................................................195
Figure 97. Configuration Timing When LVR RESET...........................................................................196
Figure 98. Read Device Internal Checksum (Full Size: 0x0000~0x1FFF) .........................................204

MC97F6108A User’s manual List of figures
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Figure 99. Flash Memory Map ............................................................................................................206
Figure 100. Address Configuration of Flash Memory .........................................................................206
Figure 101. The Sequence of Page Program and Erase of Flash Memory........................................207
Figure 102. The Sequence of Bulk Erase of Flash Memory ...............................................................208
Figure 103. Pin Diagram for Parallel Programming ............................................................................214
Figure 104. Parallel Byte Read Timing of Program Memory ..............................................................216
Figure 105. Parallel Byte Write Timing of Program Memory...............................................................216
Figure 106. ISP Mode .........................................................................................................................217
Figure 107. Byte-Parallel Mode ..........................................................................................................217
Figure 108. AC Timing.........................................................................................................................225
Figure 109. Waveform for USART Timing Characteristics..................................................................227
Figure 110. Timing Waveform for the USART Module ........................................................................227
Figure 111. SPI Timing ........................................................................................................................228
Figure 112. I2C Timing ........................................................................................................................229
Figure 113. STOP Mode Release Timing when Initiated by an Interrupt ............................................230
Figure 114. STOP Mode Release Timing when Initiated by RESETB ................................................230
Figure 115. Operating Voltage Range.................................................................................................232
Figure 116. Recommended Voltage Range ........................................................................................232
Figure 117. Output High Voltage (VOH)..............................................................................................233
Figure 118. Output Low Voltage (VOL) ...............................................................................................234
Figure 119. 20 SOP Package Outline .................................................................................................235
Figure 120. 16 SOPN Package Outline ..............................................................................................236
Figure 121. MC97F6108A Device Numbering Nomenclature.............................................................237
Figure 122. Debugger (OCD1/OCD2) and Pinouts ............................................................................239
Figure 123. E-PGM+ (Single Writer) and Pinouts ...............................................................................239
Figure 124. E-Gang4 and E-Gang6 (for Mass Production) ................................................................240
Figure 125. PCB Design Guide for On-Board Programming ..............................................................242
Figure 126. On-Chip Debugging System in Block Diagram................................................................244
Figure 127. 10-bit Transmission Packet..............................................................................................245
Figure 128. Data Transfer on Twin Bus ..............................................................................................246
Figure 129. Bit Transfer on Serial Bus ................................................................................................246
Figure 130. Start and Stop Condition..................................................................................................246
Figure 131. Acknowledge on Serial Bus .............................................................................................247
Figure 132. Clock Synchronization during Wait Procedure ................................................................247
Figure 133. Connection of Transmission ............................................................................................248

List of tables MC97F6108A User’s manual
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List of tables
Table 1. MC97F6108A Device Features and Peripheral Counts ..........................................................12
Table 2. Normal Pin Description............................................................................................................17
Table 3. SFR Map Summary .................................................................................................................27
Table 4. XSFR Map Summary ..............................................................................................................28
Table 5. SFR Map .................................................................................................................................29
Table 6. XSFR Map ...............................................................................................................................33
Table 7. Port Register Map....................................................................................................................37
Table 8. Interrupt Vector Address Table ................................................................................................51
Table 9. Interrupt Register Map.............................................................................................................60
Table 10. Clock Generator Register Map..............................................................................................76
Table 11. Basic Interval Timer Register Map.........................................................................................77
Table 12. Watchdog Timer Register Map ..............................................................................................80
Table 13. Capture and Event Counter Source ......................................................................................82
Table 14. PWM Frequency vs. Resolution at 16MHz ...........................................................................85
Table 15. Register Map .........................................................................................................................88
Table 16. Register Map .......................................................................................................................116
Table 17. Buzzer Frequency at 1MHz.................................................................................................137
Table 18. Buzzer Driver Register Map ................................................................................................138
Table 19. ADC Register Map...............................................................................................................143
Table 20. Equations for Calculating Baud Rate Register Setting........................................................149
Table 21. CPOL Functionality..............................................................................................................157
Table 22. USART Register Map ..........................................................................................................160
Table 23. Examples of UBAUD Settings for Commonly Used Oscillator Frequencies .......................166
Table 24. Register Map .......................................................................................................................179
Table 25. Peripheral Operation Status during Power Down Mode .....................................................184
Table 26. Power Down Operation Register Map.................................................................................189
Table 27. Hardware Setting Values in Reset State .............................................................................190
Table 28. Boot Process Description ....................................................................................................193
Table 29. Reset Operation Register Map............................................................................................196
Table 30. Flash Control and Status Register Map ..............................................................................199
Table 31. Program and Erase Time ....................................................................................................205
Table 32. Operation Mode...................................................................................................................213
Table 33. Selection of Memory Type by ADDRH[7:4] .........................................................................214
Table 34. Parallel Mode Instruction Format ........................................................................................215
Table 35. Mode Entrance Method for ISP ...........................................................................................217
Table 36. Mode Entrance of Byte-Parallel...........................................................................................217
Table 37. Security Policy using Lock Bits............................................................................................218
Table 38. Absolute Maximum Ratings.................................................................................................220
Table 39. Recommended Operating Conditions .................................................................................220
Table 40. Internal RC Oscillator Characteristics .................................................................................221
Table 41. Internal WDT Oscillator Characteristics ..............................................................................221
Table 42. Voltage Dropout Converter Characteristics .........................................................................221
Table 43. A/D Converter Characteristics .............................................................................................222
Table 44. Low Voltage Reset Characteristics......................................................................................222
Table 45. Brown out Detector Characteristics.....................................................................................223
Table 46. Power-on Reset Characteristics..........................................................................................223
Table 47. DC Characteristics...............................................................................................................224
Table 48. AC Characteristics ...............................................................................................................225

MC97F6108A User’s manual List of tables
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Table 49. Analog Comparator DC Characteristics ..............................................................................226
Table 50. Operational Amplifier Characteristics ..................................................................................226
Table 51. USART Characteristics........................................................................................................227
Table 52. SPI Characteristics ..............................................................................................................228
Table 53. I2C Characteristics ..............................................................................................................229
Table 54. Data Retention Voltage in STOP Mode ...............................................................................230
Table 55. Internal Flash ROM Characteristics ....................................................................................231
Table 56. Input/Output Capacitance....................................................................................................231
Table 57. MC97F6108A Device Ordering Information ........................................................................237
Table 58. Pins for Flash Programming................................................................................................241
Table 59. OCD II Features ..................................................................................................................243
Table 60. Instruction Table: Arithmetic.................................................................................................249
Table 61. Instruction Table: Logical .....................................................................................................250
Table 62. Instruction Table: Data Transfer ..........................................................................................251
Table 63. Instruction Table: Boolean ...................................................................................................252
Table 64. Instruction Table: Branching ................................................................................................253
Table 65. Instruction Table: Miscellaneous .........................................................................................254
Table 66. Instruction Table: Additional Instructions .............................................................................254

1. Description MC97F6108A User’s manual
12
1Description
MC97F6108A is an advanced CMOS 8-bit microcontroller with 8Kbytes of FLASH. This is a powerful
microcontroller which provides a highly flexible and cost effective solution to many embedded control
applications.
1.1 Device overview
In this section, features of MC97F6108A and peripheral counts are introduced.
Table 1. MC97F6108A Device Features and Peripheral Counts
Peripherals
Description
Core
CPU
8-bit CISC core (M8051, 2 clocks per cycle)
Interrupt
Up to 23 peripheral interrupts supported.
EINT0, EINT1, EINT2, PCI (4)
Comparator output (5)
I2C (1)
USART (2)
Timer (0/1/2/3) (4)
PPG (1)
ADC (1)
WDT (1)
BIT (1)
BOD (1)
ATP MAX/MIN (2)
Memory
ROM (FLASH)
capacity
8Kbytes FLASH with self-read and write capability
In-system programming (ISP)
Endurance: 10,000times
Retention: 10years
IRAM
256Bytes
XRAM
256Bytes
Pin change interrupt
P1[7:0]
Pulse width modulation
Pulse generation (by T0/T1/T2/T3)
Buzzer
8-bit ×1-ch
Minimum instruction execution
time
125ns (@ 16MHz main clock)
Power down mode
STOP mode
IDLE mode

MC97F6108A User’s manual 1. Description
13
Table 1. MC97F6108A Device Features and Peripheral Counts (continued)
Peripherals
Description
General Purpose I/O (GPIO)
20 SOP Normal I/O : 18 ports
—P0[7:0], P1[7:0], P2[1:0]
16 SOPN Normal I/O : 14 ports
—P0[7:1], P1[7:3], P2[1:0]
Reset
Power on reset
Reset release level: 1.4V
Low voltage reset
Reset release level: 1.8V
Brown Out Detect
6 levels detect
2.2 / 2.5 /2.7 / 3.2 / 3.7 / 4.2V
Timer/counter
Basic interval timer (BIT) 8-bit x 1-ch.
Watchdog timer (WDT) 8-bit x 1-ch.
16-bit x 4-ch (T0/T1/T2/T3)
Comm.
function
USART
8-bit USART x 1-ch or 8-bit SPI x 1-ch
I2C
8-bit I2C x 1-ch
12-bit A/D Converter
8 input channels
Analog comparator
5 Comparators :
1 Comparator for Sync
1 Comparator for zero-cross
3 Comparator for protection
—Surge, IGBT over voltage, over current
Internal reference voltage for comparator
OP-AMP
2 OP-Amp 2stage amplifier
Programmable pulse generator
Pulse generation (by PPG based on 16bit timer)
1-ch output (PPG step < 0.1us)
Internal RC oscillator
INTRC 16MHz ±3.0% (TA=-40~ +85°C)
WDT Clock 8kHz ±50% (TA= -40~ +85°C)
Operating voltage
and frequency
2.7V to 5.5V @ 2MHz to 16.0MHz with internal RC
Operating temperature
-40℃to +85℃
Package
Pb-free packages
20 SOP
16 SOPN

1. Description MC97F6108A User’s manual
14
1.2 MC97F6108A block diagram
In this section, MC97F6108A device with peripherals are described in a block diagram.
IRAM
256 B
Flash
8 KB
On-chip debug
In-system programming
Power control
Power on reset,
Low voltage reset,
Brown out detector
Clock generator
16MHz, Internal RC OSC
8kHz, Internal WDT OSC
Voltage Down convertor
CORE
M8051
General purpose I/O
18 ports normal I/O
(with analog input)
Watchdog timer
1 channel, 8-bit
8kHz, internal WDT OSC
Basic interval timer
1 channel, 8-bit
Timer / Counter / PWM
4 channels, 16-bit
UART
1 channel, 8-bit
I2C
1 channel, 8-bit
Buzzer
1 channel, 8-bit
PPG
1 channel, 16-bit
Comparator
5 channels
OP-AMP
2 stage
ADC
8 input channels, 12-bit
XRAM
256 B
Figure 1. MC97F6108A Block Diagram

MC97F6108A User’s manual 2. Pinouts and pin description
15
2Pinouts and pin description
In this chapter, MC97F6108A device pinouts and pin descriptions are introduced.
2.1 Pinouts
MC97F6108AD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
RESETB/P00
DSDA/AN0/EC1/CMPXO/SCK/XCK/P01
DSCL/AN1/EINT0/SS/P02
AN2/EINT1/SDA/MISO/RXD/P03
AN3/EINT2/SCL/MOSI/TXD/P04
PPGO/PWM3O/T3O/P05
AN4/PWM1O/T1O/P06
TPPGO/BUZO/PWM0O/T0O/P07
AN6/PWM2O/T2O/EC0/P10
VSS
P21/AMP1I
P20/AN5/AMP2O
P17/AN7/AVREF/(AMP1O)
P16/CMP0_IN_N
P15/CMP0_IN_P
P14/CMP2_IN_P
P13/CMP1_IN_P
P12/DSDA1
P11/DSCL1
NOTES:
1. Monitor function: P01/CMPXO, P07/TPPGO
2. USART function: P01/XCK, P04/TXD, P03/RXD
3. SPI function: P02/SS, P04/MOSI, P03/MISO, P01/SCK (when USART is used as SPI mode)
4. I2C function: P03/SDA, P04/SCL
5. When using 16-pin products, it is recommended that configure internal pull-up to the floating pin in
order to prevent current consumption.
6. Programmer (E-PGM+, E-Gang4/6) uses P0[1:2] or P1[1:2] pin as DSCL/DSCL1, DSDA/DSDA1.
7. The second functions of DSDA and DSCL port are not supported in OCD mode. (EC1, XCK, EINT0).
Figure 2. MC97F6108A 20 SOP Pin Assignment

2. Pinouts and pin description MC97F6108A User’s manual
16
MC97F6108AM
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
DSDA/AN0/EC1/CMPXO/SCK/XCK/P01
DSCL/AN1/EINT0/SS/P02
AN2/EINT1/SDA/MISO/RXD/P03
AN3/EINT2/SCL/MOSI/TXD/P04
PPGO/PWM3O/T3O/P05
AN4/PWM1O/T1O/P06
TPPGO/BUZO/PWM0O/T0O/P07
VSS
P21/AMP1I
P20/AN5/AMP2O
P17/AN7/AVREF/(AMP1O)
P16/CMP0_IN_N
P15/CMP0_IN_P
P14/CMP2_IN_P
P13/CMP1_IN_P
NOTES:
1. Monitor function: P01/CMPXO, P07/TPPGO
2. USART function: P01/XCK, P04/TXD, P03/RXD
3. SPI function: P02/SS, P04/MOSI, P03/MISO, P01/SCK (when USART is used as SPI mode)
4. I2C function: P03/SDA, P04/SCL
5. When using 16-pin products, it is recommended that configure internal pull-up to the floating pin in
order to prevent current consumption.
6. Programmer (E-PGM+, E-Gang4/6) uses P0[1:2] pin as DSCL, DSDA.
7. The second functions of DSDA and DSCL port are not supported in OCD mode. (EC1, XCK, EINT0).
Figure 3. MC97F6108A 16 SOPN Pin Assignment

MC97F6108A User’s manual 2. Pinouts and pin description
17
2.2 Pin description
Table 2. Normal Pin Description
Pin no.
PIN Name
I/O(1)
Description
Remark
20 SOP
16 SOPN
2
-
P00*
IOUS
Port 0 bit 0 Input/output
RSTB
IU
Reset pin
Pull-up
3
2
P01*
IOUS
Port 0 bit 1 Input/output
XCK
IO
USART clock signal
EC1
I
Timer 1(Event Capture) input
AN0
IA
ADC input ch-0
DSDA
IOU
OCD debugger data input/output
Pull-up
4
3
P02*
IOUS
Port 0 bit 2 Input/output
EINT0
I
External interrupt input ch-0
AN1
IA
ADC input ch-1
DSCL
IOU
OCD debugger clock
Pull-up
5
4
P03*
IOUS
Port 0 bit 3 Input/output
RXD
I
USART data receive
SDA
IO
I2C data signal
EINT1
I
External interrupt input ch-1
AN2
IA
ADC input ch-2
6
5
P04*
IOUS
Port 0 bit 4 Input/output
TXD
O
USART data transmit/SPI MOSI
SCL
IO
I2C clock signal
EINT2
I
External interrupt input ch-2
AN3
IA
ADC input ch-3
7
6
P05*
IOUS
Port 0 bit 5 Input/output
T3O
O
Timer 3 interval output
PPGO
O
Program pulse generator output
8
7
P06*
IOUS
Port 0 bit 6 Input/output
T1O
O
Timer 1 interval output
AN4
IA
ADC input ch-4
9
8
P07*
IOUS
Port 0 bit 7 Input/output
T0O
O
Timer 0 interval output
BUZO
O
Buzzer Output
10
-
P10*
IOUS
Port 1 bit 0 Input/output
EC0
I
Timer/Event Counter 0 input

2. Pinouts and pin description MC97F6108A User’s manual
18
Table 2. Normal Pin Description (continued)
Pin no.
PIN Name
I/O(1)
Description
Remark
20 SOP
16 SOPN
10
-
T2O
O
Timer 2 interval output
AN6
IA
ADC input ch-6
11
-
P11*
IOUS
Port 1 bit 1 Input/output
DSCL1
IOU
OCD debugger clock
Pull-up
12
-
P12*
IOUS
Port 1 bit 2 Input/output
DSDA1
IOU
OCD debugger data input/output
Pull-up
13
9
P13*
IOUS
Port 1 bit 3 Input/output
CMP1_IN_P
IUS
Comparator1 input positive signal
14
10
P14*
IOUS
Port 1 bit 4 Input/output
CMP2_IN_P
IUS
Comparator2 input positive signal
15
11
P15*
IOUS
Port 1 bit 5 Input/output
CMP0_IN_P
IUS
Comparator0 input positive signal
16
12
P16*
IOUS
Port 1 bit 6 Input/output
CMP0_IN_N
IUS
Comparator0 input negative signal
17
13
P17*
IOUS
Port 1 bit 7 Input/output
AN7
IA
ADC input ch-7
AVREF
P
A/D converter reference voltage
(AMP1O)
O
OP-AMP 1 output
18
14
P20*
IOUS
Port 2 bit 0 Input/output
AN5
IA
ADC input ch-5
AMP2O
O
OP-AMP 2 output
19
15
P21*
IOUS
Port 2 bit 1 Input/output
AMP1I
I
OP-AMP 1 input
1
1
VDD
P
VDD
20
16
VSS
P
VSS
NOTES:
1. P00 and P10–P12 are not in the 16-pin package.
2. P00/RSTB pin is configured as one of the P00 and RESETB pin by the “CONFIGURE OPTION.”
3. If the P01/XCK/EC1/AN0/DSDA and P02/EINT0/AN1/DSCL pins are connected to the programmer
during power-on reset, the pins are automatically configured as In-system programming pins.
4. Or if the P11/DSCL1 and P12/DSDA1 pins are connected to the programmer during power-on reset, the
pins are automatically configured as In-system programming pins.
5. P01/XCK/EC1/AN0/DSDA, P02/EINT0/AN1/DSCL, P11/DSCL1 and P12/DSDA1 pins are only
configured as inputs with internal pull-up resistor during the reset or power-on reset.
(1) I=Input, O=Output, U=Pull-up, D=Pull-down, S=Schmitt-Trigger Input Type, C=CMOS Input Type,
A=Analog, P=Power
6. The * means ‘Selected pin function after reset condition.

MC97F6108A User’s manual 3. Port structures
19
3Port structures
In this chapter, two port structures are introduced in figures 1, 2 and 3 regarding general purpose I/O
port and external interrupt I/O port respectively.
DATA
REGISTER
DIRECTION
REGISTER
PORTx INPUT
PAD
VDDVDD
Schmitt Level
Input
Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V)
VDD
MUX
1
0
PULL-UP
REGISTER
VDD
OPEN-DRAIN
REGISTER
Figure 4. General Purpose I/O Port

3. Port structures MC97F6108A User’s manual
20
DATA
REGISTER
SUB-FUNC DATA OUTPUT
SUB-FUNC ENABLE
DIRECTION
REGISTER
SUB-FUNC DIRECTION
SUB-FUNC DATA INPUT
PORTx INPUT
PAD
VDDVDD
MUX
MUX
0
1
MUX
1
0
0
1
Schmitt Level
Input
VDD
Level Shift (1.8V to ExtVDD) Level Shift (ExtVDD to 1.8V)
OPEN-DRAIN
REGISTER
PULL-UP
REGISTER
VDD
* If one sub-function is selected, the direction of the sub-function is applied to the port automatically.
example)
EIENAB = 0x01 →P02 input mode
T3CR1 = 0x02 →P05 output mode
Figure 5. Secondary Function I/O Port