Intel BX80619I73960X User manual

Reference Number: 326196-002
Intel®Core™ i7 Processor Family for
the LGA-2011 Socket
Datasheet, Volume 1
Supporting Desktop Intel®Core™ i7-3960X and i7-3970X Extreme Edition
Processor for the LGA-2011 Socket
Supporting Desktop Intel®Core™ i7-39xxK and i7-38xx Processor Series
for the LGA-2011 Socket
This is volume 1 of 2.
November 2012

2Datasheet, Volume 1
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life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them. The information here is subject to change without notice. Do not finalize a design with this information.
The products described in this document may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
This document contains information on products in the design phase of development. The information here is subject to change
without notice. Do not finalize a design with this information.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Hyper-Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology
enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. For
more information including details on which processors support HT Technology, see
http://www.intel.com/products/ht/hyperthreading_more.htm.
Enhanced Intel SpeedStep® Technology - See the Processor Spec Finder or contact your Intel representative for more information.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting
operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
Intel®Virtualization Technology requires a computer system with an enabled Intel®processor, BIOS, virtual machine monitor
(VMM) and, for some uses, certain computer system software enabled for it. Functionality, performance or other benefits will vary
depending on hardware and software configurations and may require a BIOS update. Software applications may not be compatible
with all operating systems. Please check with your application vendor.
Intel®Turbo Boost Technology requires a PC with a processor with Intel Turbo Boost Technology capability. Intel Turbo Boost
Technology performance varies depending on hardware, software and overall system configuration. Check with your PC
manufacturer on whether your system delivers Intel Turbo Boost Technology. For more information, see
http://www.intel.com/technology/turboboost/.
Intel®Active Management Technology requires the platform to have an Intel®AMT-enabled chipset, network hardware and
software, connection with a power source and a network connection.
64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device
drivers and applications enabled for Intel®64 architecture. Performance will vary depending on your hardware and software
configurations. Consult with your system vendor for more information.
ΔIntel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor
family, not across different processor families. See http://www.intel.com/products/processor_number for details.
I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed
by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and
North American Philips Corporation.
Intel, Enhanced Intel SpeedStep Technology, Intel Core, and the Intel logo are trademarks of Intel Corporation in the U.S. and
other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2011, Intel Corporation. All rights reserved.

Datasheet, Volume 1 3
Table of Contents
1Introduction..............................................................................................................9
1.1 Processor Feature Details ................................................................................... 10
1.1.1 Supported Technologies .......................................................................... 10
1.2 Interfaces ........................................................................................................ 11
1.2.1 System Memory Support ......................................................................... 11
1.2.2 PCI Express* ......................................................................................... 11
1.2.3 Direct Media Interface Gen 2 (DMI2)......................................................... 13
1.2.4 Platform Environment Control Interface (PECI)........................................... 13
1.3 Power Management Support ............................................................................... 13
1.3.1 Processor Package and Core States........................................................... 13
1.3.2 System States Support ........................................................................... 13
1.3.3 Memory Controller.................................................................................. 13
1.3.4 PCI Express* ......................................................................................... 13
1.4 Thermal Management Support ............................................................................ 14
1.5 Package Summary............................................................................................. 14
1.6 Terminology ..................................................................................................... 14
1.7 Related Documents ........................................................................................... 16
2Interfaces................................................................................................................ 17
2.1 System Memory Interface .................................................................................. 17
2.1.1 System Memory Technology Support ........................................................ 17
2.1.2 System Memory Timing Support............................................................... 17
2.2 PCI Express* Interface....................................................................................... 17
2.2.1 PCI Express* Architecture ....................................................................... 17
2.2.1.1 Transaction Layer ..................................................................... 18
2.2.1.2 Data Link Layer ........................................................................ 18
2.2.1.3 Physical Layer .......................................................................... 19
2.2.2 PCI Express* Configuration Mechanism ..................................................... 19
2.3 DMI2/PCI Express* Interface .............................................................................. 19
2.3.1 DMI2 Error Flow ..................................................................................... 19
2.3.2 DMI2 Link Down..................................................................................... 20
2.4 Platform Environment Control Interface (PECI)...................................................... 20
3 Technologies ........................................................................................................... 21
3.1 Intel®Virtualization Technology (Intel®VT) ......................................................... 21
3.1.1 Intel®Virtualization Technology (Intel®VT) for Intel®64
and IA-32 Intel®Architecture (Intel®VT-x) Objectives ............................... 21
3.1.2 Intel®Virtualization Technology (Intel®VT) for Intel®64
and IA-32 Intel®Architecture (Intel®VT-x) Features .................................. 22
3.1.3 Intel®Virtualization Technology (Intel®VT) for
Directed I/O (Intel®VT-d) Objectives ....................................................... 22
3.1.3.1 Intel®Virtualization Technology (Intel®VT) for
Directed I/O (Intel®VT-d) Features Supported ............................. 23
3.1.3.2 Intel®Virtualization Technology (Intel®VT) for
Directed I/O (Intel®VT-d) Processor Feature Additions.................. 23
3.1.4 Intel®Virtualization Technology Processor Extensions ................................. 23
3.2 Security Technologies ........................................................................................ 24
3.2.1 Intel®AES New Instructions (Intel®AES-NI) ............................................. 24
3.2.2 Execute Disable Bit................................................................................. 24
3.3 Intel®Hyper-Threading Technology (Intel®HT Technology).................................... 24
3.4 Intel®Turbo Boost Technology ........................................................................... 25
3.4.1 Intel®Turbo Boost Operating Frequency ................................................... 25
3.5 Enhanced Intel®SpeedStep®Technology............................................................. 25
3.6 Intel®Advanced Vector Extensions (Intel®AVX) ................................................... 26

4Datasheet, Volume 1
4 Power Management .................................................................................................27
4.1 Advanced Configuration and Power Interface (ACPI) States Supported ......................27
4.1.1 System States........................................................................................27
4.1.2 Processor Package and Core States ...........................................................27
4.1.3 Integrated Memory Controller States .........................................................29
4.1.4 DMI2 / PCI Express* Link States...............................................................29
4.1.5 G, S, and C State Combinations................................................................30
4.2 Processor Core / Package Power Management .......................................................30
4.2.1 Enhanced Intel®SpeedStep®Technology ..................................................30
4.2.2 Low-Power Idle States.............................................................................31
4.2.3 Requesting Low-Power Idle States ............................................................32
4.2.4 Core C-states .........................................................................................32
4.2.4.1 Core C0 State ...........................................................................33
4.2.4.2 Core C1/C1E State ....................................................................33
4.2.4.3 Core C3 State ...........................................................................33
4.2.4.4 Core C6 State ...........................................................................33
4.2.4.5 Core C7 State ..........................................................................33
4.2.4.6 C-State Auto-Demotion .............................................................33
4.2.5 Package C-States ...................................................................................34
4.2.5.1 Package C0 ..............................................................................35
4.2.5.2 Package C1/C1E........................................................................35
4.2.5.3 Package C2 State ......................................................................36
4.2.5.4 Package C3 State ......................................................................36
4.2.5.5 Package C6 State ......................................................................36
4.2.6 Package C-State Power Specifications........................................................37
4.3 System Memory Power Management ....................................................................37
4.3.1 CKE Power-Down ....................................................................................37
4.3.2 Self Refresh ...........................................................................................38
4.3.2.1 Self Refresh Entry .....................................................................38
4.3.2.2 Self Refresh Exit .......................................................................38
4.3.2.3 DLL and PLL Shutdown...............................................................38
4.3.3 DRAM I/O Power Management ..................................................................38
4.4 DMI2 / PCI Express* Power Management ..............................................................38
5 Thermal Management Specifications ........................................................................39
6 Signal Descriptions ..................................................................................................41
6.1 System Memory Interface ...................................................................................41
6.2 PCI Express* Based Interface Signals ...................................................................42
6.3 DMI2 / PCI Express* Port 0 Signals ......................................................................44
6.4 Platform Environment Control Interface (PECI) Signal .............................................44
6.5 System Reference Clock Signals ..........................................................................44
6.6 JTAG and TAP Signals.........................................................................................45
6.7 Serial VID Interface (SVID) Signals ......................................................................45
6.8 Processor Asynchronous Sideband and Miscellaneous Signals...................................46
6.9 Processor Power and Ground Supplies ..................................................................48
7 Electrical Specifications ...........................................................................................49
7.1 Processor Signaling ............................................................................................49
7.1.1 System Memory Interface Signal Groups....................................................49
7.1.2 PCI Express* Signals...............................................................................49
7.1.3 DMI2/PCI Express* Signals ......................................................................49
7.1.4 Platform Environmental Control Interface (PECI) .........................................49
7.1.4.1 Input Device Hysteresis .............................................................50
7.1.5 System Reference Clocks (BCLK{0/1}_DP, BCLK{0/1}_DN) .........................50
7.1.5.1 PLL Power Supply ......................................................................50
7.1.6 JTAG and Test Access Port (TAP) Signals....................................................51
7.1.7 Processor Sideband Signals ......................................................................51
7.1.8 Power, Ground and Sense Signals .............................................................51

Datasheet, Volume 1 5
7.1.8.1 Power and Ground Lands ........................................................... 51
7.1.8.2 Decoupling Guidelines ............................................................... 52
7.1.8.3 Voltage Identification (VID)........................................................ 52
7.1.9 Reserved or Unused Signals..................................................................... 56
7.2 Signal Group Summary ...................................................................................... 56
7.3 Power-On Configuration (POC) Options................................................................. 59
7.4 Absolute Maximum and Minimum Ratings ............................................................. 60
7.4.1 Storage Conditions Specifications ............................................................. 60
7.5 DC Specifications .............................................................................................. 61
7.5.1 Voltage and Current Specifications............................................................ 61
7.5.2 Die Voltage Validation ............................................................................. 63
7.5.2.1 VCC Overshoot Specifications ...................................................... 63
7.5.3 Signal DC Specifications .......................................................................... 64
7.5.3.1 PCI Express* DC Specifications................................................... 69
7.5.3.2 DMI2 / PCI Express* DC Specifications ........................................ 69
7.5.3.3 Reset and Miscellaneous Signal DC Specifications .......................... 69
8 Processor Land Listing............................................................................................. 71
9 Package Mechanical Specifications ........................................................................ 119
Figures
1-1 Processor Platform Block Diagram Example........................................................... 10
1-2 PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2) .................. 12
2-1 PCI Express* Layering Diagram........................................................................... 18
2-2 Packet Flow through the Layers........................................................................... 18
4-1 Idle Power Management Breakdown of the Processor Cores..................................... 31
4-2 Thread and Core C-State Entry and Exit .............................................................. 31
4-3 Package C-State Entry and Exit ........................................................................... 35
7-1 Input Device Hysteresis ..................................................................................... 50
7-2 VR Power-State Transitions................................................................................. 54
7-3 VCC Overshoot Example Waveform ...................................................................... 63
Tables
1-1 Terminology ..................................................................................................... 14
1-2 Reference Documents ........................................................................................ 16
4-1 System States .................................................................................................. 27
4-2 Package C-State Support.................................................................................... 28
4-3 Core C-State Support......................................................................................... 28
4-4 System Memory Power States ............................................................................. 29
4-5 DMI2/PCI Express* Link States ........................................................................... 29
4-6 G, S, and C State Combinations .......................................................................... 30
4-7 P_LVLx to MWAIT Conversion ............................................................................. 32
4-8 Coordination of Core Power States at the Package Level ......................................... 35
4-9 Package C-State Power Specifications .................................................................. 37
6-1 Memory Channel DDR0, DDR1, DDR2, DDR3......................................................... 41
6-2 Memory Channel Miscellaneous ........................................................................... 42
6-3 PCI Express* Port 1 Signals ................................................................................ 42
6-4 PCI Express* Port 2 Signals ................................................................................ 43
6-5 PCI Express* Port 3 Signals ................................................................................ 43
6-6 PCI Express* Miscellaneous Signals ..................................................................... 44

6Datasheet, Volume 1
6-7 DMI2 to Port 0 Signals........................................................................................44
6-8 PECI Signals .....................................................................................................44
6-9 System Reference Clock (BCLK{0/1}) Signals........................................................44
6-10 JTAG and TAP Signals.........................................................................................45
6-11 SVID Signals .....................................................................................................45
6-12 Processor Asynchronous Sideband Signals.............................................................46
6-13 Miscellaneous Signals .........................................................................................47
6-14 Power and Ground Signals ..................................................................................48
7-1 Power and Ground Lands ....................................................................................51
7-2 SVID Address Usage ..........................................................................................54
7-3 Voltage Identification Definition ...........................................................................55
7-4 Signal Description Buffer Types ...........................................................................56
7-5 Signal Groups ...................................................................................................57
7-6 Signals with On-Die Termination ..........................................................................59
7-7 Power-On Configuration Option Lands...................................................................59
7-8 Processor Absolute Minimum and Maximum Ratings ...............................................60
7-9 Voltage Specification ..........................................................................................61
7-10 Current (Icc_Max and Icc_TDC) Specification.........................................................62
7-11 VCC Overshoot Specifications...............................................................................63
7-12 DDR3 Signal DC Specifications.............................................................................64
7-13 PECI DC Specifications .......................................................................................65
7-14 System Reference Clock (BCLK{0/1}) DC Specifications..........................................66
7-15 SMBus DC Specifications.....................................................................................66
7-16 JTAG and TAP Signals DC Specifications................................................................67
7-17 Serial VID Interface (SVID) DC Specifications ........................................................67
7-18 Processor Asynchronous Sideband DC Specifications...............................................68
7-19 Miscellaneous Signals DC Specifications ................................................................69
8-1 Land Name .......................................................................................................72
8-2 Land Number ....................................................................................................95

Datasheet, Volume 1 7
Revision History
§
Revision
Number Description Revision Date
001 • Initial Release November 2011
002 • Updated to clarify references to PCI Express*
•AddedIntel
®Core™ i7-3970X Processor Extreme Edition November 2012

8Datasheet, Volume 1

Datasheet, Volume 1 9
Introduction
1Introduction
The Intel®Core™ i7 processor family for the LGA-2011 socket is the next generation of
64-bit, multi-core desktop processor built on 32-nanometer process technology. Based
on the low-power/high performance Intel®Core™ i7 processor microarchitecture, the
processor is designed for a two-chip platform as opposed to the traditional three-chip
platforms (processor, MCH, and ICH). The two-chip platform consists of a processor
and the Platform Controller Hub (PCH) and enables higher performance, easier
validation, and improved x-y footprint. Refer to Figure 1-1 for a block diagram of the
processor platform.
The processor features up to 40 lanes of PCI Express* links capable of up to 8.0 GT/s,
and 4 lanes of DMI2/PCI Express* 2.0 interface with a peak transfer rate of 5.0 GT/s.
The processor supports up to 46 bits of physical address space and 48 bits of virtual
address space.
Included in this family of processors is an integrated memory controller (IMC) and
integrated I/O (IIO) (such as PCI Express* and DMI2) on a single silicon die. This single
die solution is known as a monolithic processor.
This document is Volume 1 of the datasheet for the Intel®Core™ i7 processor family
for the LGA-2011 socket. The complete datasheet consists of two volumes. This
document provides DC electrical specifications, land and signal definitions, interface
functional descriptions, power management descriptions, and additional feature
information pertinent to the implementation and operation of the processor on its
platform. Volume 2 provides register information. Refer to Section 1.7, “Related
Documents” for access to Volume 2.
Note: Throughout this document, the Intel®Core™ i7 processor family for the LGA-2011
socket may be referred to as “processor”.
Note: Throughout this document, the Desktop Intel®Core™ i7-39xxK processor series for the
LGA-2011 socket refers to the i7-3930K.
Note: Throughout this document, the Desktop Intel®Core™ i7-38xx processor series for the
LGA-2011 socket refers to the i7-3820.
Note: Throughout this document, the Intel®X79 Chipset Platform Controller Hub may be
referred to as “PCH”.

Introduction
10 Datasheet, Volume 1
1.1 Processor Feature Details
• Up to 6 Execution Cores
• Each core supports two threads (Intel®Hyper-Threading Technology) for up to
12 threads
• A 32-KB instruction and 32-KB data first-level cache (L1) for each core
• A 256-KB shared instruction/data mid-level (L2) cache for each core
• Up to 15 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level
cache (LLC), shared among all cores
1.1.1 Supported Technologies
•Intel
®Virtualization Technology (Intel®VT)
•Intel
®Virtualization Technology for Directed I/O (Intel®VT-d)
•Intel
®Virtualization Technology Intel®Core™ i7 processor family for the LGA-2011
socket Extensions
•Intel
®64 Architecture
•Intel
®Streaming SIMD Extensions 4.1 (Intel®SSE4.1)
•Intel
®Streaming SIMD Extensions 4.2 (Intel®SSE4.2)
•Intel
®Advanced Vector Extensions (Intel®AVX)
•Intel
®Hyper-Threading Technology (Intel®HT Technology)
• Execute Disable Bit
•Intel
®Turbo Boost Technology
• Enhanced Intel®SpeedStep®Technology
Figure 1-1. Processor Platform Block Diagram Example
Processor
DDR3 DDR3 DDR3 DDR3
PCH DMI2
PCIe*
PCIe*
...
SATA
ethernet
BIOS
x4
x1
PCIe*
x16
PCIe*
x8
PCIe*
x16
SCU Uplink
Note: if SCU Uplink is used,
the x8 PCIe* device shown is
limited to x4.

Datasheet, Volume 1 11
Introduction
1.2 Interfaces
1.2.1 System Memory Support
• The processor supports 4 DDR3 channels with 1 unbuffered DIMM per channel
• Unbuffered DDR3 DIMMs supported
• Data burst length of eight cycles for all memory organization modes
• Memory DDR3 data transfer rates of 1066, 1333, and 1600 MT/s
• DDR3 UDIMM standard I/O Voltage of 1.5 V
• 1-Gb, 2-Gb, and 4-Gb DDR3 DRAM technologies supported for these devices:
— UDIMMs x8, x16
• Up to 2 ranks supported per memory channel, 1 or 2 ranks per DIMM
• Open with adaptive idle page close timer or closed page policy
• Command launch modes of 1n/2n
• Improved Thermal Throttling with dynamic CLTT
• Memory thermal monitoring support for DIMM temperature using two memory
signals, MEM_HOT
1.2.2 PCI Express*
• Support for PCI Express* 2.0 (5.0 GT/s), PCI Express* (2.5 GT/s), and capable of
up to PCI Express* 8.0 GT/s.
• Up to 40 lanes of PCI Express* interconnect for general purpose PCI Express
devices capable of up to 8.0 GT/s speeds that are configurable for up to 10
independent ports.
• Negotiating down to narrower widths is supported, see Figure 1-2
— x16 port (Port 2 & Port 3) may negotiate down to x8, x4, x2, or x1
— x8 port (Port 1) may negotiate down to x4, x2, or x1
— x4 port (Port 0) may negotiate down to x2, or x1
— When negotiating down to narrower widths, there are caveats as to how lane
reversal is supported
• Address Translation Services (ATS) 1.0 support
• Hierarchical PCI-compliant configuration mechanism for downstream devices
• Traditional PCI style traffic (asynchronous snooped, PCI ordering)
• PCI Express* extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
• PCI Express* Enhanced Access Mechanism. Accessing the device configuration
space in a flat memory mapped fashion.

Introduction
12 Datasheet, Volume 1
• Supports receiving and decoding 64 bits of address from PCI Express*
— Memory transactions received from PCI Express* that go above the top of
physical address space (when Intel VT-d is enabled, the check would be against
the translated HPA (Host Physical Address) address) are reported as errors by
the processor.
— Outbound access to PCI Express* will always have address bits 63 to 46 cleared
• Re-issues Configuration cycles that have been previously completed with the
Configuration Retry status
• Power Management Event (PME) functions
• Message Signaled Interrupt (MSI and MSI-X) messages
• Degraded Mode support and Lane Reversal support
• Static lane numbering reversal and polarity inversion support
Figure 1-2. PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2)
Transaction
Link
Physical
0…3
X4
DMI
Port 0
DMI
4…7
X4
Port 1b
Transaction
Link
Physical
0…3
X4
Port 1a
Port 1
(IOU2)
PCIe
X8
Por t 1a
8…11
Transaction
Link
Physical
0…3
Port 2
(IOU0)
PCIe
X4
Por t 2b
X4
Port 2a
X8
Port 2a
X4
Port 2d
X4
Port 2c
X8
Port 2c
X16
Port 2a
12..154…7 8…11
Transaction
Link
Physical
0…3
Port 3
(IOU1)
PCIe
X4
Port 3b
X4
Port 3a
X8
Port 3a
X4
Port 3d
X4
Port 3c
X8
Port 3c
X16
Port 3a
12..154…7
Transaction
Link
Physical
0…3
X4
DMI
Port 0
DMI
4…7
X4
Port 1b
Transaction
Link
Physical
0…3
X4
Port 1a
Port 1
(IOU2)
PCIe
X8
Por t 1a
8…11
Transaction
Link
Physical
0…3
Port 2
(IOU0)
PCIe
X4
Por t 2b
X4
Port 2a
X8
Port 2a
X4
Port 2d
X4
Port 2c
X8
Port 2c
X16
Port 2a
12..154…7 8…11
Transaction
Link
Physical
0…3
Port 2
(IOU0)
PCIe
X4
Por t 2b
X4
Port 2a
X8
Port 2a
X4
Port 2d
X4
Port 2c
X8
Port 2c
X16
Port 2a
12..154…7 8…11
Transaction
Link
Physical
0…3
Port 3
(IOU1)
PCIe
X4
Port 3b
X4
Port 3a
X8
Port 3a
X4
Port 3d
X4
Port 3c
X8
Port 3c
X16
Port 3a
12..154…7 8…11
Transaction
Link
Physical
0…3
Port 3
(IOU1)
PCIe
X4
Port 3b
X4
Port 3a
X8
Port 3a
X4
Port 3d
X4
Port 3c
X8
Port 3c
X16
Port 3a
12..154…7

Datasheet, Volume 1 13
Introduction
1.2.3 Direct Media Interface Gen 2 (DMI2)
• Serves as the chip-to-chip interface to the PCH
• The DMI2 port supports x4 link width and only operates in a x4 mode when in DMI2
• Operates at PCIe2 or PCIe1 speeds
• Transparent to software
• Processor and peer-to-peer writes and reads with 64-bit address support
• APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined “End of
Interrupt” broadcast message when initiated by the processor.
• System Management Interrupt (SMI), SCI, and SERR error indication
• Static lane numbering reversal support
• Supports DMI2 virtual channels VC0, VC1, VCm, and VCp
1.2.4 Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (the processor) and a PECI master (the PCH). Refer to the processor
Thermal Mechanical Specification and Design Guide (see Section 1.7, “Related
Documents”)for additional details on PECI services available in the processor.
• Supports operation at up to 2 Mbps data transfers
• Link layer improvements to support additional services and higher efficiency over
PECI 2.0 generation
• Services include processor thermal and estimated power information, control
functions for power limiting, P-state and T-state control, and access for Machine
Check Architecture registers and PCI configuration space (both within the processor
package and downstream devices)
• Single domain (Domain 0) is supported
1.3 Power Management Support
1.3.1 Processor Package and Core States
• ACPI C-states as implemented by the following processor C-states
— Package: PC0, PC1/PC1E, PC2, PC3, PC6 (Package C7 is not supported)
— Core: CC0, CC1, CC1E, CC3, CC6, CC7
• Enhanced Intel SpeedStep®Technolog y
1.3.2 System States Support
• S0, S1, S3, S4, S5
1.3.3 Memory Controller
• Multiple CKE power down modes
• Multiple self-refresh modes
• Memory thermal monitoring using MEM_HOT_C01_N and MEM_HOT_C23_N Signals
1.3.4 PCI Express*
• L0s and L1 ASPM power management capability

Introduction
14 Datasheet, Volume 1
1.4 Thermal Management Support
• Adaptive Thermal Monitor
• THERMTRIP_N and PROCHOT_N signal support
• On-Demand mode clock modulation
• Open Loop Thermal Throttling and Hybrid OLTT/CLTT support for system memory
• Fan speed control with DTS
• Two integrated SMBus masters for accessing thermal data from DIMMs
• New Memory Thermal Throttling features using MEM_HOT signals
1.5 Package Summary
The processor socket type is noted as LGA2011. The processor package is a 52.5 x
45 mm FC-LGA package (LGA2011). Refer to the processor Thermal Mechanical
Specification and Design Guide (see Section 1.7, “Related Documents”) for the package
mechanical specifications.
1.6 Terminology
Table 1-1. Terminology (Sheet 1 of 3)
Term Description
ASPM Active State Power Management
Cbo Cache and Core Box. It is a term used for internal logic providing ring interface to
LLC and Core.
DDR3 Third generation Double Data Rate SDRAM memory technology that is the successor to
DDR2 SDRAM
DMA Direct Memory Access
DMI Direct Media Interface
DMI2 Direct Media Interface Gen 2
DTS Digital Thermal Sensor
ECC Error Correction Code
Enhanced Intel®
SpeedStep®Tech no log y
Allows the operating system to reduce power consumption when performance is not
needed.
Execute Disable Bit
The Execute Disable bit allows memory to be marked as executable or non-executable,
when combined with a supporting operating system. If code attempts to run in non-
executable memory the processor raises an error to the operating system. This feature
can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities
and can thus help improve the overall security of the system. See the Intel®64 and IA-32
Architectures Software Developer's Manuals for more detailed information.
Functional Operation Refers to the normal operating conditions in which all processor specifications, including
DC, AC, system bus, signal quality, mechanical, and thermal, are satisfied.
Integrated Memory
Controller (IMC)
A Memory Controller that is integrated in the processor die.
Integrated I/O
Controller (IIO)
An I/O controller that is integrated in the processor die.
Intel®64 Technology
64-bit memory extensions to the IA-32 architecture. Further details on Intel 64
architecture and programming model can be found at
http://developer.intel.com/technology/intel64/.
Intel®Turbo Boost
Tech nology
Intel®Turbo Boost Technology is a way to automatically run the processor core faster
than the marked frequency if the part is operating under power, temperature, and current
specifications limits of the Thermal Design Power (TDP). This results in increased
performance of both single and multi-threaded applications.

Datasheet, Volume 1 15
Introduction
Intel®Virtualization
Technology (Intel®VT)
Processor virtualization which when used in conjunction with Virtual Machine Monitor
software enables multiple, robust independent software environments inside a single
platform.
Intel®VT-d
Intel®Virtualization Technology (Intel®VT) for Directed I/O. Intel VT-d is a hardware
assist, under system software (Virtual Machine Manager or OS) control, for enabling I/O
device virtualization. Intel VT-d also brings robust security by providing protection from
errant DMAs by using DMA remapping, a key feature of Intel VT-d.
Integrated Heat
Spreader (IHS)
A component of the processor package used to enhance the thermal performance of the
package. Component thermal solutions interface with the processor at the IHS surface.
Jitter Any timing variation of a transition edge or edges from the defined Unit Interval (UI).
IOV I/O Virtualization
LGA2011 Socket The 2011-land FC-LGA package mates with the system board through this surface mount,
2011-contact socket.
LLC Last Level Cache
ME Management Engine
NCTF
Non-Critical to Function: NCTF locations are typically redundant ground or non-critical
reserved, so the loss of the solder joint continuity at end of life conditions will not affect
the overall product functionality.
Intel®Core™ i7
processor family for the
LGA-2011 socket
Intel’s 32-nm processor design, follow-on to the 32-nm 2nd Generation Intel®Core™
processor family desktop design.
PCH
Platform Controller Hub. The next generation chipset with centralized platform capabilities
including the main I/O interfaces along with display connectivity, audio features, power
management, manageability, security and storage features.
PCU Power Control Unit.
PCIe* PCI Express*
PECI Platform Environment Control Interface
Processor The 64-bit, single-core or multi-core component (package)
Processor Core
The term “processor core” refers to Si die itself which can contain multiple execution
cores. Each execution core has an instruction cache, data cache, and 256-KB L2 cache. All
execution cores share the L3 cache. All DC and AC timing and signal integrity
specifications are measured at the processor die (pads), unless otherwise noted.
PCU Uncore Power Manager
Rank A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC. These
devices are usually, but not always, mounted on a single side of a DDR3 DIMM.
SCI System Control Interrupt. Used in ACPI protocol.
SSE Intel®Streaming SIMD Extensions (Intel®SSE)
SKU A processor Stock Keeping Unit (SKU) to be installed in the platform. Electrical, power and
thermal specifications for these SKU’s are based on specific use condition assumptions.
SMBus
System Management Bus. A two-wire interface through which simple system and power
management related devices can communicate with the rest of the system. It is based on
the principals of the operation of the I2C* two-wire serial bus from Philips Semiconductor.
Storage Conditions
A non-operational state. The processor may be installed in a platform, in a tray, or loose.
Processors may be sealed in packaging or exposed to free air. Under these conditions,
processor landings should not be connected to any supply voltages, have any I/Os biased
or receive any clocks. Upon exposure to “free air” (that is, unsealed packaging or a device
removed from packaging material) the processor must be handled in accordance with
moisture sensitivity labeling (MSL) as indicated on the packaging material.
TAC Thermal Averaging Constant
TDP Thermal Design Power
TSOD Thermal Sensor on DIMM
UDIMM Unbuffered Dual In-line Module
Table 1-1. Terminology (Sheet 2 of 3)
Term Description

Introduction
16 Datasheet, Volume 1
1.7 Related Documents
Refer to the following documents for additional information.
§
Unit Interval
Signaling convention that is binary and unidirectional. In this binary signaling, one bit is
sent for every edge of the forwarded clock, whether it be a rising edge or a falling edge. If
a number of edges are collected at instances t1, t2, tn,...., tkthen the UI at instance “n” is
defined as:
UI n= t n– t n– 1
VCC Processor core power supply
VSS Processor ground
VCCD_01, VCCD_23 Power supply for the processor system memory interface. VCCD is the generic term for
VCCD_01, VCCD_23.
x1 Refers to a Link or Port with one Physical Lane
x4 Refers to a Link or Port with four Physical Lanes
x8 Refers to a Link or Port with eight Physical Lanes
x16 Refers to a Link or Port with sixteen Physical Lanes
Table 1-1. Terminology (Sheet 3 of 3)
Term Description
Table 1-2. Reference Documents
Document Document Number/
Location
Intel®Core™ i7 Processor Family for the LGA-2011 Socket Datasheet, Volume 2 326197
Intel®Core™ i7 Processor Family for the LGA-2011 Socket Specification Update 326198
Desktop Intel®Core™ i7 Processor Family for the LGA-2011 Socket Thermal
Mechanical Specifications and Design Guide 326199
Intel®X79 Express Chipset Datasheet 326200
Intel®X79 Express Chipset Specification Update 326201
Intel®X79 Express Chipset Thermal Mechanical Specifications and Design Guide 326202
Advanced Configuration and Power Interface Specification 3.0 http://www.acpi.info
PCI Local Bus Specification http://www.pcisig.com/
specifications
PCI Express* Base Specification http://www.pcisig.com
System Management Bus (SMBus) Specification http://smbus.org/
DDR3 SDRAM Specification http://www.jedec.org
Intel®64 and IA-32 Architectures Software Developer's Manuals
• Volume 1: Basic Architecture
• Volume 2A: Instruction Set Reference, A-M
• Volume 2B: Instruction Set Reference, N-Z
• Volume 3A: System Programming Guide
• Volume 3B: System Programming Guide
Intel®64 and IA-32 Architectures Optimization Reference Manual
http://www.intel.com/p
roducts/processor/man
uals/index.htm
Intel®Virtualization Technology Specification for Directed I/O Architecture
Specification
http://download.intel.co
m/technology/computin
g/vptech/Intel(r)_VT_fo
r_Direct_IO.pdf

Datasheet, Volume 1 17
Interfaces
2Interfaces
This chapter describes the functional behaviors supported by the processor.
2.1 System Memory Interface
2.1.1 System Memory Technology Support
The Integrated Memory Controller (IMC) supports DDR3 protocols with four
independent 64-bit memory channels and supports 1 unbuffered DIMM per channel.
2.1.2 System Memory Timing Support
The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
• tCL = CAS Latency
• tRCD = Activate Command to READ or WRITE Command delay
• tRP = PRECHARGE Command Period
• CWL = CAS Write Latency
• Command Signal modes = 1n indicates a new command may be issued every clock
and 2n indicates a new command may be issued every 2 clocks. Command launch
mode programming depends on the transfer rate and memory configuration.
2.2 PCI Express* Interface
This section describes the PCI Express* interface capabilities of the processor. See the
PCI Express* Base Specification for details of PCI Express*.
Note: The processor is capable of up to 8.0 GT/s speeds.
2.2.1 PCI Express* Architecture
Compatibility with the PCI addressing model is maintained to ensure that all existing
applications and drivers operate unchanged. The PCI Express configuration uses
standard mechanisms as defined in the PCI Plug-and-Play specification.
The PCI Express architecture is specified in three layers — Transaction Layer, Data Link
Layer, and Physical Layer. The partitioning in the component is not necessarily along
these same boundaries. Refer to Figure 2-1 for the PCI Express Layering Diagram.

Interfaces
18 Datasheet, Volume 1
PCI Express uses packets to communicate information between components. Packets
are formed in the Transaction and Data Link Layers to carry the information from the
transmitting component to the receiving component. As the transmitted packets flow
through the other layers, they are extended with additional information necessary to
handle packets at those layers. At the receiving side, the reverse process occurs and
packets get transformed from their Physical Layer representation to the Data Link
Layer representation and finally (for Transaction Layer Packets) to the form that can be
processed by the Transaction Layer of the receiving device.
2.2.1.1 Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The
Transaction Layer's primary responsibility is the assembly and disassembly of
Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as
read and write, as well as certain types of events. The Transaction Layer also manages
flow control of TLPs.
2.2.1.2 Data Link Layer
The middle layer in the PCI Express stack, the Data Link Layer, serves as an
intermediate stage between the Transaction Layer and the Physical Layer.
Responsibilities of Data Link Layer include link management, error detection, and error
correction.
Figure 2-1. PCI Express* Layering Diagram
Transaction
Data Link
Physical
Logical Sub-Block
Electrical Sub-Block
RX TX
Transaction
Data Link
Physical
Logical Sub-Block
Electrical Sub-Block
RX TX
Transaction
Data Link
Physical
Logical Sub-Block
Electrical Sub-Block
RX TX
Transaction
Data Link
Physical
Logical Sub-Block
Electrical Sub-Block
RX TX
Figure 2-2. Packet Flow through the Layers
Framing Sequence
Number Header Date LCRCECRC Framing
Data Link Layer
Transaction Layer
Physical Layer
Framing Sequence
Number Header Date LCRCECRC Framing
Data Link Layer
Transaction Layer
Physical Layer

Datasheet, Volume 1 19
Interfaces
The transmission side of the Data Link Layer accepts TLPs assembled by the
Transaction Layer, calculates and applies data protection code and TLP sequence
number, and submits them to Physical Layer for transmission across the Link. The
receiving Data Link Layer is responsible for checking the integrity of received TLPs and
for submitting them to the Transaction Layer for further processing. On detection of TLP
error(s), this layer is responsible for requesting retransmission of TLPs until information
is correctly received, or the Link is determined to have failed. The Data Link Layer also
generates and consumes packets which are used for Link management functions.
2.2.1.3 Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance
matching circuitry. It also includes logical functions related to interface initialization and
maintenance. The Physical Layer exchanges data with the Data Link Layer in an
implementation-specific format, and is responsible for converting this to an appropriate
serialized format and transmitting it across the PCI Express Link at a frequency and
width compatible with the remote device.
2.2.2 PCI Express* Configuration Mechanism
The PCI Express link is mapped through a PCI-to-PCI bridge structure.
PCI Express extends the configuration space to 4096 bytes per-device/function, as
compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express
configuration space is divided into a PCI-compatible region (which consists of the first
256 bytes of a logical device's configuration space) and an extended PCI Express region
(which consists of the remaining configuration space). The PCI-compatible region can
be accessed using either the mechanisms defined in the PCI specification or using the
enhanced PCI Express configuration access mechanism described in the PCI Express
Enhanced Configuration Mechanism section.
The PCI Express Host Bridge is required to translate the memory-mapped PCI Express
configuration space accesses from the host processor to PCI Express configuration
cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is
recommended that system software access the enhanced configuration space using
32-bit operations (32-bit aligned) only.
See the PCI Express* Base Specification for details of both the PCI-compatible and PCI
Express Enhanced configuration mechanisms and transaction rules.
2.3 DMI2/PCI Express* Interface
Direct Media Interface 2 (DMI2) connects the processor to the Platform Controller Hub
(PCH). DMI2 is similar to a four-lane PCI Express supporting a speed of 5 GT/s per
lane. Refer to Section 6.3, “DMI2 / PCI Express* Port 0 Signals” for additional details.
Note: Only DMI2 x4 configuration is supported.
2.3.1 DMI2 Error Flow
DMI2 can only generate SERR in response to errors; never SCI, SMI, MSI, PCI INT, or
GPE. Any DMI2 related SERR activity is associated with Device 0.

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20 Datasheet, Volume 1
2.3.2 DMI2 Link Down
The DMI2 link going down is a fatal, unrecoverable error. If the DMI2 data link goes to
data link down, after the link was up, then the DMI2 link hangs the system by not
allowing the link to retrain to prevent data corruption. This is controlled by the PCH.
Downstream transactions that had been successfully transmitted across the link prior
to the link going down may be processed as normal. No completions from downstream,
non-posted transactions are returned upstream over the DMI2 link after a link down
event.
2.4 Platform Environment Control Interface (PECI)
The Platform Environment Control Interface (PECI) uses a single wire for self-clocking
and data transfer. The bus requires no additional control lines. The physical layer is a
self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle
level near zero volts. The duration of the signal driven high depends on whether the bit
value is a logic ‘0’ or logic ‘1’. PECI also includes variable data transfer rate established
with every message. In this way, it is highly flexible even though underlying logic is
simple.
The interface design was optimized for interfacing to Intel processor and chipset
components in both single processor and multiple processor environments. The single
wire interface provides low board routing overhead for the multiple load connections in
the congested routing area near the processor and chipset components. Bus speed,
error checking, and low protocol overhead provides adequate link bandwidth and
reliability to transfer critical device operating conditions and configuration information.
Refer to the processor Thermal Mechanical Specification and Design Guide (see
Section 1.7, “Related Documents”)for additional details regarding PECI and for a list of
supported PECI commands.
§