Intel 6300ESB ICH User manual

Reference Number: 300281-003
Intel®Xeon™ Processor with 800
MHz System Bus, Intel®E7520
Chipset, and Intel®6300ESB ICH
Development Kit
User’s Manual
September 2004

2Intel®Xeon™ Processor, Intel®E7520 Chipset, Intel®6300ESB ICH Development Kit User’s Manual
Contents
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Intel®Xeon™ Processor, Intel®E7520 Chipset, Intel®6300ESB ICH Development Kit User’s Manual 3
Contents
Contents
1 Product Overview ............................................................................................................................7
1.1 Related Documents..............................................................................................................7
1.2 Product Contents..................................................................................................................7
1.3 Products Feature List............................................................................................................8
1.4 Block Diagram ......................................................................................................................9
1.4.1 Memory Subsystem...............................................................................................11
1.4.2 DIMM Placement DDR2 400..................................................................................11
1.5 Memory Population Rules and Configurations ...................................................................12
2 Platform Management...................................................................................................................13
2.1 Power Button......................................................................................................................13
2.2 Soft Off................................................................................................................................13
2.3 Sleep States Supported......................................................................................................13
2.3.1 S0 State.................................................................................................................13
2.3.2 S1 State.................................................................................................................14
2.3.3 S2 State.................................................................................................................14
2.3.4 S3 State.................................................................................................................14
2.3.5 S4 State.................................................................................................................14
2.3.6 S5 State.................................................................................................................15
2.3.7 Wake-Up Events....................................................................................................15
2.3.8 Wake-Up from S1 Sleep State...............................................................................15
2.3.9 Wake-Up from S4 and S5 States...........................................................................15
2.4 PCI PM Support..................................................................................................................15
2.5 Platform Management ........................................................................................................15
2.5.1 Processor Thermal Management...........................................................................16
2.6 System Fan Operation........................................................................................................16
3 Equipment Required for CRB Usage.............................................................................................17
3.1 Precautions.........................................................................................................................17
3.2 Driver and OS Requirements..............................................................................................18
3.2.1 Drivers included on CD..........................................................................................18
4 Jumpers and Headers...................................................................................................................21
4.1 Jumpers..............................................................................................................................21
5 System Overview...........................................................................................................................25
5.1 Power Diagrams.................................................................................................................25
5.2 Platform Clocking................................................................................................................26
5.3 Platform Resets ..................................................................................................................27
5.4 SMBus ................................................................................................................................28
5.5 Platform IRQ Routing..........................................................................................................29
5.6 VRD VID Headers...............................................................................................................30
5.7 Miscellaneous Buttons........................................................................................................32
6 Debug Procedure ..........................................................................................................................33
6.1 Level 1 Debug (Port 80/BIOS)............................................................................................33
6.2 Level 2 Debug (Power Sequence)......................................................................................34

4Intel®Xeon™ Processor, Intel®E7520 Chipset, Intel®6300ESB ICH Development Kit User’s Manual
Contents
6.3 Level 3 Debug (Voltage References)..................................................................................34
7 Heatsink Assembly........................................................................................................................35
7.1 Processor Heat Sink Installation Instructions .....................................................................36

Intel®Xeon™ Processor, Intel®E7520 Chipset, Intel®6300ESB ICH Development Kit User’s Manual 5
Contents
Figures
1Intel
®Xeon™ Processor with 800 MHz System Bus and Intel®E7520 and Intel®
6300ESB Customer Reference Board Block Diagram .................................................................9
2 Placement - Top View.................................................................................................................10
3 DDR2 400 Memory - DIMM Ordering.........................................................................................12
4Intel
®Xeon™ Processor with 800 MHz System Bus and Intel®E7520 and Intel®
6300ESB Customer Reference Board Jumper...........................................................................21
5 Power Distribution Block Diagram..............................................................................................25
6 Clock Block Diagram ..................................................................................................................26
7 Platform Reset Diagram .............................................................................................................27
8 SMBus Block Diagram................................................................................................................28
9 IRQ Routing Diagram .................................................................................................................29
10 Power Buttons ............................................................................................................................32
11 Components Requiring Heat Sink Assembly..............................................................................35
12 Inserting Processor in Socket.....................................................................................................36
13 Cleaning the Processor Surface.................................................................................................36
14 Installing the Processor Backplate..............................................................................................37
15 Removing the Protective Covers................................................................................................37
16 Installing the Heatsink.................................................................................................................38
Tables
1 Related Documents......................................................................................................................7
2 Supported DIMM Module Types.................................................................................................11
3 DIMM Placement DDR2 400 ......................................................................................................11
4 Jumper Settings..........................................................................................................................22
5 Processor VRD Settings.............................................................................................................30
6 Level 1 Debug (Port 80/BIOS)....................................................................................................33
7 Level 2 Debug (Power Sequence)..............................................................................................34
8 Level 3 Debug (Voltage References)..........................................................................................34
9 Components Requiring Heat Sink Assembly..............................................................................35

6Intel®Xeon™ Processor, Intel®E7520 Chipset, Intel®6300ESB ICH Development Kit User’s Manual
Contents
Revision History
Date Revision Description
August 2004 003 Changed figures that referenced PCI-X to PCI-X 133 MHz;
changed jumpers on Figure 4; made other miscellaneous
changes.
July 2004 002 Changed code names to public names; clarified illustrations.
December 2003 001 Initial release of this document.

Intel®Xeon™ Processor, Intel®E7520 Chipset, Intel®6300ESB ICH Development Kit User’s Manual 7
Product Overview
Product Overview 1
The Intel®Xeon™ Processor with 800 MHz System Bus, Intel®E7520 Chipset, and Intel®
6300ESB ICH Development Kit comprise an IA-32 based dual-processor platform. This platform
serves as a reference for OEMs development platform. This and other development kits from Intel
provide a fully working product with range of performance options which can be modified or used
immediately for product development.
1.1 Related Documents
Visit http://www.intel.com/platforms/applied/eiacomm/reference_configs.htm for latest updates.
1.2 Product Contents
The Reference Board is shipped with the following components and features:
•Two Intel®Xeon™ processors (2.8 GHz and 3.2 GHz) capable of 800 MT/s
•One 550 W SSI EPS12V power supply
•Two Heat sinks for the two processors
•Two pieces of DDR2 400 [256 Mbytes]
•Blank Hard drive
•CD with necessary drivers
— Red Hat 8.0 Compatible Driver Package Contents
— Red-Hat Advanced Server 2.1 Compatible Driver Package Contents
— Windows* Compatible Driver Package Contents
— ATI Rage* Mobility-M Graphics Accelerator
Table 1. Related Documents
Document/Reference Title Source/Document Number
Intel®E7520 Memory Controller Hub (MCH) Datasheet
Contact your Intel Sales
Representative for access
Intel®E7520 Memory Controller Hub (MCH) Specification Update
Intel®Xeon™ Processor with 800 MHz System Bus Datasheet
Intel 6300ESB I/O Controller Datasheet
Intel®Xeon™ Processor Debug Port Design Guide
Extended Debug Port Design Guide: for UP and DP platforms
Schematics file

8Intel®Xeon™ Processor, Intel®E7520 Chipset, Intel®6300ESB ICH Development Kit User’s Manual
Product Overview
1.3 Products Feature List
•Processor Support
—DualIntel
®Xeon™ Processors
— On-board processor voltage regulators compatible with VRM/EVRD 10.1 Design Guide
•Clocking
— CK409B clock synthesizer that generates all host clock and the PCI Express* interface
clock for the MCH PHY Layer
— DB800 generates the PCI Express differential pair clocks to the onboard PCI Express
components and the dedicated PCI Express slots
•Memory Support
— Registered, ECC, DDR2 400
— Each of the two memory channels on the Intel®E7520 in this CRB supports a maximum
of two DDR2 400 DIMMs per channel
— The maximum supported DDR2 400 memory configuration is 8 Gbyte using different
combinations of single and dual ranked, x4, 1 Gbyte technology DIMMs (limit of up to
four ranks per channel)
— 3.2 Gbytes/s bus per channel bandwidth with DDR2 400
•I/O slot support
— One PCI-X 133 MHz slot from PXH
— Two PCI-X 100 MHz slots from PXH
— One PCI Express x8 slot
— One PCI Express x4 slot
— One 5 V PCI-32/33 slot connected through the Intel®6300ESB I/O Controller
— Two 3.3 V PCI-X 64/66 slots connected through the Intel®6300ESB I/O Controller
•Low Pin Count Bus
— National* LPC 47M172 Super I/O residing on LPC bus
— LPC card header for debug purposes only
— Firmware hub
•IDE ATA 100 support
— Two ATA-100 IDE connectors supported
•S-ATA support
— Two S-ATA connectors
•USB Support (Four Channels)
— Two USB 2.0 connectors
— Two USB 2.0 headers
•Back Panel I/O

Intel®Xeon™ Processor, Intel®E7520 Chipset, Intel®6300ESB ICH Development Kit User’s Manual 9
Product Overview
— Two RS-232 serial ports from the Intel®6300ESB I/O Controller
— Two PS/2 connectors for mouse and keyboard
— On-board VGA Video, ATI Rage Mobility* video controller
— Parallel port
•Dual Watchdog Timer
•Miscellaneous
— National LM93* for fan control and temperature/voltage monitoring
Refer to Figure 1 for complete detailed features of the Intel®Xeon™ Processor with 800 MHz
system bus and Intel®E7520 and Intel®6300ESB Customer Reference Board (CRB).
1.4 Block Diagram
Figure 1. Intel®Xeon™ Processor with 800 MHz System Bus and Intel®E7520 and Intel®
6300ESB Customer Reference Board Block Diagram
Intel
®
Xeon
Intel
®
Xeon
ITP
Intel
®
E7520
MCH
PXH
PCI
-
X 100MHz
PCI
-
E
DDR 266
PCI-E x8PCI-E x4
PCI
-
E
DDR2 400
Intel®
6300ESB
ICH
CK409B
PCI
-
X 66MHz
HI 1.5
PCI
-
X
PCI 33MHz
PCI
IDE
S-ATA
S
-
ATA
IDE
USB 2.0
UART 1
UART 2
FWH
LPC Debug
SIO
Floppy
UART 3
Parallel
PS2
LM 93
VGA
DB800
DDR2 400
USB 2.0
USB 2.0
USB 2.0
PCI
-
X
133 MHz

10 Intel®Xeon™ Processor, Intel®E7520 Chipset, Intel®6300ESB ICH Development Kit User’s Manual
Product Overview
Figure 2. Placement - Top View
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Intel®
6300ESB
I/O
Controller
 

Intel®Xeon™ Processor, Intel®E7520 Chipset, Intel®6300ESB ICH Development Kit User’s Manual 11
Product Overview
1.4.1 Memory Subsystem
The memory subsystem is designed to support Double Data Rate2(DDR2) Synchronous Dynamic
Random Access Memory (SDRAM) using the Intel(R) E7520 MCH. The MCH provides two
independent DDR channels, which support DDR2 400 DIMMs. The peak bandwidth of each
DDR2 branch channel is 3.2 Gbyte/s (8 bytes x 400 MT/s) with DDR2 400. The two DDR2
channels from the MCH operate in lock step; the effective overall peak bandwidth of the DDR2
memory subsystem is 6.4 Gbyte/s for DDR2 400.
Table 2 shows all DIMM technology supported by the CRB. Other DIMM types are not supported.
1.4.2 DIMM Placement DDR2 400
Table 2. Supported DIMM Module Types
Technology Organization SDRAM Chips/DIMM
256 Mbit 8 Mbytes x 8 x 4 banks 8
16 Mbytes x 4 x 4 banks 16
512 Mbit 16 Mbytes x 8 x 4 banks 8
32 Mbytes x 4 x 4 banks 16
1 Gbit 32 Mbytes x 8 x 4 banks 8
64 Mbytes x 4 x 4 banks 16
Table 3. DIMM Placement DDR2 400
DIMM Configuration DIMM1 DIMM2
1 Single Rank Empty Single Rank
1 Dual Rank Empty Dual Rank
2 Single Rank Single Rank Single Rank
1 Dual Rank, 1 Single Rank Single Rank Dual Rank
2 Dual Rank Dual Rank Dual Rank
NOTES:
1. Populate DIMMs starting with the sockets farthest away from the MCH (DIMM slots A2 and B2).
2. When populating both channels, always place identical DIMMs in sockets that have the same position on
channel A and channel B (i.e., DIMM A2 should be identical to DIMM B2).

12 Intel®Xeon™ Processor, Intel®E7520 Chipset, Intel®6300ESB ICH Development Kit User’s Manual
Product Overview
1.5 Memory Population Rules and Configurations
The system supports two DDR2 400 DIMM slots for Channel A and two DDR2 400 DIMM slots
for Channel B. The four slots are interleaved and placed in a row in the following order: A1, B1,
A2, B2, with A1 being closest to the MCH. This design supports only registered ECC-enabled
DIMMs.
When populating both channels, always place identical DIMMs in sockets that have the same
position on Channel A and Channel B (i.e., DIMM A2 should be identical to DIMM B2).
In addition, single-rank DIMMs should be populated furthest when a combination of single-rank
and double-rank DIMMs are used. This recommendation is based on the signal integrity
requirements of the DDR2 interface.
Figure 3. DDR2 400 Memory - DIMM Ordering
B3519-01
+
++
DIMM B2 DIMM A2 DIMM B1 DIMM A1
MCH

Intel®Xeon™ Processor, Intel®E7520 Chipset, Intel®6300ESB ICH Development Kit User’s Manual 13
Platform Management
Platform Management 2
The following sections describe how the system power management operates and how the different
ACPI states are implemented. Platform management involves:
•ACPI implementation specific details
•System monitoring, control and response to thermal, voltage and intrusion events
•BIOS security
2.1 Power Button
The system power buttonis connected to the I/O controller component. When the button is pressed,
the I/O controller receives the signal and transitions the system to the proper sleep state as
determined by the operating system and software. If the power button is pressed and held for four
seconds, the system powers off (S5 state). This feature is called power button override and is
particularly helpful in case of system hang and system lock.
2.2 Soft Off
The I/O controller incorporates a SLP_S4 output signal which routes to the power supply. This
signal has register access that allows software to deactivate the power supply. When SLP_S4 goes
active, the power supply cuts main power but keeps 5 V auxiliary power rails available. 5 V
auxiliary voltage is active while the power supply receives AC power.
2.3 Sleep States Supported
The I/O controller controls the system sleep states. States S0, S1, S3, S4, and S5 are supported. The
platform enters sleep states in response to BIOS, operating system or user actions. Normally the
operating system determines which sleep state to transition into. However, a four-second power
button override event places the system immediately into S5. When transitioning into a software-
invoked sleep state, the I/O controller attempts to gracefully put the system to sleep by first going
into the processor C2 state.
2.3.1 S0 State
This is the normal operating state, even though there are some power savings modes in this state
using processor Halt and Stop Clock (processor C1 and C2 states). S0 affords the fastest wake-up
response time of any sleep state because the system remains fully powered and memory is intact.

14 Intel®Xeon™ Processor, Intel®E7520 Chipset, Intel®6300ESB ICH Development Kit User’s Manual
Platform Management
2.3.2 S1 State
This state is entered via a processor Sleep signal from the I/O controller (processor C3 state). The
system remains fully powered with memory contents intact but the processors enter their lowest
power state. The operating system disables bus masters for uniprocessor configurations while
flushing and invalidating caches before entering this state in multiprocessor configurations. Wake-
up latency is slightly longer in this state than in S0; however, power savings are improved from S0.
2.3.3 S2 State
This state is not supported.
2.3.4 S3 State
This state is called Suspend to RAM (STR). The system context is maintained in system DRAM,
but power is shut off to non-critical circuits. Memory is retained, and refreshes continue. All clocks
stop except the RTC. S3 is entered when the I/O controller asserts the SLP_S3# signal to
downstream circuitry to control 1.8 V power plane switching. Power must be switched from the
normal 1.8 V rail to standby 1.8 V, because the EPS-12V 550 W power supply does not directly
supply a standby 1.8 V rail. The sequence to enter Suspend to RAM is as follows:
1. The OS and BIOS prepare for S3 sleep state.
2. The OS sets the appropriate sleep bits in the I/O controller.
3. The I/O controller drives STPCLK to the processors.
4. The processors respond with a Stop-Grant cycle, passed over hub interface by MCH.
5. The I/O controller indicates an S3 (STR) sleep mode to the MCH via Hub Interface A.
6. The MCH puts DDR memory into the self-refresh mode.
7. The MCH drives DDR CMDCLK differential pairs and all DDR outputs low.
8. The MCH drives a completion message via Hub Interface A to the I/O controller.
9. The I/O controller turns off all voltage rails (except Standby 5V) from the main power supply
by asserting the SLP_S3_N signal.
— When in the S3 state, only the Standby 5 V rail is available from the power supply. The
board uses this standby source to generate 1.8 V standby rail to power the DIMMs.
— The asserted SLP_S3_N signal also controls the logic to switch the DIMM power source
from main 1.8 V to standby 1.8 V.
2.3.5 S4 State
This state is called Suspend to Disk. From a hardware perspective, it is equivalent to an S5 state.
The operating system is responsible for saving the system context in a special partition on the hard
drive. Although the system must power up and fully boot, boot time to an application is reduced
because the platform is returned to the same system state as when the preceding power off
occurred.

Intel®Xeon™ Processor, Intel®E7520 Chipset, Intel®6300ESB ICH Development Kit User’s Manual 15
Platform Management
2.3.6 S5 State
This state is the normal off state whether entered through the Power Button or Soft Off. All power
is shut off except for the logic required to restart. The system remains in the S5 State only while the
power supply is plugged into the electrical outlet. If the power supply is unplugged, this is
considered a Mechanical OFF or G3.
2.3.7 Wake-Up Events
The types of wake-up events and wake-up latencies are related tothe actual power rails available to
the system in a particular sleep state, as well as to the location in which the system context is
stored. Regardless of the Sleep State, Wake on the Power Button is always supported except in a
mechanical off situation. When in a Sleep State, the system complies with the PCI specification by
supplying the optional 3.3 V standby voltage to each PCI slot as well as the PME# signal. This
enables any compliant PCI card to wake up the system from supported sleep states except
Mechanical Off.
Note: Wake on USB, Wake on PS/2, and Wake on LAN are not supported.
2.3.8 Wake-Up from S1 Sleep State
During S1, the system is fully powered, permitting support for PCI Express* Wake and Wake on
PCI PME#.
2.3.9 Wake-Up from S4 and S5 States
The power button is used to wake from S4 and S5.
2.4 PCI PM Support
This design holds the system reset signal low when in a sleep state. The system supports the PCI
PME# signal and provides 3.3 V standby to the PCI and PCI Express slots. This support allows any
compliant PCI or PCI Express card to wake up the system from any sleep state except mechanical
off. The user and the operating system must configure the system carefully following the PCI
power management interface specification because of the limited amount of power available on
3.3 V standby.
2.5 Platform Management
The LM 93 monitors the majority of the system voltages. The VID signals from the processors are
also monitored by LM 93. All voltage levels can be read via the SMBus.

16 Intel®Xeon™ Processor, Intel®E7520 Chipset, Intel®6300ESB ICH Development Kit User’s Manual
Platform Management
2.5.1 Processor Thermal Management
Each processor monitors its own core temperature and thermally manages itself when it reaches a
certain temperature. The system also uses the internal processor diode to monitor the die
temperature. The diode pins are routed to the diode input pins in the LM 93. The LM 93 can be
programmed to force the processor fans to full speed operation when it senses the processor core
temperature exceeding a specific value. In addition, the LM 93 has an on chip thermal monitor
which allows it to monitor the incoming ambient temperature. Additional processor thermal
management requires the system to communicate to the processors when the VRD reaches a
critical temperature. The VR thermal monitor asserts FORCEPR_N signal to the processor. The
thermal monitor, an LM26, is a ±3° C precision thermostat used to sense high temperature
conditions and drive a digital output active low. This circuit works as an external PROCHOT event
to further protect the processor during high current/temperature conditions. This forces the
processor to activate a thermal protection circuit that reduces the current consumption of the
processor.
2.6 System Fan Operation
The system uses both the LM 93 and the National* 87427 Super I/O to monitor and control the fans
in the system.The LM93 uses pulse width modulated (PWM) outputs that can modulate the voltage
across the fans, providing a variable duty cycle to effect a reduced DC voltage from nominal 12
VDC. The fan headers are the standard 12V, three-pin type, used in previous Servers, which
support tachometer out. The LM 93 also has four tachometer inputs that it can use to monitor the
fans that it is controlling. All fan tachometer data can be extracted from the controllers via the
SMBus. The system fan speed control circuit does not control the power supply fan. Each PWM
output has a bypass jumper that causes all fans to run at full speed and ignore the PWM control.
Each processor fan has its own dedicated PWM output and tachometer input, so each fan is
controlled and monitored independently, depending on the core temperature. The LM 93 is
dedicated to processor fan speed control and monitor, and can be programmed with temperature
limit values that allow it to speed up or idle the processor fans, depending upon the input
temperature.

Intel®Xeon™ Processor, Intel®E7520 Chipset, Intel®6300ESB ICH Development Kit User’s Manual 17
Equipment Required for CRB Usage
Equipment Required for CRB Usage 3
The following components are required for the Intel®Xeon™ Processor with 800 MHz System
Bus and Intel®E7520 and Intel®6300ESB Customer Reference Board (CRB) usage:
•A 550 W SSI EPS 12 V power supply. The CRB is shipped with the power supply.
•At least two modules of DDR2 400 DIMM. The CRB is shipped with 2 x 256 Mbytes of
DDR2 400.
•Hard drive loaded with Operating System1
•Monitor
•PS/2 mouse and keyboard
Visually inspect the board and ensure that the MCH, Intel®6300ESB I/O Controller, PXH, and
other components did not shake loose during shipment. If the board has any loose or missing
components, contact your Intel representative.
Caution: Powering up without all components installed correctly could lead to a power-up failure that could
damage the board. Do not power up the board until the source of any loose component is
determined and the component has been replaced on the board.
3.1 Precautions
The following precautions will reduce the chances of damaging the board:
•Ensure that a 550 W SSI EPV 12 V power supply is used to power up the CRB. Refer to
Section 5.1, “Power Diagrams” on page 25 for details on the SSI power supply interface on the
CRB.
•This platform supports DDR2 400 DIMMs; ensure that the same speed DIMM is plugged in
all slots of the platform.
•Ensure that each processor has heat sinks attached before powering up the board.
•Ensure that the heat sink is attached to the MCH and PXH before powering up the board.
Never attach a heat sink while the board is powered.
•Use Table 4 to verify that all jumpers are in their default positions.
1. Note The hard disk provided with the development kit is not pre-loaded with any software.

18 Intel®Xeon™ Processor, Intel®E7520 Chipset, Intel®6300ESB ICH Development Kit User’s Manual
Equipment Required for CRB Usage
3.2 Driver and OS Requirements
The required INF driver for the CRB supports the functionality of the Intel®6300ESB I/O
Controller and PXH. The INF file will be included with Red Hat compatible drivers on the CD
shipped with the kit.
The CRB supports these operating systems:
•Microsoft Windows* XP, Windows Embedded XP, 2000 Pro, 2000 Server, 2000 Advanced
Server, 2003 Standard Edition
•Red Hat Linux Advanced Server 2.1, Red Hat 8.0 on kernel 2.4.x
•Wind River VxWorks* real-time operating system
•QNX Neutrino* real-time operating system
•Customer operating systems when applicable
3.2.1 Drivers included on CD
3.2.1.1 Red Hat 8.0 Compatible Driver Package Contents
This operating system compatible driver package is available from:
http://downloadfinder.intel.com/scripts-df/
Detail_Desc.asp?agr=Y&ProductID=1706&DwnldID=7249
esb_rh8.txt Release notes
sources/ac97/alsa-driver-0.9.0rc5.bz2 alsa-driver sources
sources/ac97/alsa-lib-0.9.0rc5.bz2 alsa-lib sources
sources/ac97/alsa-util-0.9.0rc5.bz2 alsa-util sources
sources/ac97/alsa-xmms-0.9.9b.tar.gz alsa plugin for xmms
sources/ac97/xmms-mpg123-1.2.7-13.i386.rpm mpeg plugin for xmms
sources/kernel/linux-2.4.20.tar.gz 2.4.20 kernel sources
sources/kernel/config-2.4.20-p4-upapic-i2c-apm-nooss UP Kernel Config File
sources/kernel/config-2.4.20-p4-upapic-i2c-acpi-nooss UP Kernel Config File
sources/kernel/config-2.4.20-p4-smp-i2c-apm-nooss MP Kernel Config File
sources/smbus/i2c-2.7.0.tar.gz latest I2C-core driver sources
sources/smbus/lm_sensors-2.7.0.tar.gz latest smbus adapter/sensor sources
sources/esbwdt/LICENSElicense for Intel WDT driver
sources/esbwdt/esbwdt-doc.txt Linux WDT Driver release notes
sources/esbwdt/driver/esbwdt.c Linux WDT Driver source file
sources/esbwdt/driver/esbwdt.h Linux WDT Driver header file
sources/esbwdt/driver/Makefile Linux WDT Driver Makefile
sources/esbwdt/demoapp/esbwdt-demo.c WDT driver demo application
patches/COPYING GPL-v2 license for Intel patches
patches/ac97/alsa-hr.patch enables ESB AC97 AC in ALSA
patches/ac97/alsa-hr-ich5.patch enables ICH5 AC97 AC in ALSA
patches/ide-sata/pci_ids-hr.patch enables ICH5 AC97 AC in ALSA
patches/ide-sata/pci_ids-hr-ich5.patch patches to 2.4.20 IDE driver
patches/ide-sata/piix.c-hr.patch to enable support for PATA & SATA storage interfaces
patches/ide-sata/piix.c-hr-ich5.patch to enable support for PATA & SATA storage
interfaces
patches/ide-sata/ide_pci-hr.patch integrated into the ESB & ICH5 Southbridges
patches/ide-sata/ide_pci-hr-ich5.patch integrated into the ESB & ICH5 Southbridges
patches/ide-sata/pci_irq-hr.patch integrated into the ESB & ICH5 Southbridges

Intel®Xeon™ Processor, Intel®E7520 Chipset, Intel®6300ESB ICH Development Kit User’s Manual 19
Equipment Required for CRB Usage
patches/ide-sata/pci_irq-hr-ich5.patch integrated into the ESB & ICH5 Southbridges
patches/lspci/pciids-112202.patch patch to update 2.4.20 pci.ids file
patches/lspci/pciids-112202-hr.patch patch to add ESB dev IDs to pci.ids
patches/lspci/pciids-112202-hr-ich5.patch patch to add ICH5 dev IDs to pci.ids
patches/ioapic/irqbalance-2.4.20-MRC.patch patch for use with P4 Hyper-Threading
patches/smbus/i2c-hr.patch enables ESB SMBUS dev in I2C driver
patches/smbus/i2c-hr-ich5.patch enables ICH5 SMBUS dev in I2C driver
patches/smbus/i2c-2.7.0-Makefile.patch customizations for I2C-2.7.0 Makefile
patches/smbus/lm_sensors-2.7.0-Makefile.patch customizations for lm_sensors
Makefile
patches/smbus/readme.txt build/install instruction for lm_sensors
binaries/binaries.tar.gz pre-build kernel and modules
utils/ks.cfg-raid015-hd-acd raid0, 1, & 5 enabled kickstart file
utils/ks.cfg-noraid-hda non-RAID kickstart file
utils/debug/readme-up.txt Instructions on using UP install scripts
ks.cfg-noraid-hda-cdrom-text-interactiveinteractive kickstart file
install-bin.pl script to automate UP pkg install
bldsrcs.pl script to automate UP pkg install
readme-smp.txt instructions on using SMP install scripts
bldsmpkernel.pl script to automate SMP kernel bld/install
bldsmpdrivers.pl script to automate SMP driver modules bld
3.2.1.2 Red Hat Advanced Server 2.1 Compatible Driver Package Contents
This operating system compatible driver package is available from:
http://downloadfinder.intel.com/scripts-df/
Detail_Desc.asp?agr=Y&ProductID=1706&DwnldID=7248
esb_rhas.txt Release notes
sources/ac97/alsa-driver-0.9.0rc5.bz2 alsa-driver sources
sources/ac97/alsa-lib-0.9.0rc5.bz2 alsa-lib sources
sources/ac97/alsa-util-0.9.0rc5.bz2 alsa-util sources
sources/ac97/alsa-xmms-0.9.9b.tar.gz alsa plugin for xmms
sources/ac97/README build/install instructions for ac97
sources/kernel/config-2.4.9-e.24-p4-smp-i2c Optimized MP Kernel Config File
sources/kernel/config-2.4.9-e.24-p4-upapic-i2c Optimized UP Kernel Config File
sources/kernel/install-2.4.9-e.24esb-grub.conf.patch Patch to install UP kernel
sources/kernel/install-2.4.9-e.24esbsmp.patch Patch to install SMP kernel
sources/kernel/rhas21-q2u-gold-iso origin of RHAS Q2-03 updates
sources/smbus/i2c-2.7.0.tar.gz latest i2c-core driver sources
sources/smbus/lm_sensors-2.7.0.tar.gz latest smbus adapter/sensor sources
sources/esbwdt/LICENSE license for Intel WDT driver
sources/esbwdt/esbwdt-doc.txt esbwdt driver/demoapp release notes
sources/esbwdt/driver/esbwdt.c esbwdt driver sources
sources/esbwdt/driver/esbwdt.h esbwdt driver header file
sources/esbwdt/driver/Makefile esbwdt driver Makefile
sources/esbwdt/demoapp/esbwdt-demo.c esbwdt driver demo app
patches/COPYING GPL-v2 license for Intel patches
patches/ac97/alsa-hr.patch enables ESB AC97 AC in alsa
patches/ac97/alsa-hr-ich5.patch enables ICH5 AC97 AC in alsa
patches/ide-sata/pci_ids-hr.patchpatches to 2.4.9-e.24 ide driver
patches/ide-sata/pci_ids-hr-ich5.patch patches to 2.4.9-e.24 ide driver
patches/ide-sata/piix.c-hr.patch to enable support for pata & sata storage interfaces
patches/ide-sata/piix.c-hr-ich5.patch to enable support for pata & sata storage
interfaces
patches/ide-sata/ide_pci-hr.patch integrated into the esb6300 & ich5 southbridges
patches/ide-sata/ide_pci-hr-ich5.patch integrated into the esb6300 & ich5 southbridges
patches/ide-sata/pci_irq-hr.patch integrated into the esb6300 & ich5 southbridges

20 Intel®Xeon™ Processor, Intel®E7520 Chipset, Intel®6300ESB ICH Development Kit User’s Manual
Equipment Required for CRB Usage
patches/ide-sata/pci_irq-hr-ich5.patch integrated into the esb6300 & ich5 southbridges
patches/lspci/pci.ids-hr.patch adds esb dev ids to 2.4.9-e.24 pci.ids
patches/lspci/pci.ids-hr-ich5.patch adds ich5 dev ids to 2.4.9-e.24 pci.ids
patches/smbus/i2c-hr.patch enables esb smbus dev in i2c driver
patches/smbus/i2c-hr-ich5.patch enables ich5 smbus dev in i2c driver
patches/smbus/i2c-2.7.0-Makefile.patch customizations for i2c-2.7.0 Makefile
patches/smbus/lm_sensors-2.7.0-Makefile.patch customizations for lm_sensors
Makefile
sources/smbus/lm_sensors-2.7.0-Module.mk-patch patch to fix bld errs on rhas v21
patches/smbus/readme.txt build/install instructions for smbus
utils/debug/ks.cfg-yyyy basic kickstart file to install from ftp to hda
utils/debug/bldkernel.pl script to build/install esb enabled UP kernel
utils/debug/bldsrcs.pl script to build/install esb enabled UP drivers
utils/debug/readme.txt BKM (aka EASIEST) way to install UP kernel & drivers
utils/debug/bldsmpkern.pl script to build/install esb enabled SMP kernel
utils/debug/bldsmpdrivers.pl script to build/install esb enabled SMP drivers
utils/debug/readme-smp.txt BKM (aka EASIEST) way to install SMP kernel & drivers
3.2.1.3 Windows Compatible Driver Package Contents
This operating system compatible driver package is available from:
http://downloadfinder.intel.com/scripts-df/
Detail_Desc.asp?agr=Y&ProductID=1706&DwnldID=7246
ESB_windows_Relnotes.txt Release notes for Windows* compatible drivers
SMB.SYS SMBus Driver
SMB.INF Install file for SMBus driver
SMB.CAT SMBus driver security catalog file
STAC97.SYS AC'97 audio code driver provided by SigmaTel*
SLAoemisv1.doc Single-user and OEM license for SigmaTel STA97 driver
WDTDRVR.SYS Watchdog Timer driver
WDTDRVR.INF Install file for Watchdog Timer driver
WDT_LICENSE.TXT Generic Alpha license for Watchdog Timer components
WDTDEMO.EXE Demo program for exercising Watchdog Timer features
Mfc42.dll Microsoft C++ runtime library
Mfco42.dll Microsoft C++ runtime library
Msvcrtd.dll Mircosoft C++ runtime library
wdtdemoAppSpec.pdf WdtDemo App user documentation
wdtdriverspec.pdf Overview of Watchdog Timer driver
Intelwdtapi.pdf Watchdog Timer driver interface API document
IWDTLIB.DLL Watchdog Timer Interface Dynamic Link Library
CWESB.slx eXP Configuration file
WESB.log log of OS build for eXP
eXP-README.DOC readme of eXP build
infinst_enu.exe Intel INF update utility
3.2.1.4 Third Party Drivers
Included on the CD is software compatible with the ATI Rage* Mobility-M Graphics Accelerator
021112a-006561C-ATI.zip.