Intel BX80623I52500K User manual

Intel®Pentium®4 Processor
Specification Update
August 2008
Revision 071
Document Number: 249199-071

2Specification Update
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL®PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS
PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER,
AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS
INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR
INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use
in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel
reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future
changes to them.
The Intel®Pentium®4 processor may contain design defects or errors known as errata which may cause the product to deviate
from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Intel Pentium 4 processor, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries
in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright ©2000-2008, Intel Corporation. All rights reserved.

Specification Update 3
Contents
Preface............................................................................................................................. 9
Summary Tables of Changes.............................................................................................. 11
General Information ......................................................................................................... 21
Identification Information .................................................................................................. 24
Errata ............................................................................................................................ 31
Specification Changes....................................................................................................... 69
Specification Clarifications ................................................................................................. 70
Documentation Changes ................................................................................................... 74
§

4Specification Update
Revision History
Revision Description Date
-001 •Initial Release November 2000
-002 •Added errata numbers N41-N44. December 2000
-003 •Updated Intel®Pentium®4 Processor Identification
Information. Updated erratum N40. Added errata N45 through
N46.
January 2001
-004 •Added errata N47. February 2001
-005 •Updated the processor identification information table.
Removed Possible system hang due to cacheable line-split loads
with page-tables in uncacheable (UC) space and Uncacheable
memory type prevents physical address code breakpoint match
erratum. Renumbered remaining errata. Modified the
workaround for N45. Added errata N46 and N47. Added
processor marking information.
March 2001
-006 •Updated plans column for errata N6, N7, N10, N11, N14, N18,
N19, N21, N23 – N28, N30 – N35, and N41
March 2001
-007 •Added information for the Intel®Pentium®4 processor in the
478-pin package, Added erratum N48.
April 2001
-008 •Updated the Intel®Pentium®4 Processor Identification
Information table. Added erratum N49.
May 2001
-009 •Updated Specification Update product key to include the Intel®
Xeon™processor. Updated erratum N45, added erratum N50
and Specification Change N1.
June 2001
-010 •Added errata N51 and Specification Clarification N1. Updated
Intel®Pentium®4 Processor Identification Information table.
July 2001
-011 •Added errata N52 and N53 and Specification Clarification N2. August 2001
-012 •Release for launch of new frequencies and the 478-pin
package. Updated Intel®Pentium®4 Processor Identification
Information table.
August 2001
-013 •Added errata N54 -- N56. September
2001
-014 •Added erratum N57. Added Specification Clarification N3.
Updated Intel®Pentium®4 Processor Identification Information
table.
October 2001
-015 •Added Documentation Changes N1 and N2. November 2001
-016 •Added erratum N58 and Documentation Change N3. December 2001
-017 •Added Intel®Pentium®4 Processor with 512-KB cache in 0.13
micron process information.
January 2002

Specification Update 5
Revision Description Date
-018 •Added Documentation Change N4. January 2002
-019 •Added errata N60 and N61. February 2002
-020 •Added Documentation Change N5 March 2002
-021 •Added errata N62 and N63. Removed Documentation Changes,
Specification Clarifications, and Specification Changes that have
been incorporated into documentation. Added Specification
Clarifications
N1 – N5.
April 2002
-022 •Updated erratum N37. Added errata N64. Added Specification
Change N1 to N3. Removed Documentation Changes that have
been incorporated into the documentation. Added
Documentation Changes N1 and N2.
May 2002
-023 •Added erratum N65. Removed Documentation Changes that
have been incorporated into the documentation. Added
Documentation Change N1 and N2.
June 2002
-024 •Added erratum N66. Removed Documentation Changes that
have been incorporated into the documentation. Added
Documentation Changes N3 to N12.
July 2002
-025 •Removed Documentation Changes that have been incorporated
into the documentation.
August 2002
-026 •Added 2.80 GHz and C1 stepping information. August 2002
-027 •Updated erratum N39. Added Documentation Changes N3 to
N24.
September
2002
-028 •Added erratum N67. Added Documentation Changes N25 to
N32.
October 2002
-029 •Added Package Markings under General Information.
•Added Erratum N68. Added Specification Clarification N1.
Added Specification Changes N3 and N4. Added Documentation
Changes N33-42.
November 2002
-030 •Added eight S-spec numbers under identification information
table.
December 2002
-031 •Added Errata N69 and N70. January 2003
-032 •Added Erratum N71. February 2003
-033 •Added full graphics range to General Information section. Minor
typographical errors from text conversion corrected.
February 2003
-034 •Updated Erratum N70. Added new Errata N72 and N73.
•Added S-spec numbers under identification information table.
March 2003
-035 •Added S-spec numbers under identification information table. April 2003
-036 •Added Erratum N74.
•Added Specification Clarification N2.
May 2003
-037 •Added Erratum N75 and Updated Errata N68 and N74. June 2003
-038 •Added 3.20 GHz S-spec number information. June 2003

6Specification Update
Revision Description Date
-039 •Added Errata N76 and N77. July 2003
-040 •Added Erratum N78 and Updated Erratum N69.
•Added N2 to specification changes.
August 2003
-041 •Added Errata N79 to N82. September
2003
-042 •Added Erratum N83. October 2003
-043 •Release for launch of Intel®Pentium®4 Processor Extreme
Edition Supporting Hyper-Threading Technology.
•Added Erratum N84
Added S-Spec number under identification information table.
November 2003
-044 •Added Erratum N85 and Updated Erratum N83. November 2003
-045 •Release 3.40 GHz Intel®Pentium®4 Processor Extreme Edition
Supporting Hyper-Threading Technology.
•Added S-Spec number under identification information table.
•Added Intel®Pentium®4 processor on 90 nm process.
•Removed Specification Change N2.
•Removed Specification Clarification Change N2
“Out of Cycle”
February 2004
-046 •Added Errata 90 to N92.
oN9 and /N91 removed in rev049.
oN92 changed to N86
•Added S-Spec number under identification information table.
March 2004
-047 •Updated Errata N9 and N85. April 2004
-048 •Updated Erratum N38
•Added Erratum N93.
oN93 is errata N87 in rev049
May 2004
-049 •Relocated Intel®Pentium®4 processor on 90 nm process
content to the Intel®Pentium®4 Processor on 90 nm Process
Specification Update
oRemoved Figure 5
oRemoved Notes 23 thru 26 in Table 1. Notes 27/28
renumbered to Notes 23/24 respectively
oRemoved corresponding S-Spec numbers: SL7B8,
SL79L, SL79K, SL7D8, SL7E8
oRemoved Errata N86-N90. Errata N91, N92, and N93
renumbered to N86, N87, and N88 respectively.
oRemoved references to Intel®Pentium®4 processor on
90 nm process documentation
•Added Erratum N89 thru N91
June 2004
-050 •Added Figure Numbers to each Figure
•Added content for Intel Pentium 4 Extreme Edition on 0.13
“Out of Cycle”
June 21 2004

Specification Update 7
Revision Description Date
micron process in 775-LGA package
oAdded Figure 5
oAdded Datasheet information and its link
oAdded S-spec number SL7GD
-051 •Added S-Spec number under identification information table
•Updated Summary Tables of Changes (Errata N16, N51, N56,
N69, N79, N84, N85 and N92)
•Modified erratum N69, and added erratum N92
Aug 2004
-052 •Updated Figure 7 diagram “Out of Cycle”
August 12,
2004
-053 •Added Errata N93-95 Sept 2004
-054 •Updated processor identification table, and added Errata N96-
97
Oct 2004
-055 •Added 1066 Products in processor identification table
•Added Erratum N98
“Out of Cycle”
November 1,
2004
-056 •Added Erratum N99 Nov 2004
-057 •Added Erratum N100 December 2004
-058 •Updated code used in summary table, and updated processor
identification table
February 2005
-059 •Added Specification Clarification and updated processor
identification table
April 2005
-060 •Updated Related Documents table July 2005
-061 •Added new Erratum N101
•Updated processor identification information table
October 2005
-062 •Updated Erratum N68. January 2006
-063 •Updated links to Software Developers Manuals. March 2006
-064 •Added errata N102 and N103. April 2006
-065 •Added erratum N104. Updated Summary Table of Changes. June 2006
-066 •Updated Software Developer Manuals Name. Updated
Summary Table of Changes.
October 2006
-067 •Updated Summary Table of Changes. December 2006
-068 •Updated Summary Table of Changes. January 2007

8Specification Update
Revision Description Date
-069 •Updated Summary Table of Changes. May 2007
-070 •Updated Summary Table of Changes. April 2008
-071 •Updated Summary Table of Changes August 2008
§

Preface
Specification Update 9
Preface
This document is an update to the specifications contained in the documents listed in
the following Affected Documents/Related Documents table. It is a compilation of
device and document errata and specification clarifications and changes, and is
intended for hardware system manufacturers and for software developers of
applications, operating system, and tools.
Information types defined in the Nomenclature section of this document are
consolidated into this update document and are no longer published in other
documents. This document may also contain information that has not been previously
published.
Affected Documents
Document Title Document
Number/Location
Intel®Pentium®4 Processor in the 423-pin Package
datasheet
249198-005
http://developer.intel.com/d
esign/pentium4/datashts/24
9198.htm
Intel®Pentium®4 Processor in the 478-pin Package
datasheet 249887-003 http://developer.intel.com/d
esign/pentium4/datashts/24
9887.htm
Intel®Pentium®4 Processor with 512-KB L2 Cache on 0.13
Micron Process and Intel®Pentium®4 Processor Extreme
Edition Supporting Hyper-Threading Technology1datasheet
298643-012
http://developer.intel.com/d
esign/pentium4/datashts/29
8643.htm
Intel®Pentium®4 Processor Extreme Edition on 0.13 Micron
Process in the 775-land Package datasheet
302350-001
http://intel.com/design/Penti
um4/datashts/302351.htm
NOTES:
1. Hyper-Threading Technology requires a computer system with an Intel®Pentium®4
processor supporting HT Technology and a Hyper-Threading Technology enabled
chipset, BIOS and operating system. Performance will vary depending on the specific
hardware and software you use. See <<http:// www.intel.com/info/hyperthreading/>>
for more information including details on which processors support HT Technology.
Related Documents
Document Title and Link
Intel®64 and IA-32 Intel Architectures Software Developer's Manual Volume 1: Basic

Preface
10 Specification Update
Document Title and Link
Architecture
Intel®64 and IA-32 Intel Architectures Software Developer's Manual Volume 2A:
Instruction Set Reference, A-M
Intel®64 and IA-32 Intel Architectures Software Developer's Manual Volume 2B:
Instruction Set Reference, N-Z
Intel®64 and IA-32 Intel Architectures Software Developer's Manual Volume 3A: System
Programming Guide
Intel®64 and IA-32 Intel Architectures Software Developer's Manual Volume 3B: System
Programming Guide
Nomenclature
Errata are design defects or errors. Errata may cause the Intel®Pentium®4
processor’s behavior to deviate from published specifications. Hardware and software
designed to be used with any given stepping must assume that all errata
documented for that stepping are present on all devices.
Specification Changes are modifications to the current published specifications.
These changes will be incorporated in the next release of the specifications.
Specification Clarifications describe a specification in greater detail or further
highlight a specification’s impact to a complex design situation. These clarifications
will be incorporated in the next release of the specifications.
Documentation Changes include typos, errors, or omissions from the current
published specifications. These changes will be incorporated in the next release of the
specifications.
Note: Errata remain in the specification update throughout the product’s lifecycle, or until a
particular stepping is no longer commercially available. Under these circumstances,
errata removed from the specification update are archived and available upon
request. Specification changes, specification clarifications and documentation
changes are removed from the specification update when the appropriate changes
are made to the appropriate product specification or user documentation
(datasheets, manuals, etc.).
§

Summary Tables of Changes
Specification Update 11
Summary Tables of Changes
The following table indicates the Specification Changes, Errata, Specification
Clarifications or Documentation Changes, which apply to the listed MCH steppings.
Intel intends to fix some of the errata in a future stepping of the component, and to
account for the other outstanding issues through documentation or Specification
Changes as noted. This table uses the following notations:
Codes Used in Summary Table
Stepping
X: Erratum, Specification Change or Clarification that applies
to this stepping.
(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification
change does not apply to listed stepping.
Status
Doc: Document change or update that will be implemented.
PlanFix: This erratum may be fixed in a future stepping of the
product.
Fixed: This erratum has been previously fixed.
NoFix: There are no plans to fix this erratum.
Row
Shaded: This item is either new or modified from the previous
version of the document.
Note: Each Specification Update item is prefixed with a capital letter to distinguish the
product. The key below details the letters that are used in Intel’s microprocessor
Specification Updates:
A = Dual-Core Intel® Xeon® processor 7000 sequence
C = Intel® Celeron® processor
D = Dual-Core Intel® Xeon® processor 2.80 GHz

Summary Tables of Changes
12 Specification Update
E = Intel® Pentium® III processor
F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D
processor
I = Dual-Core Intel® Xeon® processor 5000 series
J = 64-bit Intel® Xeon® processor MP with 1MB L2 cache
K = Mobile Intel® Pentium® III processor
L = Intel® Celeron® D processor
M = Mobile Intel® Celeron® processor
N = Intel® Pentium® 4 processor
O = Intel® Xeon® processor MP
P = Intel ® Xeon® processor
Q = Mobile Intel® Pentium® 4 processor supporting Hyper-Threading technology
on 90-nm process technology
R = Intel® Pentium® 4 processor on 90 nm process
S = 64-bit Intel® Xeon® processor with 800 MHz system bus (1 MB and 2 MB L2
cache versions)
T = Mobile Intel® Pentium® 4 processor-M
U = 64-bit Intel® Xeon® processor MP with up to 8MB L3 cache
V = Mobile Intel® Celeron® processor on .13 micron process in Micro-FCPGA
package
W= Intel® Celeron® M processor
X = Intel® Pentium® M processor on 90nm process with 2-MB L2 cache and
Intel® processor A100 and A110 with 512-KB L2 cache
Y = Intel® Pentium® M processor
Z = Mobile Intel® Pentium® 4 processor with 533 MHz system bus
AA = Intel® Pentium® D processor 900 sequence and Intel® Pentium® processor
Extreme Edition 955, 965
AB = Intel® Pentium® 4 processor 6x1 sequence
AC = Intel(R) Celeron(R) processor in 478 pin package
AD = Intel(R) Celeron(R) D processor on 65nm process
AE = Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm
process
AF = Dual-Core Intel® Xeon® processor LV
AG = Dual-Core Intel® Xeon® processor 5100 series
AH = Intel® Core™2 Duo/Solo processor for Intel® Centrino® Duo processor
technology
AI = Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop
processor E6000 and E4000 sequence

Summary Tables of Changes
Specification Update 13
AJ = Quad-Core Intel® Xeon® processor 5300 series
AK = Intel® Core™2 Extreme quad-core processor QX6000 sequence and Intel®
Core™2 Quad processor Q6000 sequence
AL = Dual-Core Intel® Xeon® processor 7100 series
AM = Intel® Celeron® processor 400 sequence
AN = Intel® Pentium® dual-core processor
AO = Quad-Core Intel® Xeon® processor 3200 series
AP = Dual-Core Intel® Xeon® processor 3000 series
AQ = Intel® Pentium® dual-core desktop processor E2000 sequence
AR = Intel® Celeron® processor 500 series
AS = Intel® Xeon® processor 7200, 7300 series
AT = Intel® Celeron® processor 200 series
AU = Intel® Celeron® Dual Core processor T1400
AV = Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad
processor Q9000 series
AW = Intel® Core™ 2 Duo processor E8000 series
AX = Quad-Core Intel® Xeon® processor 5400 series
AY= Dual-Core Intel® Xeon® processor 5200 series
AZ = Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-
nm Process
AAA = Quad-Core Intel® Xeon® processor 3300 series
AAB = Dual-Core Intel® Xeon® E3110 Processor
AAC = Intel® Celeron® dual-core processor E1000 series
AAD = Intel® Core™2 Extreme Processor QX9775Δ
AAE = Intel® Atom™ processor Z5xx series
AAF = Intel® Atom™ processor 200 series
AAG = Intel® Atom™ processor N series
No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA
N1 X X X X X X X X No Fix
I/O restart in SMM may fail after
simultaneous machine check exception
(MCE)
N2 X X X X X X X X No Fix
MCA registers may contain invalid
information if RESET# occurs and
PWRGOOD is not held asserted

Summary Tables of Changes
14 Specification Update
No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA
N3 X X X X Fixed
Uncacheable (UC) code in same line as
write back (WB) data may lead to data
corruption
N4 X X X X X X X X No Fix Transaction is not retried after BINIT#
N5 X X X X X X X X No Fix
Invalid opcode 0FFFh requires a ModRM
byte
N6X Fixed
RFO-ECC-snoop-MCA combination can
result in two lines being corrupted in
main memory
N7X Fixed
Overlap of MTRRs with the same
memory type results in a type of
uncacheable (UC)
N8 X X X X X X X X No Fix
FSW may not be completely restored
after page fault on FRSTOR or FLDENV
instructions
N9 X X X X X X X X No Fix
The Processor Signals Page-Fault Exception
(#PF) Instead of Alignment Check Exception
(#AC) on an Unlocked CMPXCHG8B
Instruction
N10X Fixed
IERR# may not go active when an
internal error occurs
N11X Fixed
All L2 cache uncorrectable errors are
logged as data writes
N12 X X X X X X X X No Fix
When in no-fill mode the memory type
of large pages are incorrectly forced to
uncacheable
N13 X X X X X X X X No Fix
Processor may hang due to speculative
page walks to non-existent system
memory
N14X Fixed
Load operations may get stale data in
the presence of memory address
aliasing
N15 X X X X Fixed
Writing a performance counter may
result in incorrect value
N16 X X X X Fixed
IA32_MC0_STATUS register overflow
bit not set correctly
N17 X X X X Fixed
Performance counter may contain
incorrect value after being stopped
N18X Fixed
The TAP drops the last bit during
instruction register shifting
N19X Fixed
Data breakpoints on the high half of a
floating point line split may not be
captured
N20 X X X X Fixed
MCA error code field in
IA32_MC0_STATUS register may
become out of sync with the rest of the

Summary Tables of Changes
Specification Update 15
No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA
register
N21X Fixed
Processor may hang on a correctable
error and snoop combination
N22 X X X X X X X X No Fix
The IA32_MC1_STATUS register may
contain incorrect information for
correctable errors
N23X Fixed
MCA error incorrectly logged as
prefetches
N24X Fixed
Speculative loads which hit the L2
cache and get an uncorrectable error
will log erroneous information
N25X Fixed
Processor may fetch reset vector from
cache if A20M# is asserted during init
N26X Fixed
A correctable error on an L2 cache
shared state line hit with go to invalid
snoop hangs processor
N27X Fixed
System hang due to uncorrectable
error and bus lock combination
N28X Fixed
Incorrect address for an L1 tag parity
error is logged in IA32_MC1_ADDR
register
N29 X X Fixed
REP MOV instruction with overlapping
source and destination may result in
data corruption
N30X Fixed
Stale data in processor translation
cache may result in hang
N31X Fixed
I/O buffers for FERR#, PROCHOT# and
THERMTRIP# are not AGTL+
N32X Fixed
RFO and correctable error combination
may cause lost store or hang
N33X Fixed
RFO and correctable error may
incorrectly signal the machine check
handler
N34X Fixed
Processor may report invalid TSS fault
instead of double fault during mode C
paging
N35X Fixed
IA32_MC0_STATUS incorrect after
illegal APIC request
N36 X X Fixed
Thermal status log bit may not be set
when the thermal control circuit is
active
N37 X X X X X X X X No Fix
Debug mechanisms may not function
as expected
N38 X X X X X X X X No Fix
Machine check architecture error
reporting and recovery may not work

Summary Tables of Changes
16 Specification Update
No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA
as expected
N39 X X X X Fixed
Processor may Timeout Waiting for a
Device to Respond after ~0.67 Seconds
N40 X X X X X X X X No Fix
Cascading of Performance Counters
does not work Correctly when Forced
Overflow is Enabled
N41X Fixed
Possible Machine Check Due to Line-
Split Loads with Page-Tables in
Uncacheable (UC) Space
N42 X X X X Fixed
IA32_MC1_STATUS MSR ADDRESS
VALID bit may be set when no Valid
Address is Available
N43 X X X X X X X X No Fix
EMON event counting of x87 loads may
not work as expected
N44 X X X X Fixed
Software controlled clock modulation
using a 12.5% or 25% duty cycle may
cause the processor to hang
N45 X X Fixed
Speculative page fault may cause
livelock
N46 X X Fixed
PAT index MSB may be calculated
incorrectly
N47 X X X Fixed
SQRTPD and SQRTSD may return
QNaN indefinite instead of negative
zero
N48 X X X X Fixed
Bus invalidate line requests that return
unexpected data may result in L1
cache corruption
N49 X X X X Fixed
Write Combining (WC) load may result
in unintended address on system bus
N50 X X X X X Fixed
Incorrect data may be returned when
page tables are in Write Combining
(WC) memory space
N51 X X X Fixed
Buffer on resistance may exceed
specification
N52 X X X X X X X X No Fix
Processor issues inconsistent
transaction size attributes for locked
operation
N53 X X X X X Fixed
Multiple accesses to the same S-state
L2 cache line and ECC error
combination may result in loss of cache
coherency
N54 X X X X Fixed
Processor may hang when resuming
from Deep Sleep state
N55 X X X X X X X X No Fix
When the processor is in the System
Management Mode (SMM), debug
registers may be fully writeable

Summary Tables of Changes
Specification Update 17
No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA
N56 X X X X Fixed
Associated counting logic must be
configured when using Event Selection
Control (ESCR) MSR
N57 X X X X X X X X No Fix
IA32_MC0_ADDR and IA32_MC0_MISC
registers will contain invalid or stale
data following a Data, Address, or
Response Parity Error
N58 X X X X X Fixed
CR2 may be incorrect or an incorrect
page fault error code may be pushed
onto stack after execution of an LSS
instruction
N59 X Fixed
BPM[5:3]# VIL does not meet
specification
N60 X X X X No Fix
Processor may hang under certain
frequencies and 12.5% STPCLK# duty
cycle
N61 X X X X X X X X No Fix
System may hang if a fatal cache error
causes Bus Write Line (BWL)
transaction to occur to the same cache
line address as an outstanding Bus
Read Line (BRL) or Bus Read-Invalidate
Line (BRIL)
N62 X X X X X Fixed
L2 cache may contain stale data in the
Exclusive state
N63 X X X X X X Fixed
Re-mapping the APIC base address to
a value less than or equal to
0xDC001000 may cause IO and Special
Cycle failure
N64 X X X Fixed
Erroneous BIST result found in EAX
register after reset
N65 X X X X X Fixed
Processor does not flag #GP on non-
zero write to certain MSRs
N66 X X X X X X X X No Fix
Simultaneous assertion of A20M# and
INIT# may result in incorrect data
fetch
N67 X X X X X Fixed
CPUID instruction returns incorrect
number of ITLB entries
N68 X X X X X X X X No Fix
A Write to an APIC Register Sometimes May
Appear to Have Not Occurred
N69 XX
Plan
Fix
STPCLK# Signal Assertion under
Certain Conditions May Cause a
System Hang
N70 X Fixed
Store to Load Data Forwarding may
Result in Switched Data Bytes
N71 X X X X No Fix
Parity Error in the L1 Cache may Cause
the Processor to Hang

Summary Tables of Changes
18 Specification Update
No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA
N72 X X Fixed
The TCK Input in the Test Access Port
(TAP) is Sensitive to Low Clock Edge
Rates and Prone to Noise Coupling
Onto TCK's Rising or Falling Edges
N73 X X X No Fix
Disabling a Local APIC Disables Both
Logical Processor APICs on a Hyper-
Threading Technology Enabled
Processor
N74 XX
Plan
Fix
A circuit marginality in the 800 MHz
Front Side Bus power save circuitry
may cause a system and/or application
hang or may result in incorrect data
N75 X X X No Fix
Using STPCLK# and Executing Code
From Very Slow Memory Could Lead to
a System Hang
N76 X X X X X X No Fix
Changes to CR3 Register do not Fence
Pending Instruction Page Walks
N77 X X X X X X X X No Fix
The State of the Resume Flag (RF Flag)
in a Task-State Segment (TSS) May be
Incorrect
N78 X X X X X X X X No Fix
Processor Provides a 4-Byte Store
Unlock After an 8-Byte Load Lock
N79 X X1X
1Plan
Fix
Simultaneous Page Faults at Similar
Page Offsets on Both Logical Processors
of an Hyper-Threading Technology
Enabled Processor May Cause
Application Failure
N80 X X X X X X X X No Fix
System Bus Interrupt Messages
Without Data Which Receive a
HardFailure Response May Hang the
Processor
N81 X X X X X X X X No Fix
Memory Type of the Load Lock
Different from its Corresponding Store
Unlock
N82 X X X No Fix
Shutdown and IERR# May Result Due
to a Machine Check Exception on a
Hyper-Threading Technology Enabled
Processor
N83 X X X X X X X X
Plan
Fix
A 16-bit Address Wrap Resulting from
a Near Branch (Jump or Call) May
Cause an Incorrect Address to Be
Reported to the #GP Exception Handler
N84 X
Plan
Fix
Simultaneous Cache Line Eviction From
L2 and L3 Caches may Result in the
Write Back of Stale Data
N85 X X X No Fix
Locks and SMC Detection May Cause
the Processor to Temporarily Hang

Summary Tables of Changes
Specification Update 19
No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA
N86 X X X X X X X X No Fix
Incorrect Debug Exception (#DB) May
Occur When a Data Breakpoint is set
on an FP Instruction
N87 X
Plan
Fix
Modified Cache Line Eviction From L2
Cache May Result in Writeback of Stale
Data
N88 X X X X X X X X No Fix
xAPIC May Not Report Some Illegal Vector
Errors
N89 X X X
Plan
Fix
Incorrect Duty Cycle is Chosen when On-
Demand Clock Modulation is Enabled in a
Processor Supporting Hyper-Threading
Technology
N90 X X X X X X X X No Fix
Memory Aliasing of Pages as Uncacheable
Memory Type and Write Back (WB) May Hang
the System
N91 XX
Plan
Fix
A Timing Marginality in the Instruction Decoder
Unit May Cause an Unpredictable Application
Behavior and/or System Hang
N92 X X X No Fix
Missing Stop Grant Acknowledge Special Bus
Cycle May Cause a System Hang
N93 X X X X X X X X No Fix
Check Exceptions May not Update Last-
Exception Record MSRs (LERs)
N94 X X X X X X X X No Fix
Stores to Page Tables May Not Be Visible to
Pagewalks for Subsequent Loads Without
Serializing or Invalidating the Page Table Entry
N95 XX
Plan
Fix
A Timing Marginality in the Arithmetic Logic
Unit (ALU) May Cause Indeterminate Behavior
N96 X X X X X X X X No Fix
With TF (Trap Flag) Asserted, FP Instruction
That Triggers an Unmasked FP Exception
May Take Single Step Trap Before Retirement
of Instruction
N97 X X X X X X X X No Fix
BTS(Branch Trace Store) and PEBS(Precise
Event Based Sampling) May Update Memory
outside the BTS/PEBS Buffer
N98 XNoFix
Brand String Field Reports Incorrect Maximum
Operating Frequency on Intel®Pentium®4
Extreme Edition Processor with 1066 MHz
FSB
N99 X X X X X X X X No Fix
Memory Ordering Failure May Occur with
Snoop Filtering Third Party Agents after
Issuing and Completing a BWIL (Bus Write
Invalidate Line) or BLW (Bus Locked Write)
Transaction
N100 X X X X X X X X No Fix
Control Register 2 (CR2) Can be Updated
during aREP MOVS/STOS Instruction with
Fast Strings Enabled
N101 X X X X X X X X No Fix
Writing the Local Vector Table (LVT)

Summary Tables of Changes
20 Specification Update
No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA
when an Interrupt is Pending May Cause an
Unexpected Interrupt
N102 X X X X X X X X No Fix
Using 2M/4M Pages When A20M# Is
Asserted May Result in Incorrect
Address Translations
N103 X X X X X X X X No Fix
Writing Shared Unaligned Data that
Crosses a Cache Line without Proper
Semaphores or Barriers May Expose a
Memory Ordering Issue
N104 X X X X X X X X No Fix
Debug Status Register (DR6)
Breakpoint Condition Detected Flags
May be set Incorrectly
NOTE:
1. For these steppings, this erratum may be worked around in BIOS.
No. B2 C1 D0 E0 B0 C1 D1 M0 Plans SPECIFICATION CHANGES
There are no specification changes in
this Specification Update revision.
No. B2 C1 D0 E0 B0 C1 D1 M0 Plans SPECIFICATION CLARIFICATIONS
N1 X X X X X X X X Doc
Specification clarification with respect
to time stamp counter
No. B2 C1 D0 E0 B0 C1 D1 M0 Plans DOCUMENTATION CHANGES
TherearenoDocumentationChanges
in this Specification Update revision.
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