Intel IXP28XX User manual

Order Number: 309192-002US
Intel®IXP28XX Network
Processors
Hardware Design Guide
August 2005

2
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IXP28XX Network Processor
Contents
3
Contents
1 Introduction....................................................................................................................................11
1.1 System Overview................................................................................................................11
1.2 In This Guide ......................................................................................................................13
1.2.1 Typographical Conventions ...................................................................................14
1.2.2 Acronyms and Terminology...................................................................................14
1.3 Related Documentation ......................................................................................................16
1.4 Contacting Intel®................................................................................................................16
2 Power Ratings and Requirements.................................................................................................17
2.1 Power Ratings ....................................................................................................................17
2.2 Supply Voltage Power-up Sequence..................................................................................24
2.2.1 Sequence for 1.4 / 1.0 GHz Devices .....................................................................24
2.2.2 Sequence for 650 MHz Devices ............................................................................24
2.2.3 Power Supply Regulation ......................................................................................25
2.2.3.1 Power-Up Power Supply Regulation......................................................25
2.2.3.2 Power Supply Decoupling......................................................................25
2.3 LC Filter Network................................................................................................................26
2.4 IXDP2800 Advanced Development Platform Power Supply Subsystem............................27
2.4.1 Subsystem Block Diagram.....................................................................................27
2.4.2 Power-up Sequence ..............................................................................................29
2.5 IXP28XX Network Processor Power-On di/dt Profiles........................................................30
2.5.1 di/dt Droop Analysis Results..................................................................................31
2.5.2 Recommendations From Droop Analysis ..............................................................31
3 RDRAM .........................................................................................................................................33
3.1 IXMB2800 RDRAM Subsystem Design..............................................................................33
3.1.1 RDRAM Subsystem Implementation Options........................................................34
3.2 Rambus* Channel Design ..................................................................................................35
3.2.1 RSL Trace Requirements and Recommendations ................................................35
3.2.2 Unused Channel Guidelines..................................................................................36
3.2.3 Crosstalk................................................................................................................36
3.2.4 Third-party Sources ...............................................................................................36
3.2.5 IXP28XX Network Processor Power-Up Sequence...............................................36
3.2.6 IXP28XX Network Processor Power-Up Considerations when using NexMod*
Memory Modules ...................................................................................................37
3.3 IXP28XX Network Processor Rambus* Controller Footprint and Via Placement...............38
3.4 IXP28XX Network Processor Controller Escape Routing...................................................41
3.5 IXP28XX Network Processor Three-Channel Controller to HCD NexMod* RDRAM
Routing ...............................................................................................................................46
3.6 IXP28XX Network Processor Short Channel Routing ........................................................49
3.7 Package Trace Lengths for RDRAM Signals......................................................................50
4 QDR SRAM ...................................................................................................................................53
4.1 Introduction.........................................................................................................................53
4.2 QDR Clocking Scheme.......................................................................................................54
4.2.1 SRAM Controller Configurations............................................................................54
4.3 QDR SRAM Connections ...................................................................................................57

IXP28XX Network Processor
Contents
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4.4 QDR SRAM Interface .........................................................................................................57
4.4.1 Using x9 Versus x18 QDR SRAM Parts................................................................58
4.4.1.1 Examples of the QDR Interface.............................................................60
4.4.2 Signal Groups........................................................................................................62
4.4.3 QDR Signal Mapping.............................................................................................62
4.4.4 ClamShell Configuration of SRAMs.......................................................................63
4.4.5 QDR SRAM Input/Output Timing Specifications....................................................64
4.4.5.1 IXP2800 Input Timing ............................................................................64
4.4.5.2 IXP2800 Output Timing..........................................................................64
4.4.6 QDR Signal Group Package Trace Length............................................................64
4.5 QDR SRAM Routing Rules.................................................................................................65
4.5.1 QDR Trace Requirements .....................................................................................65
4.5.2 QDR SRAM Address Topology .............................................................................65
4.5.3 QDR SRAM D (Data Out) Topology......................................................................68
4.5.4 QDR SRAM Q (Data In) Topology.........................................................................70
4.5.5 QDR SRAM K, K# Clock Topologies.....................................................................71
4.5.5.1 Relationship between Address, Control, Data-OUT and K-Clock..........73
4.5.6 QDR SRAM C, C#, CIN, CIN# Clock Topologies..................................................74
4.5.7 QDR SRAM RPE#, WPE#, BWE# Control Topologies .........................................76
4.6 QDR SRAM VREF Generation...........................................................................................79
4.7 TCAM/SRAM/Coprocessor Interface..................................................................................81
4.7.1 TCAM/SRAM/Coprocessor Interface — Base Card Side......................................81
4.7.1.1 Interface Topologies ..............................................................................81
4.8 IXDP2800 QDR Implementation Guidelines.......................................................................84
4.8.1 Routing for a Four-QDR SRAM Topology .............................................................84
4.8.2 Determining Loopclock Length for QDRII SRAM Used by IXDP2800 Advanced
Development Platform...........................................................................................85
4.8.3 QDR SRAM Alternating Routing Layers................................................................89
4.9 IXDP2800 TCAM Implementation.......................................................................................90
4.9.1 TCAM and QDR SRAM Placement.......................................................................90
4.9.2 QDR SRAM and TCAM Routing Implementation..................................................92
4.10 QDR SRAM and TCAM Routing.........................................................................................93
4.11 QDR SRAM Design Review Checklist................................................................................94
4.12 Package Trace Lengths for QDR Signals...........................................................................95
5 MSF (SPI-4/CSIX/FC) .................................................................................................................101
5.1 Media and Switch Fabric Interface ...................................................................................101
5.1.1 SPI-4.2.................................................................................................................101
5.1.2 CSIX ....................................................................................................................102
5.1.3 Flow Control Bus .................................................................................................103
5.2 Routing Recommendations for LVDS Signals..................................................................104
5.2.1 LVDS Trace Requirements..................................................................................104
5.2.2 LVDS Trace Characteristics for IXDP2800 Advanced Development Platform....104
5.2.3 Design Review Checklist.....................................................................................104
5.2.4 LVDS Routing Example.......................................................................................105
5.3 Simulation Results for LVDS Signals on IXDP2800 Advanced Development Platform....106
5.4 Package Trace Lengths for LVDS_Diff Signals................................................................108
6 PCI...............................................................................................................................................111
6.1 PCI Controller...................................................................................................................111
6.2 PCI Interface.....................................................................................................................111

IXP28XX Network Processor
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6.2.1 PPCI Bus Interface ..............................................................................................112
6.2.1.1 PPCI Address/Data Signals.................................................................112
6.2.1.2 PPCI Clock Signals..............................................................................113
6.2.1.3 Address/Data Signals with IDSEL........................................................114
6.2.2 SPCI Bus Interface ..............................................................................................116
6.2.2.1 SPCI Address/Data Signals.................................................................116
6.2.2.2 SPCI Clock Signals..............................................................................117
6.2.2.3 SPCI Address/Data Signals with IDSEL ..............................................118
6.2.3 cPCI Bus Interface...............................................................................................120
6.2.3.1 cPCI Signals ........................................................................................120
6.3 PCI Design Review Checklist ...........................................................................................121
6.4 PCI Routing Examples: IXP2800 Network Processor ......................................................121
6.5 Package Trace Lengths for PCI Signals...........................................................................124
7 Slowport.......................................................................................................................................127
7.1 Slowport Interface.............................................................................................................128
7.1.1 Slowport Signals..................................................................................................130
7.1.1.1 Topology and Routing..........................................................................130
7.1.2 Flash Memory and Microprocessor Interface Support.........................................133
7.1.2.1 Flash PROM Interface Logic................................................................134
7.1.2.2 Microprocessor Interface Logic............................................................136
7.2 Summary ..........................................................................................................................145
8 Mechanical/Packaging.................................................................................................................147
8.1 Package Marking..............................................................................................................147
8.2 Package Dimensions........................................................................................................149
Index............................................................................................................................................151
Figures
1 IXP2800/IXP2850 Network Processor Functional Block Diagram..............................................13
2 IXDP2800 Decoupling Implementation.......................................................................................26
3 LC Filter Network........................................................................................................................27
4 IXDP2800 Advanced Development Platform Power Supply Subsystem....................................28
5 IXDP2800 Advanced Development Platform Power-up Sequence............................................29
6 IXP28XX Network Processor di/dt Stimulus...............................................................................30
7 Power-up Sequence...................................................................................................................37
8 Common VCCR_IO for All Three RACs in the IXP28XX® Network Processor..........................38
9 Rambus* Controller Footprint and Via Placement Showing Alternating Dogbone Orientation...39
10 Rambus* Controller Footprint and Via Placement Showing Exploded View of
Checkerboard Detail...................................................................................................................40
11 Network Processor Controller Escape Routing - Layer 4...........................................................41
12 Network Processor Controller Escape Routing - Layer 6...........................................................42
13 Network Processor Controller Escape Routing - Layer 13.........................................................43
14 Network Processor Controller Escape Routing - SCK/CMD Signals Routed on Layer 12.........44
15 Network Processor Controller Escape Routing - SCK/CMD Signals Routed on Layer 16.........45
16 Three-Channel Controller to HCD NexMod* RDRAM Routing - Layer 4....................................46
17 Three-Channel Controller to HCD NexMod* RDRAM Routing - Layer 6....................................47
18 Three-Channel Controller to HCD NexMod* RDRAM Routing - Layer 13..................................48
19 Three-Channel Controller to HCD NexMod* RDRAM Routing - SCK/CMD Layer 12 ................48
20 IXP28XX Network Processor Short Channel Routing ................................................................49

IXP28XX Network Processor
Contents
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21 Clocking Scheme for a QDR Interface Driving Four SRAMs......................................................54
22 QDR SRAM Connections ...........................................................................................................57
23 Topologies for Using x9 Versus x18 QDR SRAM Parts.............................................................59
24 IXP2800 Width-Expanded QDR Interface ..................................................................................60
25 Ingress IXP28XX Network Processor QDR Modular Channel Depth-Expanded QDR Interface61
26 Ingress IXP2800 Network Processor QDR Modular Channel, Four-Load QDR Interface..........61
27 QDR Address Signals — Balanced T-Topology.........................................................................66
28 QDR Address Routing — T-Topology with Daisy-Chain Branches............................................66
29 QDR Address Signal Trace Width/Spacing Routing...................................................................67
30 D (Data Out) Routing Topology..................................................................................................68
31 QDR D Signal Trace Width/Spacing Routing .............................................................................69
32 Q (Data In) Routing Topology.....................................................................................................70
33 QDR Q Signal Trace Width/Spacing Routing.............................................................................71
34 QDR K and K# Routing Topology...............................................................................................72
35 QDR K and K# Signal Trace Width/Spacing Routing.................................................................73
36 QDR C, C#, CIN, and CIN# Routing Topology...........................................................................74
37 QDR C, C#, CIN, CIN# Signal Trace Width/Spacing Routing ....................................................75
38 QDR Control RPE# and WPE# Signals Routing Topology ........................................................76
39 QDR Control RPE# and WPE# Signal Trace Width/Spacing Routing........................................77
40 QDR Control BWE# Signals Routing Topology..........................................................................78
41 Control BWE# Signal Trace Width/Spacing Routing..................................................................79
42 QDR SRAM VREF Generation...................................................................................................80
43 Resistive QDR VREF Divider Example ......................................................................................80
44 Voltage QDR VREF Divider Example for Each QDR Channel...................................................81
45 Address, D, CONTROL, Q, and K-Clocks Topologies ...............................................................82
46 C, C#, CIN, and CIN# Clocks Topologies...................................................................................83
47 QDR SRAM Routing Recommendations....................................................................................84
48 Four-QDR SRAM Load Routing Recommendations ..................................................................85
49 Example Interconnects on the IXP28XX Network Processor, with a Two-QDRII SRAM Load
per Channel................................................................................................................................86
50 Trace Length from IXP28XX Network Processor to SRAM (C, K, SA, D, and R/W_BW) ..........87
51 Trace Length from SRAM to IXP28XX Network Processor (Q Data).........................................87
52 QDR 0 Routing on Layer 13 - Adjacent QDR Clamshell Pairs...................................................89
53 QDR 1 Routing on Layer 12 - Adjacent QDR Clamshell Pairs...................................................90
54 TCAM and QDR SRAM Placement............................................................................................91
55 Routing Recommendations for QDR SRAM and TCAM Routing...............................................92
56 QDR Signal from IXP28XX Network Processor to Tee Point on Layer 12.................................93
57 QDR Signal Tee Point Arms Routed on Signal Layers 4 and 13 ...............................................94
58 SPI-4 Clock Configuration for Dual Network Processors .........................................................102
59 CSIX Flow Control Interfaces: Simplex and Full Duplex Modes...............................................103
60 LVDS Routing as Signal Pairs..................................................................................................105
61 Topology 1 - Two Unique PCBs Connected.............................................................................106
62 Topology 2 - Two Unique PCBs with Signal Loopback Through Connectors ..........................107
63 PCI Subsystem.........................................................................................................................112
64 PPCI Address/Data Signal Topology........................................................................................113
65 PPCI Clock Signals Topology...................................................................................................114
66 Address/Data Signals with IDSEL Topology (Showing Only the Ingress
Intel® IXP28XX Network Processor)........................................................................................115
67 SPCI Address/Data Signal Topology........................................................................................116
68 SPCI Clock Signals Topology...................................................................................................117

IXP28XX Network Processor
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69 SPCI Address/Data Signals with IDSEL Signal Topology........................................................118
70 cPCI Signal Topology...............................................................................................................120
71 IXDP2800 PCI Bus Topology Block Diagram...........................................................................121
72 64-Bit PCI Bus Routing Between Processors...........................................................................122
73 64-bit PCI Bus Routing from IXP28XX Network Processor to Bridge.......................................123
74 Generic Slowport Connection...................................................................................................127
75 Example Ingress IXP28XX Network Processor Slowport Configuration...................................128
76 Example Egress IXP28XX Slowport Configuration...................................................................129
77 CPLD Implementation of a Flash EEPROM Interface..............................................................129
78 Slowport Control Signals Topology...........................................................................................131
79 Slowport Clock Topology..........................................................................................................132
80 Slowport Address/Data Topology.............................................................................................133
81 Slowport Application Topology .................................................................................................135
82 Mode 0 Single Write Transfer for a Fixed-timed Device...........................................................135
83 Mode 0 Single Write Transfer for a Self-timing Device.............................................................136
84 An Interface Topology with Intel / AMCC* SONET/SDH Device ..............................................139
85 Mode 3 32-Bit Write Transfer....................................................................................................140
86 Slowport Mode 3 write example showing TXE +1 delay using SP_TXE ..................................141
87 Mode 32-Bit Read Transfer ......................................................................................................142
88 Slowport Mode 3 read example showing RXE = 2 ...................................................................143
89 Intel® IXP2800 Network Processor Package Marking .............................................................148
90 Intel® IXP2850 Network Processor Package Marking .............................................................148
91 Intel® IXP2800 or Intel® IXP2850 Network Processor Package Ball Grid Array .....................149
92 Intel® IXP2800 or Intel® IXP2850 Network Processor Package Side View.............................149
93 Intel® IXP2800 or Intel® IXP2850 Network Processor Package Top View..............................150
Tables
1 Product Features of IXP28XX Network Processors ...................................................................12
2 Guide Conventions.....................................................................................................................14
3 Acronyms and Terminology........................................................................................................14
4 Absolute Maximum/Minimum Ratings Table ..............................................................................17
5 Functional Operating Temperature Range.................................................................................17
6 Typical and Maximum Power......................................................................................................18
7 Functional Operating Voltage Range – 1.4/1.0 GHz ..................................................................19
8 Functional Operating Voltage Range – 650 MHz.......................................................................20
9 Example Power by Supply – 1.4 GHz.........................................................................................21
10 Example Power by Supply – 1.0 GHz.........................................................................................22
11 Example Power by Supply – 650 MHz .......................................................................................23
12 RDRAM Subsystem Implementation Options.............................................................................34
13 Package Trace Lengths for RDRAM Signals..............................................................................50
14 SRAM Controller Configurations.................................................................................................55
15 QDR Address/RPE/WPE Mapping.............................................................................................55
16 Total Memory per Channel.........................................................................................................55
17 An Overview of QDR signal groups............................................................................................62
18 QDR SRAM Signal Mapping.......................................................................................................62
19 QDR Address Signal Group Routing Guidelines........................................................................67
20 QDR Address Stack-up Signal Cross-section Details ................................................................68
21 QDR D Signal Group Routing Guidelines...................................................................................69
22 QDR D Stack-up Signal Cross-section Details...........................................................................69
23 QDR Q (Data In) Signal Group Routing Guidelines....................................................................70

IXP28XX Network Processor
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24 QDR Q Stack-up Signal Cross-section Details...........................................................................71
25 QDR K and K# Signal Group Routing Guidelines ......................................................................72
26 QDR K-Clock Stack-up Signal Cross-section Details.................................................................73
27 QDR C, C#, CIN, and CIN# Signal Group Routing Guidelines...................................................74
28 QDR C and CIN Clock Signal Trace Width/Spacing Routing Details.........................................75
29 QDR Control RPE# and WPE# Signal Group Routing Guidelines.............................................76
30 QDR CONTROL Stack-up Signal Cross-section Details............................................................77
31 QDR Control BWE# Signal Group Routing Guidelines ..............................................................78
32 QDR CONTROL Stack-up Signal Cross-section Details............................................................79
33 TCAM/SRAM/Coprocessor Interface Guidelines (Address, D, CONTROL, Q, and K-Clocks)...82
34 TCAM/SRAM/Coprocessor Interface Guidelines (C, C#, CIN, and CIN# Clocks)......................83
35 Package Trace Lengths for QDR Signals...................................................................................96
36 Topology 1 Network Length Results ........................................................................................106
37 Topology 2 Network Length Results ........................................................................................107
38 Package Trace Lengths for LVDS_Diff Signals........................................................................108
39 PPCI Address/Data Group Guidelines .....................................................................................113
40 PPCI Clock Signals Group Guidelines .....................................................................................114
41 Address/Data Signal with IDSEL Group Guidelines.................................................................115
42 SPCI Address/Data Group Guidelines .....................................................................................116
43 SPCI Clock Signals Group Guidelines .....................................................................................117
44 SPCI Address/Data Signals with IDSEL Group Guidelines......................................................119
45 cPCI Signal Group Guidelines..................................................................................................120
46 Package Trace Lengths for PCI Signals...................................................................................124
47 Signal Description.....................................................................................................................130
48 Slowport Control Signals Routing Guidelines...........................................................................131
49 Slowport Clock Signals Guideline.............................................................................................132
50 Slowport Address/Data Routing Guidelines .............................................................................133
51 Intel® IXP2800 or IXP2850 Network Processor Package Dimensions ....................................150

IXP28XX Network Processor
Revision History
9
Revision History
Date Revision Description
August 2005 002 Updates to Chapter 4 QDR SRAM.
December 2004 001 Initial release

IXP28XX Network Processor
Revision History
10

Hardware Design Guide 11
IXP28XX Network Processor
Introduction
Introduction 1
The purpose of this manual is to accelerate the development of Intel®IXP28XX Network
Processor hardware designs. The manual provides the hardware developer general design
guidelines and includes specific design implementations used on the IXDP2800 Advanced
Development Platform.
These guidelines have been developed to ensure maximum flexibility for board designers and to
reduce board-related problems. The design information in this document is in two categories:
•Design Recommendations, based on Intel’s simulations and lab debugging experience to
date, and are strongly recommended (or necessary) to meet timing and signal quality
specifications.
•Design Considerations or suggestions, based on the development platforms designed by Intel.
They should be used as examples, but may not be applicable to particular designs.
Note: The guidelines recommended in this document are based on simulation work completed by Intel.
This work is ongoing, and recommendations are subject to change.
Note: General information regarding certain artwork in this document. Due to differences in output
devices, some figures may display inconsistently. For example, viewing a figure on a computer
screen and producing hardcopy to a printer can result in the screen providing finer resolution than
the printer.
1.1 System Overview
The IXP28XX network processors enable fast deployment of complete content processing by
providing unlimited programming flexibility, code re-use, and high-performance processing. These
network processors support a wide variety of WAN and LAN applications that require a broad
range of speeds, currently ranging from OC-3 through OC-192. High performance and scalability
is achieved through an innovative Microengine architecture that includes a multi-threaded
distribution cache architecture that enables pipeline features in software.
In addition to the standard feature set available with the Intel® IXP2800 Network Processor, the
Intel® IXP2850 Network Processor integrates functionality for secure network traffic at
10 Gbytes/sec. This enables the up-front design of secure network equipment and results in lower
power consumption and more efficient use of space on the printed circuit board.
Table 1 summarizes the product features. Figure 1 provides a functional overview of the Intel®
IXP2800 Network Processor and Intel® IXP2850 Network Processor internal hardware, showing
the major internal blocks.

12 Hardware Design Guide
IXP28XX Network Processor
Introduction
Table 1. Product Features of IXP28XX Network Processors
Feature Description
Sixteen integrated Microengines
(Version 2)
• Operating frequency of up to 1.4 GHz
• Configurable to four or eight threads per Microengine
• 640 Dwords of local memory per Microengine
• Sixteen-entry CAM per Microengine, with single cycle lookup
• Next Neighbor bus accessing adjacent Microengines
• CRC unit per Microengine
• 8K instructions control store per Microengine
• Support for Generalized Thread Signaling
Integrated Intel XScale® core
• Operating frequency of up to 700 MHz
• High performance, low power 32-bit embedded RISC processor
• 32-Kbyte instruction cache
• 32-Kbyte data cache
Two integrated Cryptographic
units (Intel® IXP2850 Network
Processor only)
• Operating frequency of 700 MHz
• Support for DES, 3DES, AES, and SHA-1 algorithms
• Support for AES 128-, 192-, and 256-bit keys
Threeindustry-standardRDRAM
interfaces
• Peak bandwidth of 2.1 Gbytes/sec
• 800-MHz and 1066-MHz RDRAM
• Error Correction Code (ECC)
• Addressable from Intel XScale®core, Microengines, and PCI
Four industry-standard 32-bit
QDR SRAM interfaces
• Peak bandwidth of 1.9 Gbytes/sec per channel
• 233-MHz SRAM
• Hardware support for Linked List and Ring operations
• Atomic bit operations
• Atomic arithmetic support
• Addressable from Intel XScale®core, Microengines, and PCI
Integrated Media Switch Fabric
interface
• Two unidirectional 16-bit Low-Voltage Differential Signaling (LVDS)
data interfaces
• Up to 500 MHz per channel
• Separately configurable for either SPI-4 or CSIX protocols
Industry-standard PCI Bus •PCI Local Bus Specification, Version 2.2* interface for 64-bit, 66-MHz
I/O
Additional integrated features
• Hardware Hash Unit (48-, 64-, and 128-bit)
• 16-KByte Scratchpad Memory
• Serial UART port for debug
• Eight general-purpose I/O pins
• Four 32-bit timers
1356 Ball FCBGA package • Dimensions of 37.5mm x 37.5mm
• 1 mm solder ball pitch

Hardware Design Guide 13
IXP28XX Network Processor
Introduction
1.2 In This Guide
This document comprises the following chapters and appendixes that describe the IXP28XX
network processor:
•Chapter 2, “Power Ratings and Requirements,” describes the minimum and maximum
operating voltages and temperatures.
•Chapter 3, “RDRAM,” describes the IXP28XX network processor’s Rambus* DRAM
implementation.
•Chapter 4, “QDR SRAM,” describes the IXP28XX network processor’s four independent
SRAM controllers, each of which supports pipelined QDR synchronous static RAM (SRAM).
•Chapter 5, “MSF (SPI-4/CSIX/FC),” describes the Media and Switch Fabric (MSF) interface.
•Chapter 6, “PCI,” describes the use of the PCI controller to provide a 64-bit, 66-MHz-capable
PCI Local Bus Specification, Version 2.2* interface for the IXP28XX network processor.
•Chapter 7, “Slowport,” describes the Slowport external interface to the IXP28XX network
processor.
•Chapter 8, “Mechanical/Packaging,” describes the dimensions of the IXP28XX network
processor and package markings for the processor chip.
Figure 1. IXP2800/IXP2850 Network Processor Functional Block Diagram
B0564-02
Media
Switch
Fabric
(MSF)
Scratched
Memory
SRAM
Controller
0
SRAM
Controller
1
SRAM
Controller
2
SRAM
Controller
3
DRAM
Controller
0
DRAM
Controller
1
DRAM
Controller
2
Hash
Unit
Crypto
0
Crypto
1
Intel® IXP2850
Network Processor
Only
PCI Controller
CAP
ME Cluster 0
ME
0x1
ME
0x0
ME
0x2
ME
0x3
ME
0x5
ME
0x4
ME
0x6
ME
0x7
ME Cluster 1
ME
0x10
ME
0x11
ME
0x13
ME
0x12
ME
0x14
ME
0x15
ME
0x17
ME
0x16
Intel
XScale
®
Core
Peripherals
(XPI)
Intel
XScale
®
Core
Performance
Monitor

14 Hardware Design Guide
IXP28XX Network Processor
Introduction
1.2.1 Typographical Conventions
This guide contains the following text and typography conventions:
1.2.2 Acronyms and Terminology
Table 3 defines the acronyms and terminology that are used throughout this document.
Table 2. Guide Conventions
Convention Description
Italics New terms and titles of documents or help systems appear in italics.
bold Special text for labels of items appears in bold type.
monospace Code and names of drives, pathnames, directories, and filenames appear in
Courier monospace type.
monospace bold Example commands given to show user input.
table of contents
table of figures
table of tables Each item in the tables of contents, figures, and tables is a hyperlink.
>Indicates the sequential choice of menu items. For example, the menu items for
the Developers Workbench are Start > IXA SDK 4.1 > DevWorkbench.
Table 3. Acronyms and Terminology (Sheet 1 of 3)
Acronym/Terminology Definition
AES Advanced Encryption Standard
ATM Asynchronous Transfer Mode
BGA ball grid array
BWE Byte Write Enable, a type of control signal that is active low
CFM Clock-to-Master, positive polarity
CFMN Clock-to-Master, negative polarity
Clamshelling Locating two devices on opposite sides of the printed circuit board
cPCI Compact PCI, a 32- or 64-bit bus, operating at either 33 or 66 MHz
CPIX Common Programming Interface Forum
CSIX Common Switch Interface
CPLD Complex Programmable Logic Device
CSR Control Status Register
CTM Clock-to-Master, positive polarity
CTMN Clock-to-Master, negative polarity
DDR Double Data Rate
DES Data Encryption Standard
DLL Dynamic Link Library
DMA Direct Memory Access
DRAM Dynamic Random Access Memory

Hardware Design Guide 15
IXP28XX Network Processor
Introduction
DRCG Direct Rambus* Clock Generator
ECC Error Correction Code
EEPROM Electrically Erasable Programmable Read-only Memory
LVDS Low-Voltage Differential Signaling
MAC Medium Access Control, a 48-bit number unique to each LAN network interface
card (NIC)
MSF Media Switch Fabric
NA Not applicable
NIC Network Interface Card
NPF Network Processor Forum; organized to facilitate the development of next- generation networking and telecommunications products based on network
processing technologies
OIF Optical Internetworking Forum
PCB Printed circuit board
PCI Peripheral Component Interconnect
PHY physical layer device
PGA pin grid array
PLL Phase Lock Loop
POS Packet over SONET
PPCI Primary PCI, a 64-bit PCI bus operating at 33 or 66 MHz. This bus connects the ingress and egress IXP28XX network processor to the master and slave PCI-PCI
bridge chips.
PVT Process/Voltage/Temperature
QDR SRAM Quad Data Rate Static Random Access Memory
RDRAM Rambus* Dynamic Random Access Memory
RIMM* Rambus* In-line Memory Module used with RDRAM chips developed by
Rambus, Inc.
RPE Read Port Enable, a type of control signal that is active low
RSL Rambus* Signaling Level
SDH Synchronous Digital Hierarchy, a set of international fiber optic transmission
standards
SF Switch Fabric
SHA-1 Secure Hash Algorithm 1
SPCI Secondary PCI, a 32-bit bus operating at 33 MHz
SPI-4
Interface for packet and cell transfer between a physical layer (PHY) device and
a link layer device (the IXP28XX network processor), for aggregate bandwidths of
OC-192 ATM and Packet over SONET/SDH (POS), as well as 10 Gb/s Ethernet
applications.
Striping
Hardware interleaving of addresses to provide balanced access to all populated
channels; the interleave size is 128 bytes. Interleaving helps to maintain
utilization of available bandwidth by spreading consecutive accesses to multiple
channels. The interleaving is done in the hardware so that the three channels
appear to software as a single contiguous memory space.
Table 3. Acronyms and Terminology (Sheet 2 of 3)
Acronym/Terminology Definition

16 Hardware Design Guide
IXP28XX Network Processor
Introduction
1.3 Related Documentation
Refer to the following documents or models for more information. All Intel-issued documentation
revision numbers are subject to change, and the latest revision should be used. The specific
revision numbers referenced should be used for all documents not released by Intel. Contact your
field representative for information on obtaining Intel-issued documentation.
•Intel® IXP2800 Network Processor Thermal/Mechanical Design Guideline Application Note
•Intel® IXP2800 and Intel® IXP2850 Network Processors Datasheet
•Intel® IXP2800 Network Processor Hardware Reference Manual
•Intel® IXP2800 Network Processor Hardware Initialization Reference Manual
•Intel® IXP2800 and Intel® IXP2850 Network Processors Interfacing Devices to the Slowport
Application Note
•Intel® IXP2800 Network Processor Electrical, Mechanical, and Thermal Specification (EMTS)
Application Note
•Intel® IXP2800 Network Processor IBIS Model
•Intel® IXP2800 Network Processor BSDL File
•PCI Local Bus Specification, Version 2.2*
1.4 Contacting Intel®
TCAM Ternary Content Addressable Memory
TM Traffic Manager
UART Universal Asynchronous Receiver-Transmitter
VOQ Virtual output queue
VRM Voltage Regulator Module
WPE Write Port Enable, a type of control signal that is active low
Table 3. Acronyms and Terminology (Sheet 3 of 3)
Acronym/Terminology Definition
Networking and Communications Building
Blocks Site http://www.intel.com/design/network
Intel Internet Exchange Architecture Site http://www.intel.com/IXA
Other Intel Support http://developer.intel.com/design/litcentr
Intel Literature Center [phone] 7 a.m. to 7 p.m. CST (U.S. and Canada)
International locations please contact your local sales office.
General Information Hotline [phone] or [phone] 5 a.m. to 5 p.m. PST

Hardware Design Guide 17
IXP28XX Network Processor
Power Ratings and Requirements
Power Ratings and Requirements 2
The following sections describe power ratings and requirements for the Intel®IXP2800 and Intel®
IXP2850 Network Processors.
2.1 Power Ratings
Operation beyond the functional operating temperature range (see Table 5) is not recommended
and extended exposure beyond this range may affect reliability. Table 7 and Table 8 list the
functional operating voltage ranges; Table 9 through Table 11 provide example power values.
Note: Under all operating conditions, the 3.3 V – 1.35/1.3/1.2 V and 3.3 V – 2.5 V supply voltage
difference (VDELTA) must not be exceeded; otherwise, permanent damage to the device may result.
Also, the Core/PLL supply voltage must never be less than 1.1 V (see Table 4).
Table 4. Absolute Maximum/Minimum Ratings Table
Parameter Minimum Maximum Comment
Junction Temp Tj (Commercial) — 120°C
Junction Temp Tj (Extended) — 120°C
Storage Temperature Range -55°C125°C
Supply Voltage Difference VDELTA — 2.7 V • 3.3 V to 2.5 V rail difference
• 3.3 V to 1.35/1.3/1.2 V rail
difference
VCORE (1.35/1.3 V) Minimum
Operating Voltage 1.1 V —
VCORE (1.2 V) Minimum Operating
Voltage 1.1 V —
Maximum power-up time — 700 ms It is expected that all supplies will be up
and stable within 700 milliseconds.
Table 5. Functional Operating Temperature Range
Parameter Minimum Maximum Comment
Commercial temperature operating
range 0° C 70° C Refer to the Intel®IXP2800 Network
Processor Thermal/Mechanical
Design Guideline Application Note.
Extended temperature operating range -40° C 85° C Refer to the Intel® IXP2800 Network
Processor Thermal/Mechanical
Design Guideline Application Note.
Maximum Junction Temperature
(Extended) — 120° C Refer to the Intel®IXP2800 Network
Processor Thermal/Mechanical
Design Guideline Application Note.
Maximum Junction Temperature
(Commercial) — 120° CRefer to the Intel® IXP2800 Network
Processor Thermal/Mechanical
Design Guideline Application Note.

18 Hardware Design Guide
IXP28XX Network Processor
Power Ratings and Requirements
Table 6. Typical and Maximum Power1
1. The maximum power parameters represent the worst-case power consumption as measured by running the Intel packet
over SONET (POS) reference design processing minimum-size packets (49 bytes) running at full OC-192 line rate.
Device2
2. Total power.
Typical Maximum Frequency
IXP2800 - Bn3
3. Bnrefers to B0 and B1.
25.5 W 31.5 W 1.4 GHz
IXP2800 - Bn18.5 W 23 W 1.0 GHz
IXP2800 - Bn12.5 W 16 W 650 MHz
IXP2850 - Bn27.5 W 34 W 1.4 GHz
IXP2850 - Bn20.5 W 25 W 1.0 GHz
IXP2850 - Bn14 W 17.5 W 650 MHz

Hardware Design Guide 19
IXP28XX Network Processor
Power Ratings and Requirements
Table 7. Functional Operating Voltage Range – 1.4/1.0 GHz
Interface Supply Name Description Voltage (V) Tolerance
(+/-%) Notes
1,2,3,4,5
1. These supplies can be derived from core Vcc, but should be filtered appropriately.
2. QDR references should be derived from Vddq so that they track fluctuations in Vddq.
3. During power-up, after NRESET is de-asserted, the device will experience an increase in current consumption after the PLL
locks and the system clocks begin to operate at full speed. During this time a droop on the core power supply may occur due
to this increase in current consumption. It is acceptable that the core power supply droop a maximum of 100 mV to a minimum
of 1.2 V during this time. It is expected that the device be Idle during this time and that no instructions be executing until the
power is within the 5% regulation specification. The behavior is undefined if instructions are executed while the power is not
within the 5% regulation specification.
4. SPI-4 reference should be derived from VCC25V so that they track fluctuations in VCC25V.
5. The tolerance on the PCI supply is tighter than specified in the PCI Local Bus Specification, Version 2.2*.
Core VCC
VSS Core power supply Core ground 1.3 V GND 5% N/A 3
Clock/PLL
VCC_PLL
VSS
VCC_CLK
VREFHI_CLK
VREFLO_CLK
PLL power
PLL ground
Ref. Clock power (also for
GPIO)
Clock reference voltage
Clock reference voltage
1.3 V
GND
2.50 V
1.40 V
1.00 V
5%
N/A
5%
5%
5%
1,3
SPI-4/CSIX/F
LOW
VCC25V
VCCA_FC
VCCA_SPI4
VREFHI
VREFLO
SPI-4 supply (also for PCI)
DLL power
DLL power
SPI-4/flow reference voltage
SPI-4/flow reference voltage
2.50 V
1.3 V
1.3 V
1.40 V
1.00 V
5%
5%
5%
5%
5%
1
1
4
4
GPIO VCC33 GPIO, JTAG, SP power 3.30 V 5%
PCI VCC33_PCI PCI power supply 3.30 V 5% 5
QDR
VDDQ
PAS0_VCCA
PAS1_VCCA
PAS2_VCCA
PAS3_VCCA
VREF_QDR0
VREF_QDR1
VREF_QDR2
VREF_QDR3
QRD power supply
DLL power
DLL power
DLL power
DLL power
QDR reference voltage
QDR reference voltage
QDR reference voltage
QDR reference voltage
1.50 V
1.3 V
1.3 V
1.3 V
1.3 V
0.75 V
0.75 V
0.75 V
0.75 V
1.4 V to 1.6 V
5%
5%
5%
5%
0.7 V to 0.85 V
0.7 V to 0.85 V
0.7 V to 0.85 V
0.7 V to 0.85 V
1
1
1
1
2
2
2
2
RDR
VCCR
VCCRA
VCCRIO
PAR0_PADVREFA
PAR0_PADVREFB
PAR1_PADVREFA
PAR1_PADVREFB
PAR2_PADVREFA
PAR2_PADVREFB
RDRAM core processor
RDRAM clean power
RDRAM I/O power
RDRAM reference voltage
RDRAM reference voltage
RDRAM reference voltage
RDRAM reference voltage
RDRAM reference voltage
RDRAM reference voltage
1.3 V
1.3 V
1.80 V
1.40 V
1.40 V
1.40 V
1.40 V
1.40 V
1.40 V
5%
5%
1.7 V to 1.9 V
1.2 V to 1.6 V
1.2 V to 1.6 V
1.2 V to 1.6 V
1.2 V to 1.6 V
1.2 V to 1.6 V
1.2 V to 1.6 V
1
FUSE VCC_FUSE Fuse power supply 1.3 V 5%

20 Hardware Design Guide
IXP28XX Network Processor
Power Ratings and Requirements
Table 8. Functional Operating Voltage Range – 650 MHz
Interface Supply Name Description Voltage (V) Tolerance
(+/-%) Notes
1,2,3,4
1. These supplies can be derived from core Vcc, but should be filtered appropriately.
2. QDR references should be derived from Vddq so that they track fluctuations in Vddq.
3. SPI-4 reference should be derived from VCC25V so that they track fluctuations in VCC25V.
4. The tolerance on the PCI supply is tighter than specified in the PCI Local Bus Specification, Version 2.2*.
Core VCC
VSS Core power supply Core ground 1.2 V GND 5% N/A
Clock/PLL
VCC_PLL
VSS
VCC_CLK
VREFHI_CLK
VREFLO_CLK
PLL power
PLL ground
Ref. Clock power (also for
GPIO)
Clock reference voltage
Clock reference voltage
1.2 V
GND
2.50 V
1.40 V
1.00 V
5%
N/A
5%
5%
5%
1
SPI-4/CSIX/F
LOW
VCC25V
VCCA_FC
VCCA_SPI4
VREFHI
VREFLO
SPI-4 supply (also for PCI)
DLL power
DLL power
SPI-4/flow reference voltage
SPI-4/flow reference voltage
2.50 V
1.2 V
1.2 V
1.40 V
1.00 V
5%
5%
5%
5%
5%
1
1
3
3
GPIO VCC33 GPIO, JTAG, SP power 3.30 V 5%
PCI VCC33_PCI PCI power supply 3.30 V 5% 4
QDR
VDDQ
PAS0_VCCA
PAS1_VCCA
PAS2_VCCA
PAS3_VCCA
VREF_QDR0
VREF_QDR1
VREF_QDR2
VREF_QDR3
QRD power supply
DLL power
DLL power
DLL power
DLL power
QDR reference voltage
QDR reference voltage
QDR reference voltage
QDR reference voltage
1.50 V
1.2 V
1.2 V
1.2 V
1.2 V
0.75 V
0.75 V
0.75 V
0.75 V
1.4 V to 1.6 V
5%
5%
5%
5%
0.7 V to 0.85 V
0.7 V to 0.85 V
0.7 V to 0.85 V
0.7 V to 0.85 V
1
1
1
1
2
2
2
2
RDR
VCCR
VCCRA
VCCRIO
PAR0_PADVREFA
PAR0_PADVREFB
PAR1_PADVREFA
PAR1_PADVREFB
PAR2_PADVREFA
PAR2_PADVREFB
RDRAM core processor
RDRAM clean power
RDRAM I/O power
RDRAM reference voltage
RDRAM reference voltage
RDRAM reference voltage
RDRAM reference voltage
RDRAM reference voltage
RDRAM reference voltage
1.2 V
1.2 V
1.80 V
1.40 V
1.40 V
1.40 V
1.40 V
1.40 V
1.40 V
5%
5%
1.7 V to 1.9 V
1.2 V to 1.6 V
1.2 V to 1.6 V
1.2 V to 1.6 V
1.2 V to 1.6 V
1.2 V to 1.6 V
1.2 V to 1.6 V
1
FUSE VCC_FUSE Fuse power supply 1.2 V 5%