Intel SL6VU - Celeron 2.40GHz 400MHz 128KB Socket 478... User manual

Intel®Celeron®Processor in the
478-Pin Package
Specification Update
October 2006
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Notice: The Intel®Celeron®Processor in the 478-Pin Package may contain design
defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are documented in this
Specification Update.
Document Number: 290749-030

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2 Intel®Celeron®Processor in the 478-Pin Package Specification Update
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL®PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL
DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR
WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT,
COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining
applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel®Celeron®Processor in the 478-Pin Package may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
The Specification Update should be publicly available following the last shipment date for a period of time equal to the specific product’s warranty
period. Hardcopy Specification Updates will be available for one (1) year following End of Life (EOL). Web access will be available for three (3)
years following EOL.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Celeron Pentium, Intel Xeon, and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United
States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2003–2005, Intel Corporation

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Intel®Celeron®Processor in the 478-Pin Package Specification Update 3
Contents
Revision History..................................................................................................................4
Preface................................................................................................................................6
Summary Tables of Changes .............................................................................................8
General Information ..........................................................................................................14
Component Identification Information...............................................................................15
Errata.................................................................................................................................19
Specification Changes ......................................................................................................46
Specification Clarifications................................................................................................47
Documentation Changes ..................................................................................................50
§

Revision History
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4 Intel®Celeron®Processor in the 478-Pin Package Specification Update
Revision History
Version Description Date
-001 Initial release. May 2002
-002 Added erratum AC35. Added Documentation Changes AC4- AC5.
Updated processor identification information table. June 2002
-003 Added erratum AC37. Added Documentation Changes AC3- AC12. July 2002
-004 Updated with Intel®Celeron®Processor on 0.13 Micron Process and in
the 478-Pin Package. Added erratum AC38. Updated Erratum AC17.
Added Documentation Changes AC3- AC24.
September
2002
-005 Added erratum AC39. Added Documentation Changes AC25- AC32. October 2002
-006 Added Erratum AC40. Added Spec Change V1. Added Documentation
Changes AC1- AC10. Updated processor identification information table. November 2002
-007 Added Erratum AC41. January 2003
-008 Added Erratum AC42. February 2003
-009 Updated Erratum AC41. Added erratum AC43.
Updated processor identification information table March 2003
-010 Added Specification clarification AC1. Updated processor identification
information table. Added Errata AC44 and AC45. May 2003
-011 Updated processor identification information table. Updated Erratum
AC40. June 2003
-012 Updated processor identification information table. Added D1 step
update. June 2003
-013 Added Erratum AC46, AC47 and AC49. Updated processor identification
information table. August 2003
-014 Added Erratum AC49, AC50 and AC51. Updated processor identification
information table. September 2003
-015 Updated Erratum AC51. Updated processor identification information
table. November 2003
-016 Added Errata AC52- AC56. March 2004
-017 Updated Erratum AC16. Added Erratum AC57. April 2004
-018 Removed Errata that were previously called AC54 & AC55. Added Errata
AC56 and AC57. June 2004
-019 Updated Erratum AC11 & added Erratum AC58. August 2004
-020 Added Errata AC59- AC61. September
2004
-021 Added Erratum AC62- AC63 October 2004
-022 Updated processor identification information table. Added Erratum V64 November
2004

Revision History
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Intel®Celeron®Processor in the 478-Pin Package Specification Update 5
Version Description Date
-023 Added Erratum AC65 December
2004
-024 •Added specification clarification AC1. April 2005
-025 •Changed the Errata ID tag from “V” to “AC”. Updated Summary table of
changes. Updated Microcode Update Guide and .PDB file guide.
Added Erratum AC66.
October 2005
-026 •Updated erratum AC40. January 2006
-027 •Updated document numbers for Software Developers Manuals. March 2006
-028 •Added erratum AC67 and AC68. Updated Summary Table of Changes. April 2006
-029 •Added erratum AC69. Updated Summary Table of Changes. June 2006
-030 •Updated the names of the Software Developer Manuals. Updated
Summary Table of Changes. Updated Links. October 2006

Preface
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6 Intel®Celeron®Processor in the 478-Pin Package Specification Update
Preface
This document is an update to the specifications contained in the documents listed in the
following Affected Documents/Related Documents table. It is a compilation of device and
document errata and specification clarifications and changes, and is intended for hardware system
manufacturers and for software developers of applications, operating system, and tools.
Information types defined in the Nomenclature section of this document are consolidated into this
update document and are no longer published in other documents. This document may also
contain information that has not been previously published.
Affected Documents
Document Title Document Number
Intel®Celeron®Processor in the 478-Pin Package up to 1.80 GHz
Datasheet http://developer.intel.com/design/ celeron/datashts/251748.htm
Intel®Celeron®Processor on 0.13 Micron Process in the 478-Pin
Package http://developer.intel.com/support /processors/celeron/478/
Related Documents
Document Title Document Number
Intel® 64 and IA-32 Intel® Architectures Software Developer's
Manual, Volume 1: Basic Architecture 253665
Intel® 64 and IA-32 Intel® Architectures Software Developer's
Manual, Volume 2A: Instruction Set Reference, A-M 253666
Intel® 64 and IA-32 Intel® Architectures Software Developer's
Manual, Volume 2B: Instruction Set Reference, N-Z 253667
Intel® 64 and IA-32 Intel® Architectures Software Developer's
Manual, Volume 3A: System Programming Guide 253668
Intel® 64 and IA-32 Intel® Architectures Software Developer's
Manual, Volume 3B: System Programming Guide 253669

Preface
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Intel®Celeron®Processor in the 478-Pin Package Specification Update 7
Nomenclature
S-Spec Number is a five-digit code used to identify products. Products are differentiated by their
unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the
processor identification information table. Care should be taken to read all notes associated with
each S-Spec number
Errata are design defects or errors. Errata may cause the Intel®Celeron®processor in the 478-pn
package behavior to deviate from published specifications. Hardware and software designed to be
used with any given stepping must assume that all errata documented for that stepping are present
on all devices.
Specification Changes are modifications to the current published specifications. These changes
will be incorporated in the next release of the specifications.
Specification Clarifications describe a specification in greater detail or further highlight a
specification’s impact to a complex design situation. These clarifications will be incorporated in
the next release of the specifications.
Documentation Changes include typos, errors, or omissions from the current published
specifications. These changes will be incorporated in the next release of the specifications.

Summary Tables of Changes
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8 Intel®Celeron®Processor in the 478-Pin Package Specification Update
Summary Tables of Changes
The following table indicates the Specification Changes, Errata, Specification Clarifications, or
Documentation Changes that apply to the listed component steppings. Intel intends to fix some of
the errata in a future stepping of the component, and to account for the other outstanding issues
through documentation or Specification Changes as noted. This table uses the following
notations:
Codes Used in Summary Table
Stepping
X: Erratum, Specification Change or Clarification that applies
to this stepping.
(No mark) or (Blank Box): This erratum is fixed in listed stepping or specification
change does not apply to listed stepping.
Status
Doc: Document change or update that will be implemented.
PlanFix: This erratum may be fixed in a future stepping of the
product.
Fixed: This erratum has been previously fixed.
NoFix: There are no plans to fix this erratum.
PKG: This column refers to errata on the Celeron processor in
the 478-pin package substrate
AP: APIC related erratum.
Shaded: This item is either new or modified from the previous
version of the document.

Summary Tables of Changes
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Intel®Celeron®Processor in the 478-Pin Package Specification Update 9
Note: Each Specification Update item is prefixed with a capital letter to distinguish the product. The key
below details the letters that are used in Intel’s microprocessor Specification Updates:
A = Dual-Core Intel® Xeon® processor 7000 sequence
B = Mobile Intel ® Pentium ® II processor
C = Intel ® Celeron ® processor
E = Intel ® Pentium ® III processor
F = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor
G = Intel ® Pentium ® III Xeon™ processor
H = Mobile Intel ® Celeron ® processor at 466/433/400/366/333/300 and 266 MHz
J = 64-bit Intel® Xeon™ processor MP with 1MB L2 Cache
K = Mobile Intel ® Pentium ® III processor
L = Intel ® Celeron ® D processor
M = Mobile Intel ® Celeron ® processor
N = Intel ® Pentium ® 4 processor
O = Intel ® Xeon™ processor MP
P = Intel ® Xeon™ processor
Q = Mobile Intel®Pentium®4 processor supporting Hyper-Threading Technology on 90-
nm process technology
R = Intel® Pentium® 4 processor on 90 nm process
S = 64-bit Intel® Xeon™ processor with 800 MHz system bus (1 MB and 2 MB L2
cache versions)
T = Mobile Intel® Pentium® 4 processor-M
V = Mobile Intel® Celeron® processor on .13 Micron Process in Micro-FCPGA
Package
W= Intel® Celeron® M processor
X = Intel®Pentium®M processor on 90nm process with 2-MB L2 Cache
Y = Intel® Pentium® M processor
Z = Mobile Intel ® Pentium ® 4 processor with 533 MHz system bus
AA = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor on
65nm
AB = Intel®Pentium®4 processor on 65 nm process
AC = Intel®Celeron®processor in 478 Pin Package
AD = Intel® Celeron® D processor on 65nm process
AE = Intel® CoreTM Duo Processor and Intel® CoreTM Solo processor on 65nm process
AF = Dual-Core Intel® Xeon® processor LV
AG = Dual-Core Intel® Xeon® Processor 5100 Series
AH = Intel® Core™2 Duo mobile processor
AI = Intel® Core™2 Extreme Processor X6800Δand Intel® Core™2 Duo Desktop
Processor E6000ΔSequence
AL = Dual-Core Intel® Xeon® Processor 7100 Series
NO. E0 nC1 nD1 Plans ERRATA
AC1 X X X NoFix
I/O restart in SMM may fail after simultaneous machine check
exception (MCE)
AC2 X X X NoFix
MCA registers may contain invalid information if RESET#
occurs and PWRGOOD is not held asserted

Summary Tables of Changes
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10 Intel®Celeron®Processor in the 478-Pin Package Specification Update
NO. E0 nC1 nD1 Plans ERRATA
AC3 X Fixed
Uncacheable (UC) code in same line as write back (WB) data
may lead to data corruption
AC4 X X X NoFix Transaction is not retried after BINIT#
AC5 X X X NoFix Invalid opcode 0FFFh requires a ModRM byte
AC6 X X X NoFix
FSW may not be completely restored after page fault on
FRSTOR or FLDENV instructions
AC7 X X X NoFix
The processor flags #PF instead of #AC on an unlocked
CMPXCHG8B instruction
AC8 X X X NoFix
When in no-fill mode the memory type of large pages are
incorrectly forced to uncacheable
AC9 X X X NoFix
Processor may hang due to speculative page walks to non-
existent system memory
AC10 X Fixed Writing a performance counter may result in incorrect value
AC11 X X X NoFix IA32_MC0_STATUS register overflow bit not set correctly
AC12 X Fixed
Performance counter may contain incorrect value after being
stopped
AC13 X NoFix
MCA error code field in IA32_MC0_STATUS register may
become out of sync with the rest of the register
AC14 X NoFix
The IA32_MC1_STATUS register may contain incorrect
information for correctable errors
AC15 X X X NoFix Debug mechanisms may not function as expected
AC16 X X X NoFix
Machine check architecture error reporting and recovery may
not work as expected
AC17 X Fixed
Processor may timeout waiting for a device to respond after
~0.67 seconds
AC18 X X X NoFix
Cascading of performance counters does not work correctly
when forced overflow is enabled
AC19 X Fixed
IA32_MC1_STATUS MSR ADDRESS VALID bit may be set
when no valid address is available
AC20 X X X NoFix EMON event counting of x87 loads may not work as expected
AC21 X Fixed
Software controlled clock modulation using a 12.5% or 25%
duty cycle may cause the processor to hang
AC22 X Fixed
SQRTPD and SQRTSD may return QnaN indefinite instead of
negative zero
AC23 X X X PlanFix
Bus Invalidate Line requests that return unexpected data may
result in L1 cache corruption
AC24 X X X PlanFix
Write Combining (WC) load may result in unintended address
on system bus
AC25 X Fixed
Incorrect data may be returned when page tables are in Write
Combining (WC) memory space
AC26 X PlanFix Buffer on resistance may exceed specification
AC27 X X X NoFix
Processor issues inconsistent transaction size attributes for
locked operation

Summary Tables of Changes
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Intel®Celeron®Processor in the 478-Pin Package Specification Update 11
NO. E0 nC1 nD1 Plans ERRATA
AC28 X Fixed
Multiple accesses to the same S-state L2 cache line and ECC
error combination may result in loss of cache coherency
AC29 X Fixed Processor may hang when resuming from Deep Sleep state
AC30 X X X NoFix
When the processor is in the System Management Mode
(SMM), debug registers may be fully writeable
AC31 X X X NoFix
Associated counting logic must be configured when using
Event Selection Control (ESCR) MSR
AC32 X X X NoFix
IA32_MC0_ADDR and IA32_MC0_MISC registers will contain
invalid or stale data following a Data, Address, or Response
Parity Error
AC33 X Fixed
CR2 may be incorrect or an incorrect page fault error code
may be pushed onto stack after execution of an LSS
instruction
AC34 X X X NoFix
System may hang if a fatal cache error causes Bus Write Line
(BWL) transaction to occur to the same cache line address as
an outstanding Bus Read Line (BRL) or Bus Read-Invalidate
Line (BRIL)
AC35 X Fixed
Processor Does not Flag #GP on Non-zero Write to Certain
MSRs
AC36 X Fixed L2 cache may contain stale data in the Exclusive state
AC37 X X X NoFix
Simultaneous assertion of A20M# and INIT# may result in
incorrect data fetch
AC38
S X X X NoFix
Glitches on Address and Data Strobe Signals May Cause
System Shutdown
AC39 X Fixed CPUID Returns Incorrect Number of ITLB Entries
AC40 X X X NoFix
A Write to an APIC Register Sometimes May Appear to Have
Not Occurred
AC41 X Fixed
Store to Load Data Forwarding may Result in Switched Data
Bytes
AC42 X X NoFix
Parity Error in the L1 Cache may Cause the Processor to
Hang
AC43 X Fixed
The TCK Input in the Test Access Port (TAP) is Sensitive to
Low Clock Edge Rates and Prone to Noise Coupling Onto
TCK's Rising or Falling Edges
AC44 X X Fixed
Re-mapping the APIC base address to a value less than or
equal to 0xDC001000 may cause IO and Special Cycle failure
AC45 X X Fixed Erroneous BIST result found in EAX register after reset
AC46 X X X NoFix
The State of the Resume Flag (RF Flag) in a Task-State
Segment (TSS) May be Incorrect
AC47 X X X NoFix
Changes to CR3 Register do not Fence Pending Instruction
Page Walks
AC48 X X X NoFix
Processor Provides a 4-Byte Store Unlock After an 8-Byte
Load Lock

Summary Tables of Changes
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12 Intel®Celeron®Processor in the 478-Pin Package Specification Update
NO. E0 nC1 nD1 Plans ERRATA
AC49 X X X NoFix
System Bus Interrupt Messages Without Data Which Receive
aHardFailure Response May Hang the Processor
AC50 X X X NoFix
Memory Type of the Load Lock Different from its
Corresponding Store Unlock
AC51 X X X NoFix
A 16-bit Address Wrap Resulting from a Near Branch (Jump or
Call) May Cause an Incorrect Address to Be Reported to the
#GP Exception Handler
AC52 X X NoFix
ITP Cannot Continue Single Step Execution after the First
Breakpoint
AC53 X X PlanFix
PWRGOOD and TAP Signals Maximum Input Hysteresis
Higher Than Specified
AC54 X X NoFix
Incorrect Debug Exception (#DB) May Occur When a Data
Breakpoint is set on an FP Instruction
AC55 X X X NoFix xAPIC May Not Report Some Illegal Vector Errors
AC56 X PlanFix
A Timing Marginality in the Instruction Decoder Unit May
Cause an Unpredictable Application Behavior and/or System
Hang
AC57 X X X NoFix
Memory Aliasing of Pages as Uncacheable Memory Type and
Write Back (WB) May Hang the System
AC58 X X NoFix
Using STPCLK and Executing Code From Very Slow Memory
Could Lead to a System Hang
AC59 X X X No Fix
Machine Check Exceptions May not Update Last-Exception
Record MSRs (LERs)
AC60 X X No Fix
Stores to Page Tables May Not Be Visible to Pagewalks for
Subsequent Loads Without Serializing or Invalidating the Page
Table Entry
AC61 X PlanFix
A Timing Marginality in the Arithmetic Logic Unit (ALU) May
Cause Indeterminate Behavior
AC62 X X X NoFix
With TF (Trap Flag) Asserted, FP Instruction That Triggers an
Unmasked FP Exception May Take Single Step Trap Before
Retirement of Instruction
AC63 X X X PlanFix
BTS(Branch Trace Store) and PEBS(Precise Event Based
Sampling) May Update Memory outside the BTS/PEBS Buffer
AC64 X X X NoFix
Memory Ordering Failure May Occur with Snoop Filtering
Third Party Agents after Issuing and Completing a BWIL (Bus
Write Invalidate Line) or BLW (Bus Locked Write) Transaction
AC65 X X X NoFix
Control Register 2 (CR2) Can be Updated during a REP
MOVS/STOS Instruction with Fast Strings Enabled
AC66 X X X NoFix
Writing the Local Vector Table (LVT) when an Interrupt is
Pending May Cause an Unexpected Interrupt
AC67 X X X NoFix
Using 2M/4M Pages When A20M# Is Asserted May Result in
Incorrect Address Translations
AC68 X X X NoFix
Writing Shared Unaligned Data that Crosses a Cache Line
without Proper Semaphores or Barriers May Expose a
Memory Ordering Issue

Summary Tables of Changes
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Intel®Celeron®Processor in the 478-Pin Package Specification Update 13
NO. E0 nC1 nD1 Plans ERRATA
AC69 X X X NoFix
Debug Status Register (DR6) Breakpoint Condition Detected
Flags May be set Incorrectly
NO. E0 nC1 nD1 SPECIFICATION CHANGES
No update for this Month
NO. E0 nC1 nD1 SPECIFICATION CLARIFICATIONS
No Update for this month.
NO. E0 nC1 nD1 DOCUMENTATION CHANGES
Refer to Documentation Changes section
§

General Information
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14 Intel®Celeron®Processor in the 478-Pin Package Specification Update
General Information
This section contains top marking information for the Intel®Celeron®processor in the 478-pn
package.
Figure 1. Example Markings for the Intel®Celeron®Processor on 0.13 Micron Process and/or
in the 478-Pin Package
2A GHZ/512/400/1.50V
SYYYY XXXXXX
FFFFFFFF -NNNN
i m
©
‘01
Frequency/Cache/Bus
FPO -
2 GHZ/128/400
FFFFFFFF-
ATPO LOT N
NNNN
im
©
‘03 Frequency/Cache/Bus
S-Spec/Country o
f
AssyS-Spec/Country o
f
Assy
FPO -SYYYY XXXXXX
Celeron®
2-
D Matrix Mark2- D Matrix Mark
§

Component Identification Information
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Intel®Celeron®Processor in the 478-Pin Package Specification Update 15
Component Identification Information
The Intel®Celeron®processor in the 478-pn package processor may be identified by the
following values.
Family1Model2Brand3
1111b 0001b 00001010b
1111b 0010b 00001010b
NOTES:
1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register
after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the
Device ID register accessible through Boundary Scan.
2. The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after
the CPUID instruction is executed with a 1 in the EAX register, and the model field of the Device ID
register accessible through Boundary Scan.
3. The Brand ID corresponds to bits [7:0] of the EBX register after the CPUID instruction is executed with a
1 in the EAX register.
Table 1. Intel®Celeron®Processor in the 478-Pin Package Processor
Identification Information
S-Spec Core Stepping
L2 Cache
Size
(bytes) Processor Signature Speed Core/Bus Package and Revision Notes
SL69Z E0 128K 0F13h 1.70 GHz/
400 MHz FC-PGA2 35.0 mm, Rev
02
1, 2
SL68C E0 128K 0F13h 1.70 GHz/
400 MHz FC-PGA2 35.0 mm, Rev
02
1
SL6A2 E0 128K 0F13h 1.80 GHz/
400 MHz FC-PGA2 35.0 mm, Rev
02
2, 3
SL68D E0 128K 0F13h 1.80 GHz/
400 MHz FC-PGA2 35.0 mm, Rev
02
3
SL6SW C1 128K 0F27h 2 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
2, 4, 8
SL6LC C1 128K 0F27h 2 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
2, 4
SL6HY C1 128K 0F27h 2 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
4

Component Identification Information
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16 Intel®Celeron®Processor in the 478-Pin Package Specification Update
Table 1. Intel®Celeron®Processor in the 478-Pin Package Processor
Identification Information
S-Spec Core Stepping
L2 Cache
Size
(bytes) Processor Signature Speed Core/Bus Package and Revision Notes
SL6RV C1 128K 0F27h 2 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
4, 8, 9
SL6VR D1 128K 0F29h 2 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
4, 8, 9
SL6VY D1 128K 0F29h 2 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
2, 4, 8
SL6RT C1 128K 0F27h 2.10 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
2, 5
SL6RS C1 128K 0F27h 2.10 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
5, 8, 10
SL6VS D1 128K 0F29h 2.10 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
5, 8, 9
SL6SY C1 128K 0F27h 2.10 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
2, 5, 8
SL6VZ D1 128K 0F29h 2.10 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
2, 5, 8
SL6RT C1 128K 0F27h 2.10 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
2, 5, 8
SL6LB C1 128K 0F27h 2.20 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
2, 6
SL6RW C1 128K 0F27h 2.20 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
6, 8
SL6SX C1 128K 0F27h 2.20 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
6, 8, 9
SL6LB C1 128K 0F27h 2.20 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
2, 6, 8
SL6VT D1 128K 0F29h 2.20 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
6, 8, 9

Component Identification Information
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Intel®Celeron®Processor in the 478-Pin Package Specification Update 17
Table 1. Intel®Celeron®Processor in the 478-Pin Package Processor
Identification Information
S-Spec Core Stepping
L2 Cache
Size
(bytes) Processor Signature Speed Core/Bus Package and Revision Notes
SL6W2 D1 128K 0F29h 2.20 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
2, 6, 8
SL6XJ C1 128K 0F27h 2.30 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
6, 8
SL6WC D1 128K 0F29h 2.30 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
6, 8, 9
SL6WD D1 128K 0F29h 2.30 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
2, 6, 8
SL6T2 C1 128K 0F27h 2.30 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
2, 6
SL6T5 C1 128K 0F27h 2.30 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
2, 6, 8
SL6VU C1 128K 0F27h 2.40 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
7, 8
SL6W4 D1 128K 0F29h 2.40 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
2, 7, 8
SL6XG C1 128K 0F27h 2.40 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
7, 8, 9
SL6V2 C1 128K 0F27h 2.40 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
7, 8
SL6VU D1 128K 0F29h 2.40 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
7, 8
SL6ZY D1 128K 0F29h 2.50 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
8
SL72B D1 128K 0F29h 2.50 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
2, 8, 11
SL6W5 C1 128K 0F27h 2.60 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
2, 8, 11

Component Identification Information
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18 Intel®Celeron®Processor in the 478-Pin Package Specification Update
Table 1. Intel®Celeron®Processor in the 478-Pin Package Processor
Identification Information
S-Spec Core Stepping
L2 Cache
Size
(bytes) Processor Signature Speed Core/Bus Package and Revision Notes
SL6VV C1 128K 0F27h 2.60 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
8, 11
SL77U D1 128K 0F29h 2.70 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
2, 8
SL77S D1 128K 0F29h 2.70 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
8
SL77T D1 128K 0F29h 2.80 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
8, 9
SL77V D1 128K 0F29h 2.80 GHz/
400 MHz FC-PGA2 31.0 mm , rev
1.0
2, 8
SL7EZ D1 128K 0F29h 1.60GHz/400MHz
31.0 mm FC,
Rev 1.0 2,8
SL7RU D1 128K 0F29h 1.80GHz/400MHz
31.0 mm FC,
Rev 1.0 2,8
NOTES:
1. This processor has maximum Tcase of 76 °C
2. This is a boxed processor with an unattached fan heatsink.
3. This processor has maximum Tcase of 77 °C.
4. This processor has maximum Tcase of 68 °C
5. This processor has maximum Tcase of 69 °C
6. This processor has maximum Tcase of 70 °C
7. This processor has maximum Tcase of 71 °C
8. This part has Multiple VID
9. Some of these processors are offered as boxed processors with an unattached fan heatsink
10. This is a Desktop product only
11. This processor has maximum Tcase of 72 °C
§

Errata
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Intel®Celeron®Processor in the 478-Pin Package Specification Update 19
Errata
AC1. I/O Restart in SMM May Fail after Simultaneous Machine Check Exception
(MCE)
Problem: If an I/O instruction (IN, INS, REP INS, OUT, OUTS, or REP OUTS) is being executed, and if
the data for this instruction becomes corrupted, the processor will signal a Machine Check
Exception (MCE). If the instruction is directed at a device that is powered down, the processor
may also receive an assertion of SMI#. Since MCEs have higher priority, the processor will call
the MCE handler, and the SMI# assertion will remain pending. However, upon attempting to
execute the first instruction of the MCE handler, the SMI# will be recognized and the processor
will attempt to execute the SMM handler. If the SMM handler is completed successfully, it will
attempt to restart the I/O instruction, but will not have the correct machine state, due to the call to
the MCE handler.
Implication: A simultaneous MCE and SMI# assertion may occur for one of the I/O instructions above. The
SMM handler may attempt to restart such an I/O instruction, but will have an incorrect state due
to the MCE handler call, leading to failure of the restart and shutdown of the processor.
Workaround: If a system implementation must support both SMM and board I/O restart, the first thing the
SMM handler code should do is check for a pending MCE. If there is an MCE pending, the SMM
handler should immediately exit via an RSM instruction and allow the MCE handler to execute. If
there is no MCE pending, the SMM handler may proceed with its normal operation.
Status: For the steppings affected, see the Summary Tables of Changes.
AC2. MCA Registers May Contain Invalid Information If RESET# Occurs and
PWRGOOD Is Not Held Asserted
Problem: This erratum can occur as a result either of the following events:
•PWRGOOD is de-asserted during a RESET# assertion causing internal glitches that may
result in the possibility that the MCA registers latch invalid information.
•Or, during a reset sequence if the processor’s power remains valid regardless of the state of
PWRGOOD, and RESET# is re-asserted before the processor has cleared the MCA registers,
the processor will begin the reset process again but may not clear these registers.
Implication: When this erratum occurs, the information in the MCA registers may not be reliable.
Workaround: Ensure that PWRGOOD remains asserted throughout any RESET# assertion and that RESET# is
not re-asserted while PWRGOOD is de-asserted.
Status: For the steppings affected, see the Summary Tables of Changes.

Errata
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20 Intel®Celeron®Processor in the 478-Pin Package Specification Update
AC3. Uncacheable (UC) Code in Same Line As Write Back (WB) Data May Lead to
Data Corruption
Problem: When both code (being accessed as UC or WC) and data (being accessed as WB) are aliased into
the same cache line, the UC fetch will cause the processor to self-snoop and generate an implicit
writeback. The data supplied by this implicit writeback may be corrupted due to the way the
processor handles self-modifying code.
Implication: UC or WC code located in the same cache line as WB data may lead to data corruption.
Workaround: UC or WC code should not be located in the same physical 64-byte cache line as any location that
is being stored to with WB data
Status: For the steppings affected, see the Summary Tables of Changes.
AC4. Transaction Is Not Retried after BINIT#
Problem: If the first transaction of a locked sequence receives a HITM# and DEFER# during the snoop
phase it should be retried and the locked sequence restarted. However, if BINIT# is also asserted
during this transaction, it will not be retried.
Implication: When this erratum occurs, locked transactions will unexpectedly not be retried.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AC5. Invalid Opcode 0FFFh Requires a ModRM Byte
Problem: Some invalid opcodes require a ModRM byte (or other following bytes), while others do not. The
invalid opcode 0FFFh did not require a ModRM byte in previous generation Intel® architecture
processors, but does in the Intel® Pentium® 4 processor.
Implication: The use of an invalid opcode 0FFFh without the ModRM byte may result in a page or limit fault
on the Pentium 4 processor.
Workaround: Use a ModRM byte with invalid 0FFFh opcode.
Status: For the steppings affected, see the Summary Tables of Changes.