Intel iAPX 86 User manual

inter
iAPX 86,88 FAMILY UTILITIES
lJSER'S GUIDE
Copyright © 1980, 1981, 1982 Intel Corporation
Intel Corporation, 3065 Bowers Avenue, Santa Clara, California 95051
Order Number: 121616-004

iAPX 86,88 FAnlilLY UTILITIES
USER'S GUIDE
Order Number: 121616-004
Copyright © 1980, 1981, 1982 Intel Corporation
I Intel Corporation, 3065
Bowers Avenue, Santa Clara, CA 95051 I

ii
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to, the implied warranties
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no responsibility for any errors that may appear in this document. Intel Corporation makes no commitment
to update nor to keep
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Intel Corporation assumes
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No other circuit patent licenses are implied.
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The following are trademarks
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products:
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CREDIT Intelevision iSBX
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inteligent Identifier
iSXM
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REV.
REVISION HISTORY
DATE
-001 Original issue. 9/80
-002
Adds information to support V2.0 of LINK86,
11/81
LOC86, and LIB86 and V1.0 of
CREF86; corrects
technical and typographical errors.
-003 Adds examples for
iRMX 86 operating environment.
5/82
-004 Adds examples for Series
IV operating environment.
10/82
iii

I
• rR)
~ ____________________ P_R_E_FA_C~EI
n
This manual describes how to use the iAPX 86,88 Family utilities:
• LINK86
• CREF86
• LIB86
• LOC86
.. OH86
These products run on 8086- and 8088-based systems. They are used by program-
mers developing programs with ASM86, ASM89, PL/M-86, PASCAL-86,
FORTRAN-86, or any other language translator that produces object code compat-
ible with the iAPX 86,88 Family of processors. The iAPX 86,88 Family of pro-
cessors inlcudes 8086, 8088, 8087,
and 8089 processor chips. Because the 8086 is the
first
member of this family, this manual uses 8086 generically to represent the entire
family.
This
manual presumes familiarity with the conventions of the operating system
under which the
iAPX 86,88 utilities are being executed. It also presumes familiarity
with the basic requirements
of individual languages and translators.
This
manual is divided into the following chapters:
• Chapter 1, Introduction: a summary of the relationship among the utilities and
basic concepts governing their use
• Chapter 2, LINK86: how to invoke, use the controls for, and read the printed
listing
from LINK86
• Chapter 3, CREF86: how to invoke, use the controls for, and read the output
listing from CREF86
• Chapter 4, LIB86: how to invoke and use the commands for LIB86
• Chapter 5, LOC86: how to invoke, use the controls for, and read the printed
listing
from LOC86
• Chapter 6, OH86: how to invoke OH86
This manual also contains several appendixes, meant for quick access to the follow-
ing
information:
• iAPX 86,88 absolute object file format definitions (Appendix A)
• Hexadecimal-decimal conversion information (Appendix B)
• The effect of available memory on the performance of LINK86, CREF86,
LIB86, and LOC86 (Appendix C)
•
Summaries of iAPX 86,88 Family utility controls and error messages:
• LINK86 (Appendix D)
• CREF86 (Appendix E)
• LIB86 (Appendix F)
• LOC86 (Appendix G)
• OH86 (Appendix H)
v

vi
NOTE
The following appendixes address issues dependent on specific
operating systems, such as operating environments, related
publications, and examples. These appendixes contain foldout
pages, designed to be opened out to your right and used in conjunc-
tion with general instructions provided in the chapters and other
appendixes. On these foldout pages you will find sample invoca-
tions
for the iAPX 86,88 Family utility controls and commands.
• Additional information for Series III users (Appendix I)
Additional information for iRMX 86 users (Appendix J)
• Additional information for Series IV users (Appendix K)
Once you have gained sufficient familiarity with the basic principles of iAPX 86,88
Family utilities
operation, you will find the following publication convenient for
quick syntax reference:
• iAPX 86,88 Family Utilities Pocket Reference, order number 121669
Before
reading this manual, ensure that you are familiar with the following terms
and conventions.
Notational Conventions
punctuation
{}
[ ]
UPPERCASE
italic
pathname
directory-name
filename
other than the following must be entered if required by the
control syntax.
indicates that one and only one of the syntactic items
contained within the braces is required.
indicates
that the syntactic item or items contained within the
brackets are optional.
indicates that the preceding syntactic item may be repeated an
indefinite number of times. (The ellipsis is often used within
brackets and with a comma "[, ... ]" to indicate that preceding
item
may be repeated, but each repetition must be separated
by a comma.)
separates various options within the brackets [ ] or braces
{ }.
indicates that these characters must be entered exactly as
shown.
indicates a meta symbol that may be replaced with an item
that fulfills the rules for that symbol. The actual symbol may
be any of the following:
is a valid designation for a file; in its entirety, it consists of a
directory-name and a filename.
is that portion of a pathname that acts as a file locator by
identifying the device
and/or directory containing the
filename.
is a valid name for the part of a pathname that names a file.

minimum-size
maximum-size
paragraph
offset
address
segment name
module name
class name
group name
overlayname
public symbol
variable name
-
system-id
pathname1,
pathname2, ...
Vx.y
are numbers and must follow Intel standards for number
representation (see PL/M-86 or ASM86). Use the H suffix for
hexadecimal, B suffix for binary, ° or Qsuffix for octal and
D or nothing for decimal.
are defined by the 8086 object file formats described in
Appendix A. They may be up to forty characters
long and may contain' any of the following characters in any
order:
A, B, C, D, E, F, G, H, I, J, K, L, M, N, 0, P, Q, R, S, T, U, V,
W, X, Y, Z, 0,1,2,3,4,5,6,7,8,9,?, @, :, .,_,
Black background is used in examples to indicate the user's
entries.
is a generic label placed on sample listings where an operating
system-dependent name would actually be printed.
are generic labels placed on sample listings where one or more
user-specified path names would actually be printed.
is a generic label placed on sample listings where the version
number of the product that produced the listing would
actually be printed.
vii

CHAPTER 1
INTRODUCTION
PAGE
Program Development .. "...................... 1-1
Overview of the Utilities ........................ 1-2
External References and Public Symbols ........ 1-2
Use of Libraries ............................. 1-3
Relative Addressing ......................... 1-4
The
LINK86/LOC86 Process ................. 1-4
An 8086 Overview ............................. 1-5
Memory ................................... 1-5
8086 Addressing Techniques .................. 1-5
Segments ........................... '....... 1-6
Segment Alignment
........................ 1-7
Segment Combining ....................... 1-8
Segment Locating ......................... 1-8
Classes .................................... 1-9
Groups .................................... 1-9
Overlays
................................... 1-10
Position-Independent-Code and Load-Time-
Locatable Code ......................... 1-10
CHAPTER 2
LINK86
LINK86 Invocation Line ................ '....... 2-1
LINK86 Controls ..................... "....... 2-2
ASSIGN ........................... "....... 2-4
ASSUMEROOT .................... "....... 2-5
BIND/NOBIND .................... "....... 2-6
COMMENTS/NOCOMMENTS ...... "....... 2-7
FASTLOAD/NOFASTLOAD ................ 2-8
INITCODE ........................ "....... 2-9
LINES/NOLINES .................. " ....... 2-10
MAP/NOMAP ............................. 2-11
MEMPOOL ................................ 2-12
NAME ............................ " ....... 2-13
OBJECTCONTROLS ............... " ....... 2-14
ORDER ................................... 2-15
OVERLAY/NOOVERLAY .......... " ....... 2-16
PRINT INOPRINT .......................... 2-17
PRINTCONTROLS ......................... 2-18
PUBLICS/NOPUBLICS ..................... 2-19
PUBLICSONL Y ............................ 2-20
PURGE/NOPURGE ........................ 2-21
RENAMEGROUPS ......................... 2-22
SEGSIZE .................................. 2-23
SYMBOLS/NOSYMBOLS ................... 2-24
SYMBOLCOLUMNS ....................... 2-25
TYPE/NOTYPE ............................ 2-26
LINK86's Print File ........................... 2-27
The Header ................................ 2-27
The Link Map .............................. 2-27
The Group Map ............................. 2-28
The Symbol Table ........................... 2-29
Error Messages ............................. 2-30
CONTENTS
CHAPTER 3
CREF86
PAGE
CREF86 Invocation Line ...................... .
CREF86 Controls ............................ .
PAGELENGTH ........................... .
PAGEWIDTH ............................ .
PRINT ................................... .
TITLE ................................... .
CREF86's Print File .......................... .
Header ................................... .
Warnings
................................. .
Module List ............................... .
Symbol Cross-Reference
Information
CHAPTER 4
LIB86
3-2
3-2
3-3
3-4
3-5
3-6
3-7
3-7
3-7
3-8
3-8
LIB86
Invocation ............................. 4-1
LIB86 Commands ............................. 4-1
ADD .. '.................................... 4-2
CREATE .................................. 4-3
DELETE .................................. 4-4
EXIT. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-5
LIST ...................................... 4-6
CHAPTER 5
LOC86
LOC86 Invocation Line. . . . . . . . . . . . . . . . . . . . . . . . .. 5-1
LOC86 Controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
ADDRESSES .............................. 5-3
BOOTSTRAP .............................. 5-4
COMMENTS/NOCOMMENTS ......... ".... 5-5
INITCODE/NOINITCODE .................. 5-6
LINES/NOLINES .......................... 5-7
MAP INOMAP ............................. 5-8
NAME .................................... 5-9
OBJECTCONTROLS ....................... 5-10
ORDER ................................... 5-11
PRINT INOPRINT .......................... 5-12
PRINTCONTROLS ......................... 5-13
PUBLICS/NOPUBLICS ..................... 5-14
PURGE/NOPURGE ........................ 5-15
RESERVE ................................. 5-16
SEGSIZE .................................. 5-17
START .................................... 5-18
SYMBOLS/NOSYMBOLS ................... 5-19
SYMBOLCOLUMNS ....................... 5-20
LOC86's Print File ............................ 5-21
The Symbol Table ........................... 5-21
The Memory Map ........................... 5-23
Error and Warning Messages .................. 5-24
LOC86's Algorithm for Locating Segments ........ 5-24
Absolute Segments
... "...................... 5-24
Segment Ordering ........................... 5-24
ix

I • @
n
PAGE
Assigning Addresses to Relocatable Segments .... 5-25
LOC86's Algorithm for Locating Modules
Containing Overlays
....................... 5-25
CHAPTER 6
OH86
APPENDIX A
iAPX 86,88 ABSOLUTE OBJECT
FILE FORMATS
APPENDIX B
HEXADECIMAL-DECIMAL
CONVERSION
APPENDIX C
THE EFFECT OF AVAILABLE
MEMORY ON LINK86, CREF86,
LIB86, AND LOC86
APPENDIX D
LINK86 CONTROLS AND
ERROR MESSAGES
APPENDIX E
CREF86 CONTROLS AND
ERROR MESSAGES
TABLE TITLE
PAGE
2-1
3-1
4-1
5-1
D-l
Summary of LINK86 Controls ..................... 2-2
Summary of CREF86 Controls ..................... 3-2
Summary of LIB86 Commands .................... 4-1
Summary of LOC86 Controls ....................... 5-1
Summary of LINK86 Controls .................... D-l
x
CONTENTS (Cont'd.)
APPENDIX F
LIB86 COMMANDS AND
ERROR MESSAGES
APPENDIX G
lLOC86 CONTROLS AND
ERROR MESSAGES
APPENDIX H
OH86 ERROR MESSAGES
APPENDIX I
ADDITIONAL INFORMATION FOR
l[NTELLEC SERIES III USERS
APPENDIX J
ADDITIONAL INFORMATION FOR
iRMX 86 USERS
APPENDIX K
ADDITIONAL INFORMATION
lFOR SERIES IV USERS
TABLES I
TABLE
lE-l
IF-l
G-l
J-I
TITLE
PAGE
Summary of CREF86 Controls ..................... E-I
Summary of LIB86 Commands .................... F-l
Summary of LOC86 Controls ...................... G-l
iRMX 86 Memory Requirements .................. J-l

FIGURE
1-1
1-2
1-3
1-4
1-5
1-6
1-7
2-1
2-2
2-3
2-4
2-5
3-1
3-2
3-3
3-4
3-5
5-1
5-2
5-3
5-4
6-1
1-1
1-2
TITLE
PAGE
The iAPX 86,88 Family Development
Process .. . .... .... ... .. .... .... .. .. ...... .. .. .. .. .. ........ .. 1-1
Library Linkage by LINK86 ...................... 1-3
The LINK86/LOC86 Process ..................... 1-4
8086 Addressing ............................."............. 1-6
Segment Physical Relationships ................... 1-7
Segment Alignment Boundaries ................... 1-8
Memory Configuration of Program
with Overlays ................:.......................... 1-10
LINK86 Input and Output Files ................ 2-1
LINK86 Print File Header ........................... 2-27
LINK86 Link Map ...................................... 2-27
LINK86 Group Map ................................... 2-28
LINK86 Symbol Table ................................. 2-29
CREF86 Input and Output Files ................ 3-1
Header of Cross-Reference Listing ............. 3-7
Warning Messages on CREF86 Listing ...... 3-7
Module List on CREF86 lListing ................ 3-8
Symbol Cross-Reference Information ......... 3-9
LOC86 Input and Output Files .................. 5-1
LOC86 Symbol Table ................................... 5-22
LOC86 Memory Map ................................... 5-23
LOC86's Address Assignments for
Overlays .................................................... 5-26
OH86 Input and Output Files ..................... 6-1
LINK86 Print File for Bound
Object Module .......................................... 1-3
LOC86 Print File for Bound Object
Module ....................................................... 1-4
FIGURE
1-3
1-4
1-5
1-6
1-7
1-8
1-9
J-l
J-2
J-3
J-4
J-5
J-6
K-l
K-2
K-3
K-4
K-5
K-6
K-7
K-8
ILLUSTRATIONS
TITLE
PAGE
LINK86 Default Print File .......................... 1-5
CREF86 Cross-Reference Listing ................ 1-6
LINK86 Listing for Program with
Overlays .....................................................
1-9
LOC86 Listing for Program with
Overlays ..................................................... 1-10
LINK86 Map for Root File ......................... 1-11
Module Information for Overlays ................ 1-12
Memory Organization for Example 6 .......... 1-13
CREF86 Cross-Reference Listing ................ J-4
LINK86 Listing for Program with
Overlays
... .................................................. J-7
LOC86 Listing for Program with
Overlays ..................................................... J-8
LINK86 Map for Root File ......................... J-9
Module Information for Overlays
.. .............. J-I0
Memory Organization for Example 4 .......... J-ll
LINK86 Print File for Bound
Object Module ........................................ K-3
LINK86 Default Print File ........................ K-5
CREF86 Cross-Reference Listing .............. K-5
LINK86 Listing for Program with
Overlays ................................................... K-8
LOC86 Listing for Program with
Overlays ...................................................
K-I0
LINK86 Map for Root File ....................... K-ll
Module Information for Overlays .............. K-12
Memory Organization for Example 6 ........ K-13
xi

• (R)
CHAPTER 1
INTRODUCTION
n
SOURCE
FILES
Program Development
Program development is a process of varying complexity. The complexity depends
on the language used to develop code, the complexity of the end product, and the
tools chosen.
Figure
1-1 shows the development process and the tools available for development
of an iAPX86,88 Family-based product.
The tools described in this manual are:
• LINK86, which is a linkage and binding tool
• CREF86, which provides a cross-reference of information on symbols in several
modules
• LIB86, which is the librarian function for 8086 object modules
• LOC86, which is the relocation tool
• OH86, which converts 8086 absolute object information to the hexadecimal
format
r------- ..
...--- _________ .. : OPERATING:
I SYSTEM I
I LOADER I
WITH BIND
r-------.. rl=~r---L-[-
I I OBJECT I I LINKED
r----:TRANSLATOR:----- M.?DUL~S : LlNK86 ~ ~g~~l~
I I .OBJ I : ".LNK"
L _______ J L _______ _
r-------,
I I
--.: CREF86 :
I I
L ___ • ___ J
CROSS-
REFERENCE
LISTING
r-------
I I
--.: LlB86 ::==
..
LTL
OBJECT
MODULE
r-------,
r------- ..
I DEBUGGER:
I OR
: MONITOR :
I. _______ J
I I ABSOLUTE
: LOC86 :----- OBJECT
I I MODULE
L _______ J
I I~----------------~
:. _______ J
Figure 1-1. The iAPX86,88 Family Development Process
L _______ J
r-------'I
I I
I IN-CIRCUIT I
: EMULATOR:
L _______ J
r-------,
I I
: OH86 :
I I
L ___ • ___ .1
r-------,
I I
I HEX I
I LOADER I
I I
L _______ J
121616-1
1-1

Introduction
1-2
iAPX 86,88 Family Utilities
Overview of the Utilities
ASM86, ASM89, PL/M··86, PASCAL-86, FORTRAN-86, and other translators as
well as LINK86
and LOC86 produce 8086 object modules. The language translators
produce 8086 relocatable object modules that must usually be processed by utilities
before execution. (Under certain circumstances the translators can produce absolute
object modules, but this is rare and does not contribute to modular design.) LINK86
combines 8086 object modules, and LOC86 converts relocatable object modules into
absolute
object modules. OH86 converts 8086 absolute object modules to 8086 hexa-
decimal
format.
LINK86 combines a list of 8086 object modules into a single object module and
attempts to match all external symbol declarations with their public symbol defini-
tions in library modules. (LIB86 is the utility used to create and maintain program
libraries.) The output of LINK86 is a relocatable object module. However, when
specified in the
controls, LINK86 produces a load-time-Iocatable (L TL) object
module; an L TL module can be executed on an 8086-based system. (See the descrip-
tion
of L TL modules later in this chapter.) Whether the LINK86 output is an L TL or
a relocatable object module, it can serve as input to LOC86.
CREF86 provides a means for producing a cross-reference listing of public and
external symbols in multiple 8086 object modules. The object modules may include
library modules. The output produced by CRlEF86 should help the programmer to
identify how symbols will be resolved by LINK86, given the same
input files.
LOC86 converts relocatable (or L TL) object modules to absolute object modules.
Absolute object modules contain references that require the module segments to be
placed
at particular places in 8086 memory.
The sequence in which the segments in the input modules are combined and absolute
addresses assigned to segments is determined by the controls supplied and the order
in which the modules are listed in the LINK86 and LOC86 invocations.
External References and Public Symbols
An address field that refers to a location in a different object module is called an
external reference. An external reference differs from a relative address because the
translator that generates the modules knows nothing about the location of the
referenced symbol. You must declare these references as external when coding a pro-
gram. This tells the translator, and subsequently the relocation and linkage (R&L)
utilities, that the target of the reference is in a different module.
A
module that contains external references is called an unsatisfied module. To
satisfy the module, a module with a public symbol that matches the external symbol
must be found. Associated with a public symbol in a module is an address that
allows other modules, with the appropriate external reference, to reference the
module with the public symbol. You must die fine these symbols as public when
coding the program. This tells the source translator and the R&L utilities that other
modules can reference the symbol.
If there are external references •. Jat are not satisfied by public symbols, warning
messages are issued and the resulting module rt:mains unsatisfied.

iAPX 86
t
88 Family Utilities
Use of Libraries
Libraries aid in the job of building programs. The library manager program
t LIB86t
creates and maintains files containing object modules.
LINK86 and CREF86 treat library files in a special manner. If you specify a library
file in the input to these utilities, they search the library for modules that satisfy
unr·esolved external references in the input modules already read. This means that
libraries should be specified after the input modules that contain external references.
If a module included from the library has an external reference, the library is
searched again to try to satisfy the reference. This process continues until all external
references have been the subject of a search of all public symbols in the library
modules.
When LINK86 and CREF86 search a library, they normally include only library
modules that satisfy external references in the output. If no external references are
satisfied by a library, no modules from the library are included in the LINK86 out-
put module or the CREF86 output listing. However, LINK86 and CREF86 provide
the means to unconditionally include a library module even if there is no external
reference to it. Figure 1-2 shows LINK86 handling of a library file.
MODA
MODB
MODC
MODO
MODE
MODF
MOOG
MODH
MODI
MODJ
MODK
INPUTS
MOD1
EXT. REF. X
LIBRARY
PUBLIC A
PUBLIC B
PUBLIC C
PUBLIC 0
PUBLIC E
PUBLIC F
PUBLIC G
PUBLIC H
RLO}:
MOOG
f--._--
PUBLIC I
PUBLIC J
PUBLIC K
Figure 1-2. Library Linkage by LINK86
OUTPUT
MODULE
121616-2
Introduction
1-3

Introduction
1-4
iAPX 86,88 Family Utilities
Relative Addressing
The relative addresses of instructions and data in program modules are assigned by
the source translator. The addresses are relative to the beginning of the segment in
which they reside.
The relative address is actually the number of bytes from the
beginning of the segment.
After LINK86 combines all the input segments, LOC86 can be used to assign
absolute
memory addresses to all relative addresses. The resulting output module
can only be executed when its segments are loaded at the absolute addresses assigned
by the
command. If LINK86 is used to create a bound object module, LOC86 is not
needed to execute the program.
The LINK86/LOC86 Process
Although controls are not required for LINK86 and LOC86 execution, the com-
mands invoking them may contain controls that affect their output. The controls
make it possible to change the defaults for module combination, address assign-
ment,
and output information.
The inputs are object modules in disk files. The input modules can contain relative
addresses,
absolute addresses, external references, and public symbols. The input
modules must be in the 8086 object module format such as is generated by 8086
translators and LINK86 and LOC86 themselves.
LINK86 combines segments
from the input modules, and for L TL object modules
LINK86 orders segments in groups and assigns offsets. LOC86 orders the segments
and assigns absolute addresses according to the controls specified with the command
and/or the default algorithms. Both commands output the module when processing
is completed along with any error messages and diagnostic information. Figure 1-3
shows the LINK86/LOC86 process.
INPUTS
lINK86
COMMAND
AND
CONTROLS
lINK86 / Loe86
OUTPUTS INF'UT
LTL
OR
LINKED
OBJECT
MODULE
LOC86
COMMAND
AND
CONTROLS
Figure 1-3. The LINK86/LOC86 Process
LOCATED
ABSOLUTE
OBJECT
MODULE
121616-3

iAPX 86,88 Family Utilities
An 8086 Overview
To use the R&L commands you must have an understanding of the following
concepts:
• Addresses, given as offsets into segments, which must be translated into
absolute memory addresses, or base offsets
• Segment definitions, which identify contiguous pieces of information, usually
code or data
• Class definitions, which identify segments that share common attributes and
should be kept together
• Group definitions, which identify segments that must be kept within a 64K byte
range of memory
• Overlay definitions, which identify modules that will be loaded in memory at
different times during execution.
• Load-time-locatable object modules
Memory
The 8086 can address up to a maximum of a megabyte of memory. In decimal a
megabyte is 1,048,576 bytes. Memory addresses are always shown in hexadecimal. A
megabyte of memory has the addresses: OH through OFFFFFH.
Not all 8086-based systems will have a full megabyte of memory. Many systems will
have
gaps in the memory that is available. The different portions of memory will
probably be implemented with different types of memory chips. The system monitor
or supervisor is usually stored in ROM or PROM chips. Because it is not modified
by execution it can be a permanent part of the system. This prevents the need to load
it each time the system is turned on. The data that is referenced often is kept in high-
speed
RAM because it is modified frequently. It may be practical to keep data that is
referenced less often in slower-speed memory. The size and composition of a
system's memory is totally dependent on the application the system serves.
Linkage
and relocation is designed to handle the linking and locating of your pro-
gram, no matter how your 8086-based system memory is implemented. It provides
very flexible segment placement within any given memory configuration.
8086 Addressing Techniques
The 8086 addresses memory with a 20-bit address that is constructed from a segment
address and a 16-bit offset from that segment address. This means that with a single
segment address, 64K bytes of memory is directly addressable by changing only the
offset.
A hardware segment address is a 20-bit address. But the segment address is con-
strained such that the segment is placed on a boundary that is a mUltiple of 16 (lOH).
The segment address can be set to any hexadecimal address ending in 0:
OH
010H
020H
OFFFFOH
Introduction
1-5

Introduction
1-6
iAPX 86,88 Family Utilities
Because the low four bits of the 20-bit segment address are always zero, the segment
address can be represented with only 16 bits.
The segment address is kept in one of four 16-bit segment registers. Because there
are
four segment registers, the 8086 can, at any moment, access 256K (4 x 64K) bytes
of memory. The full megabyte of memory is accessed by changing the values in the
segment registers. Figure 1-4 shows the 8086 addressing concept.
SEGMENT
REGISTER
OFFSET
~
12340H
+ 8003H
.~
Segments
1A343H
EFFECTIVE 20·BIT ADDRESS
64K BYTES CAN BE
ADDRESSED BY
CHANGING THE
OFFSET ONLY
MEMORY
,.....--.-------, FFFFFH
t-- - - -- -- - - - - - - -
64K BYTES
t-- - - -- - - - - - - - -
~--.-------~OH
Figure 1-4. 8086 Addressing
639-4
Programs comprise pieces called segments, which are the fundamental units of
linkage and relocation. The basic divisions have functional purposes related to the
hardware configuration of memory. The portilons of programs that are to be kept in
ROM or PROM can be put in separate segments from the portions that will be kept
in RAM.
The 8086 Assembler allows the programmer to name the segments of the program
being developed. The PL/M-86 compiler may generate predefined names for
segments.
A segment
is a contiguous area of memory that is defined at translation time
(assemble
or compile). When defined, a segment does not necessarily have a fixed
address or size. A fixed address is assigned to a segment during the locate function.
The size can be changed by combining segments and by a control that specifies a
specific size.
Some translations may produce absolute object information, with
absolute addresses and a specific segment size.

iAPX 86,88 Family Utilities
LINK86 combines all segments with the same complete (segment, class and overlay)
name and combination type (memory, stack, etc.) from all input modules. The
ordering of segments is done on the basis of these combined segments. The manner
in which segments are combined depends on the alignment of the segments (which is
described in the next topic) and a combining attribute associated with the segment.
When we refer to combining segments, we are talking about how the segments will
be loaded in
memory, not how they will be stored in the output module. The
segments in the LOC86 output module contain addresses that determine where they
will be loaded in memory"
The segments reside in the output module in the same
order as they were in the input modules. Figure 1-5 shows the physical relationships
between the
input modules, output module, and loaded program.
INPUT
MODULES
SEG A
SEG B
SEG C
SEG D
SEG E
1------
SEG F
OUTPUT
MODULE
ON DISKETTE
SEG A
SEG B
SEG C
SEG D
SEG E
SEG F
OUTPUT MODULE
LOADED IN
MEMORY
I SEG B I
I SEG E I
Figure 1-5. Segment Physical Relationships
Segment Alignment
639-5
A segment can have one (and in the case of the inpage attribute, two) of five align-
ment attributes:
• Byte, which means a segment can be located at any address
• Word, which means a segment can be located only at an address that is a
multiple
of two, starting from address OH
• Paragraph, which means a segment can be located only at an address that is a
multiple
of 16, starting from address 0
• Page, which means a segment
can be located only at an address that is a multiple
of 256, starting from address 0
• Inpage, which means a segment
can be located at whichever of the preceding
attributes apply, plus must be located so that it does not cross a page boundary
Figure 1-6 shows the segment alignment boundaries.
Any alignment
attribute except byte can result in a gap between combined segments.
For example, when two page-aligned segments are combined, there will always be a
gap, unless the first
happens to be an exact mUltiple of 256 bytes in length.
In trod uction
1-7