Intel NetStructure ZT 5504 User manual

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Intel®NetStructure™ZT 5504
System Master Processor Board
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2
Revision History
Revision Date Revision History
03/19/02 Added information on use in 3.3V systems. Removed Optional CompactFlash Carrier
appendix.
06/06/02 Added references to the ZT 96080 and to the ZT 96080 user documentation.
Copyright © 2002, Intel Corporation. All rights reserved.
Intel Corporation
5200 N.E. Elam Young Parkway
Hillsboro, OR 97124-6497
Intel Corporation assumes no responsibility for errors or omissions in this document. Nor does Intel make any
commitment to update the information contained herein.
Information in this document is provided in connection with Intel products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel
disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or
warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life
sustaining applications.
Intel and NetStructure are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the
United States and other countries.
*Other brands and names may be claimed as the property of others.
06/06/02
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3
Contents
Tables..................................................................................................................................................................8
Figures.................................................................................................................................................................9
Manual Organization .........................................................................................................................................10
1. Introduction....................................................................................................................................................11
Product Definition ......................................................................................................................................11
Features.....................................................................................................................................................12
Functional Blocks.......................................................................................................................................14
CompactPCI/PSB Architecture.............................................................................................................14
Processor .............................................................................................................................................15
Chipset .................................................................................................................................................15
PCI-to-PCI Bridge (P2P) ......................................................................................................................15
Memory and I/O Addressing.................................................................................................................16
Drone Mode..........................................................................................................................................16
Power Ramp Circuitry...........................................................................................................................16
Rear-Panel I/O......................................................................................................................................17
PCI Video .............................................................................................................................................17
PCI Mezzanine Card (PMC) Interface..................................................................................................18
Dual Ethernet Interfaces.......................................................................................................................18
IDE Hard Drive .....................................................................................................................................18
Serial I/O...............................................................................................................................................18
Interrupts ..............................................................................................................................................19
Counter/Timers.....................................................................................................................................19
DMA......................................................................................................................................................20
Real-Time Clock...................................................................................................................................20
Reset ....................................................................................................................................................20
Two-Stage Watchdog Timer.................................................................................................................20
Universal Serial Bus (USB) ..................................................................................................................20
Baseboard Management Controller .....................................................................................................21
IDE Controller.......................................................................................................................................21
Floppy Disk Controller..........................................................................................................................21
Keyboard and Mouse Controller...........................................................................................................21
LED Indicators......................................................................................................................................21
Software.....................................................................................................................................................22
2. Getting Started ..............................................................................................................................................23
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Unpacking..................................................................................................................................................23
System Requirements ...............................................................................................................................23
BIOS Version........................................................................................................................................23
Connectivity..........................................................................................................................................23
Electrical and Environmental................................................................................................................24
Memory Configuration ...............................................................................................................................25
I/O Configuration........................................................................................................................................28
Connectors ................................................................................................................................................28
Switches and Cuttable Traces...................................................................................................................28
BIOS Configuration Overview....................................................................................................................28
Operating System Installation....................................................................................................................29
3. Configuration.................................................................................................................................................31
Switch Options and Locations ...................................................................................................................31
Switch Descriptions ...................................................................................................................................32
SW1 (Reset).........................................................................................................................................32
SW2-1, SW2-2 (Real-Time Clock Battery Backup)..............................................................................32
SW2-3 (VGA Routing Control) .............................................................................................................33
SW3-1 (BIOS Recovery Module/Flash Select) ....................................................................................33
SW3-2 (Flash Write-Protect)................................................................................................................33
SW3-3 (IPMI Flash Write Protect)........................................................................................................34
SW3-4 (Drone Mode Reset).................................................................................................................34
SW4-1, SW4-2, SW4-3 (Software Configuration)................................................................................34
SW4-4 (Console Redirection)...............................................................................................................34
Cuttable Trace Options and Locations......................................................................................................35
CT14, CT15, CT17-19, CT21-24, and CT51 (Connect Chassis GND to Logic GND) .........................37
CT16 and CT27-29 (Board Revision)...................................................................................................37
CT31 and CT32 (USB1 Front/Rear Routing) .......................................................................................37
CT57 and CT58 (USB0 Front/Rear Routing) .......................................................................................37
CT38 (D_RSTDRV- to COM Port Driver).............................................................................................38
4. Reset .............................................................................................................................................................39
Reset Types and Sources .........................................................................................................................39
Hard Reset Sources.............................................................................................................................39
Soft Reset Sources...............................................................................................................................39
Backend Power Down Sources............................................................................................................40
NMI Sources.........................................................................................................................................40
5. System Monitoring and Control.....................................................................................................................41
Monitoring and Control Functions..............................................................................................................41
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BMC LED Control.................................................................................................................................42
Field Replaceable Unit Information......................................................................................................42
System Event Log Information.............................................................................................................42
SMBus Address Map.................................................................................................................................42
6. IDE Controller................................................................................................................................................44
Features of the IDE Controller...................................................................................................................44
Disk Drive Support.....................................................................................................................................44
Primary IDE Channel............................................................................................................................44
Secondary IDE Channel.......................................................................................................................44
I/O Mapping...............................................................................................................................................45
CompactFlash Carrier................................................................................................................................45
Device Drivers ...........................................................................................................................................45
7. Watchdog Timer............................................................................................................................................46
Watchdog Timer Overview ........................................................................................................................46
Power Up Initialization..........................................................................................................................47
Timeout Values.....................................................................................................................................47
Using the Watchdog in an Application.......................................................................................................47
Watchdog Reset...................................................................................................................................47
Enabling the Watchdog Reset ....................................................................................................... 47
Setting the Terminal Count............................................................................................................ 48
Strobing the Watchdog ..................................................................................................................48
Watchdog NMI......................................................................................................................................48
Chaining the ISRs..........................................................................................................................49
Enabling the Watchdog NMI.......................................................................................................... 49
NMI Handler...................................................................................................................................50
8. BIOS Recovery..............................................................................................................................................51
Flash..........................................................................................................................................................51
BIOS Recovery Module.............................................................................................................................52
Flash Utility Program............................................................................................................................52
A. Specifications................................................................................................................................................53
Electrical and Environmental.....................................................................................................................53
Absolute Maximum Ratings..................................................................................................................53
DC Operating Characteristics...............................................................................................................53
Battery Backup Characteristics............................................................................................................54
Operating Temperature........................................................................................................................54
Reliability ...................................................................................................................................................54
Mechanical.................................................................................................................................................55
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Board Dimensions and Weight.............................................................................................................55
Connectors...........................................................................................................................................56
J1 (CompactPCI Bus Connector) ..................................................................................................58
J2 (CompactPCI Bus Connector) ..................................................................................................59
J3 (CompactPCI Connector)..........................................................................................................60
J5 (Rear Panel I/O CompactPCI Connector)................................................................................. 61
JA4 and J17 (Ethernet A and B Connectors).................................................................................62
J6 (VGA Connector).......................................................................................................................62
J8 and J9 (Universal Serial Bus 0 and 1 Connectors)...................................................................63
J10 (COM1 Serial Port)..................................................................................................................63
J13 and J16 (PCI Mezzanine Connectors)....................................................................................64
J14 (IDE Connector)......................................................................................................................66
B. Thermal Considerations................................................................................................................................67
Thermal Requirements..............................................................................................................................67
Temperature Monitoring ............................................................................................................................68
C. System Registers..........................................................................................................................................69
System Register Definitions ......................................................................................................................69
Flash Control (78h)...............................................................................................................................70
Watchdog (79h)....................................................................................................................................71
J1 IPMB Control (7Bh)..........................................................................................................................74
Port 80 BIOS POST Codes (80h).........................................................................................................74
Event Monitors (E1h)............................................................................................................................75
Switch Monitors (E3h) ..........................................................................................................................75
Geographic Addressing (E4h)..............................................................................................................76
Control Bits (E5h).................................................................................................................................77
J5 SMBus Enable (E6h).......................................................................................................................77
D. Datasheet Reference....................................................................................................................................78
Board Serial Number.................................................................................................................................78
CompactPCI ..............................................................................................................................................78
Ethernet.....................................................................................................................................................78
Intel 440GX AGPset ..................................................................................................................................78
Mobile Pentium III Processor - M in BGA2 Package.................................................................................79
PCI-To-PCI Bridge.....................................................................................................................................79
PMC Specification .....................................................................................................................................79
SuperI/O ....................................................................................................................................................79
Video..........................................................................................................................................................79
E. Agency Approvals.........................................................................................................................................80
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CE Certification..........................................................................................................................................80
Safety.........................................................................................................................................................80
Emissions Test Regulations ......................................................................................................................80
EN 50081-1 Emissions.........................................................................................................................80
EN 55024 Immunity..............................................................................................................................80
Regulatory Information ..............................................................................................................................81
FCC (USA) ...........................................................................................................................................81
Industry Canada (Canada)...................................................................................................................81
F. Customer Support.........................................................................................................................................82
Technical Support and Return for Service Assistance..............................................................................82
Sales Assistance .......................................................................................................................................82
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8
Tables
Revision History...................................................................................................................................................2
Fault Current Limits...........................................................................................................................................17
Switch Cross-Reference Table..........................................................................................................................31
Cuttable Trace Definitions.................................................................................................................................35
Connector Assignments ....................................................................................................................................56
J1 CompactPCI Bus Connector Pinout.............................................................................................................58
J2 CompactPCI Bus Connector Pinout.............................................................................................................59
J3 Connector Pinout..........................................................................................................................................60
J5 Rear Panel I/O Connector Pinout.................................................................................................................61
JA4 and J17 Ethernet A and B Connector Pinout.............................................................................................62
J6 VGA Connector Pinout .................................................................................................................................62
J8 and J9 Universal Serial Bus 0 and 1 Connector Pinout ...............................................................................63
J10 COM1 Serial Port Pinout ............................................................................................................................63
J13 PCI Mezzanine Connector Pinout ..............................................................................................................64
J16 PCI Mezzanine Connector Pinout ..............................................................................................................65
J14 IDE Connector Pinout.................................................................................................................................66
Thermal Requirements......................................................................................................................................67
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9
Figures
ZT 5504 Faceplate ............................................................................................................................................12
Functional Block Diagram..................................................................................................................................14
Memory Address Map Example ........................................................................................................................26
I/O Address Map................................................................................................................................................27
Setup Screen.....................................................................................................................................................29
Default Switch Configuration.............................................................................................................................32
Cuttable Trace Locations...................................................................................................................................36
Watchdog Timer Architecture............................................................................................................................46
BIOS Recovery Socket Location.......................................................................................................................51
PCB Dimensions ...............................................................................................................................................55
Connector Locations..........................................................................................................................................57
Backplane Connectors - Pin Locations .............................................................................................................57
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10
Manual Organization
This manual describes the operation and use of the Intel® NetStructure™ ZT 5504 System
Master Processor Board with a Mobile Intel® Pentium® III Processor - M. The following topics
are covered in this manual.
Chapter 1, "Introduction," introduces the key features of the ZT 5504. This chapter includes a
product definition, a list of product features, and a functional block diagram with a brief
description of each block. This chapter can be used to compare the features of the ZT 5504
against the needs of a specific application.
Chapter 2, "Getting Started," provides unpacking instructions and initial setup information for
the ZT 5504. This chapter summarizes configuration information and should be read before
using the board.
Chapter 3, "Configuration," describes the switches and cuttable traces on the ZT 5504. This
chapter details factory default settings and provides information about tailoring the board to the
needs of specific applications.
Chapter 4, "Reset," discusses the reset types and reset sources available on the ZT 5504.
Chapter 5, "System Monitoring and Control," lists various system monitoring and control
features available on the ZT 5504.
Chapter 6, "IDE Controller," provides an introduction to the ZT 5504's IDE Controller. This
chapter covers drive configuration, IDE I/O mapping, device drivers, and the ZT 5504's support
for internal and external disk drives.
Chapter 7, "Watchdog Timer," explains the operation of the ZT 5504's watchdog timer.
Sample code is provided to illustrate how the watchdog's functions are used in an application.
Chapter 8, "BIOS Recovery," discusses recovery from and correction of a corrupted BIOS.
Appendix A, "Specifications," contains the electrical, environmental, and mechanical
specifications for the ZT 5504. This chapter also provides a connector location illustration and
connector pinout tables.
Appendix B, "Thermal Considerations," describes the thermal requirements for reliable
operation of the ZT 5504.
Appendix C, "System Registers," provides a detailed description of the system registers
available for monitoring and controlling various board operations.
Appendix D, "Datasheet Reference," provides links to Websites with information about many
of the devices and technologies used in the ZT 5504.
Appendix E, "Agency Approvals," presents UL, CE, and FCC agency approval and
certification information for the ZT 5504.
Appendix F, "Customer Support," provides technical and sales assistance information.
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1. Introduction
This chapter provides an introduction to the ZT 5504 including a product definition, a list of
product features, and a functional block diagram with descriptions of each block.
The "ZT 5504 Faceplate" illustration identifies the connectors, indicators, and switches
available on the ZT 5504's faceplate. Optional rear-panel transition boards are available to
extend various faceplate features to a system's rear-panel. For more information about
compatible rear-panel transition boards, see the Intel NetStructure ZT 4807 Packet Switched
Rear-Panel Transition Board Hardware Manual.
Product Definition
The Intel NetStructure ZT 5504 System Master Processor Board is a single board computer
designed to work as a modular component in a high-performance CompactPCI* system. It
utilizes the Mobile Intel Pentium III Processor - M, in a BGA2 package, to provide extremely
high PCI performance and the latest in memory and I/O technology combined with low power
requirements. The ZT 5504 includes CompactPCI Packet Switching Backplane
(CompactPCI/PSB) compliance and Intelligent Platform Management Bus (IPMB) system
management features. The ZT 5504 CPU board is an ideal solution for telecommunications,
Internet, and industrial control applications with demanding performance and system reliability
requirements.
The ZT 5504 occupies a single 6U high Eurocard slot. The board can be used as a System
Master or it can operate in "Drone Mode" when installed in a peripheral slot. When in Drone
Mode the ZT 5504 operates on its own without communicating over the CompactPCI bus.
Though the ZT 5504 is highly integrated, its capabilities can be extended with optional boards
available from Intel. Expansion boards are available to add IDE devices such as a CD-ROM
drive or CompactFlash and transition boards are available to extend I/O access to the rear of a
system. For more information about options and accessories, including the ZT 96080
CompactFlash Carrier, see the Intel NetStructure building blocks page at:
http://developer.intel.com/design/network/products/cbp/linecard.htm
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1. Introduction
12
ZT 5504 Faceplate
Hot Swap LED
Blue = Safe to Extract Board
Off = Normal Operation
Health LED
Green = Normal Operation
Amber = Needs Attention
Ethernet A and B
(JA4 and J17)
Yellow = Activity
Green = Link
Disk 0: Primary IDE
Disk 1: Unused
Green = Active
Off = Inactive
Ejector Handle
(with Hot Swap Switch)
Ejector Handle
Video (J6)
PMC Slot
USB 0 and 1
(J8 and J9)
Reset Push-button
(SW-1)
COM Port
(J10)
System LEDs
Features
• CompactPCI Specification, PICMG 2.0, Version 2.1 and CompactPCI Specification, PICMG
2.16, Version 1.0 compliant
• 6U single-slot CompactPCI form factor
• Mobile Intel Pentium III Processor - M, BGA2 package
• Intel® 440 GX chipset
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1. Introduction
13
• Built-in numeric coprocessor support
• 16 KB of CPU instruction cache
• 16 KB of CPU data cache
• 256 KB of Level 2 cache
• 512 MB or 1 GB of ECC SDRAM
• BIOS stored in flash memory
• Standard AT* Systems include:
– Two enhanced interrupt controllers (8259)
– Three counter/timers (one 8254)
– Real-time clock/CMOS RAM (146818)
– Two enhanced DMA controllers (8237)
– 8042 compatible keyboard controller
– Speaker interface
– PS/2 mouse and keyboard
• Dual stage watchdog timer
• Intel® 69000 series AGP graphics chip
• IPMI through an Intel® Baseboard Management Controller chip
• Dual 10/100 Mbit/s Ethernet* (available at the faceplate or the J3 backplane connector)
• Primary IDE channel supports the on-board 2.5 inch hard disk and an IDE device (CD-ROM)
on a media expansion board
• Single on-board PCI Mezzanine Card (PMC) slot, 32-bit @ 33 MHz using 3.3V signaling
• Two 16C550 RS-232 serial ports (COM1 available at the faceplate, COM1 and COM2
available through the J5 backplane connector)
• Push Button Reset on the front panel
• Rear-Panel I/O Availability (at J5) includes the following
– Secondary IDE channel
– Rear panel eject
– Push-button reset input
• DC power monitors (+3.3V, +5V, +12V, -12V, and CPU core voltage)
• Support for Windows* 2000 Professional, Windows 2000 Server, Linux*, and VxWorks*
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1. Introduction
14
Functional Blocks
The following topics provide overviews of the ZT 5504's main features, some of which are
shown in the functional block diagram below.
Functional Block Diagram
Serial
Port
Status
LEDs Reset Video Ethernet B
10BASE-T/
100BASE-TX
PMC
SITE
PMC Slot
USB 0 Battery
Real-Time Clock
ECC
SDRAM
(512 Mbyte or
1 Gbyte)
Keyboard
Controller
Power
Controller Baseboard
Management
Controller
Backplane I/O
440GX
AGPset
SVGA
Video
USB 1
Ethernet A
10BASE-T/
100BASE-TX
Pentium III
Processor
L1 and L2
Cache
(PCI-to-PCI Bridge)
Interface
IDE
HARD
DRIVE
Floppy Disk
Controller
Serial
Number Temp.
Sensor Watchdog
Timer
BGA2
Flash
Memory
(BIOS)
CompactPCI/PSB Architecture
The ZT 5504 is designed to operate in a CompactPCI Packet Switching Backplane
(CompactPCI/PSB) system. The CompactPCI/PSB specification is an extension to the PICMG
2.x family of specifications that overlays a packet-based switching architecture on top of
CompactPCI to create an Embedded System Area Network (ESAN). CompactPCI/PSB
supplements the robust, reliable and hot-swap capable CompactPCI architecture with the
easily integrated, low-cost, high-performance, and extensible Ethernet.
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1. Introduction
15
When used in accordance with the CompactPCI Packet Switching Backplane Specification,
PICMG 2.16, Version 1.0, the ZT 5504 functions as a "Dual Link Port Node" board. The
ZT 5504 can be connected to a system's fabric-switched Link Ports A and B, and can be
inserted into system or peripheral slots. The ZT 5504 is keyed for insertion into compatible
slots.
The "CompactPCI" topic in Appendix E contains a link to the PCI Industrial Computer
Manufacturers Group.
Processor
The ZT 5504 uses the Mobile Pentium III Processor - M in a BGA2 package. The 0.18 micron
BGA2 package is a highly integrated assembly containing a mobile version of the Pentium III
processor and its immediate system-level support. This mobile processor runs at a lower
voltage than the desktop version.
The 256 KB on-die transfer L2 cache is integrated with the CPU, eliminating the need for
separate components and improving performance. The BGA2 package Pentium III processor
also operates with a 100 MHz Processor Side Bus for faster access to memory and data.
The "Mobile Pentium III Processor - M in BGA2 Package" topic in Appendix E contains a link to
the datasheet for the processor.
Chipset
The Intel 440GX AGPset consists of the 82443GX Host Bridge and the 82371EB (PIIX4E) I/O
subsystem chip. The Host Bridge includes an optimized SDRAM controller. The I/O subsystem
is a highly integrated PCI ISA IDE Xcelerator Bridge.
The "Intel 440GX AGPset" topic in Appendix E contains a link to information about the chipset.
PCI-to-PCI Bridge (P2P)
The ZT 5504 features one Intel® 21154 PCI-to-PCI bridge to support the J1/J2 CompactPCI
buses. The bridge provides the isolation, arbitration, and clocks for seven PCI peripheral cards
without the need for an external bridge board.
Special features of the 21154 include:
• 33 MHz or 66 MHz PCI bus operation
• Support for independent primary and secondary PCI clocks
• 64-bit PCI operation
The "PCI-to-PCI Bridge" topic in Appendix E contains a link to information about the chipset.
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1. Introduction
16
Memory and I/O Addressing
The ZT 5504 supports 512 MB or 1 GB of local memory. This memory is installed at the factory
and is not field upgradeable. The local memory is implemented as Error-Correcting Code
(ECC) SDRAM. ECC will correct single bit errors (97% of all DRAM errors are single bit errors)
and can report multiple bit errors to the operating system. How ECC errors are reported is a
BIOS setup option.
In addition to SDRAM, the ZT 5504 uses an on-board flash memory device to store the system
BIOS.
See the "Memory Configuration" and "I/O Configuration" topics in Chapter 2 for more
information.
Drone Mode
Typically, the ZT 5504 operates as the System Master from the system slot. The ZT 5504 can
also operate in Drone Mode from a peripheral slot. In Drone Mode, the CPU board receives
power from the system but it cannot communicate on the CompactPCI bus. Onboard logic uses
SYSEN# to qualify the ZT 5504's location when inserted in a peripheral slot, thereby isolating
the board from the CompactPCI bus.
The ZT 5504 can be hot swapped when operating in Drone Mode (in peripheral slots, the board
is operating in isolation from the backplane).
CAUTION: The ZT 5504 is not intended to be hot swapped in the system slot. Hot swapping
the CPU board in the system slot may damage other boards in the system.
Power Ramp Circuitry
The ZT 5504 features a power controller with power ramp circuitry that allows the board's
voltages to be ramped in a controlled fashion. The power ramp circuitry eliminates large
voltage or current spikes caused by hot swapping boards. This controlled ramping is a
requirement of the CompactPCI Hot Swap Specification, PICMG 2.1, Version 1.0.
The ZT 5504's power controller unconditionally resets the board when it detects that the 3.3V,
5V, and 12V supplies are below an acceptable operating limit. Minimum voltage thresholds for
the ZT 5504 are: 4.75V (5V supply), 3.0V (3.3V supply), and 10.0V (+12V supply).
Fault current sensing is also provided. If a board fault (short circuit) or over-current condition is
detected, the power controller removes power from the ZT 5504's components and the Health
LED on the faceplate turns amber. Fault protection activates if the current exceeds the
threshold for greater than 50µs. The ZT 5504's fault current limits are shown in the following
table.
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1. Introduction
17
Fault Current Limits
Power Source Minimum Maximum
+5.0V 10.0A 15.0A
+3.3V 9.4A 14.1A
+12V 1.0A 1.5A
-12V 0.6A 0.9A
Notes:
• The fault trip currents listed above are design values. Noisy power sources can lower the fault trip
current limits to less than the minimum design values.
• Over-current on the -12V supply does not activate the fault trip circuit breaker and the LED will not
turn amber. -12V is over-current protected by a resettable (PTC) 0.75A fuse.
Rear-Panel I/O
The following I/O signals are available from the J5 connector at the back of the ZT 5504. These
signals are available for use by a rear panel transition board such as the ZT 4807.
• Serial ports (COM1 and COM2)
• USB Ports 0 and 1 (through cuttable trace configuration)
• Floppy Interface
• Keyboard
• PS/2 mouse
• Push button reset input
• IDE secondary channel
• SMBus
• Ejector
• Video
• Speaker Output (AT compatible)
PCI Video
The ZT 5504 provides on-board video using the Chips and Technologies 69000 HiQVideo
Accelerator with Integrated Memory. This device is configured for PCI bus transactions at
speeds up to 33 MHz.
The 69000 incorporates 2 MB of integrated SDRAM for the graphics/video frame buffer. The
integrated SDRAM memory can support up to 83 MHz operation, thus increasing the available
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1. Introduction
18
memory bandwidth for the graphics subsystem. Video signals are available at the ZT 5504's
J6 faceplate connector or at the J5 Rear Panel I/O connector. See "SW2-3 (VGA Routing
Control)" in Chapter 3 for information on directing video signals to the front or rear of the board.
The "Video" topic in Appendix E contains a link to the datasheet for this device.
PCI Mezzanine Card (PMC) Interface
The ZT 5504 provides a location for one on-board PMC device with front panel access. The
PMC interface is on PCI Bus 0 and uses a 32-bit 3.3V PCI bus.
The "PMC Specification" topic in Appendix E contains a link to the sponsoring organization for
the PMC specification.
Dual Ethernet Interfaces
The ZT 5504 provides two 10/100BaseTx Ethernet channels (A and B) through the
Intel® 82550 Fast Ethernet Multifunction PCI Controller with integrated Alert On LAN (AOL).
The 82550 consists of both the Media Access Controller (MAC) and the physical layer (PHY)
interface combined into a single component solution. Two RJ-45 connectors with integrated
LEDs are available at the faceplate. Both Ethernet channels can be directed to the J3
backplane connector. See "Geographic Addressing (E4h)" in Appendix C for more information.
The "Ethernet" topic in Appendix E contains links to the datasheets for the Ethernet devices
used on the ZT 5504.
IDE Hard Drive
The ZT 5504 includes an on-board 2.5-inch Enhanced IDE hard drive. The hard drive is on the
ZT 5504's primary IDE channel and is assigned "device 0" (master) identity.
See Chapter 6, "IDE Controller", for more information.
Serial I/O
The ZT 5504 provides support for two RS-232 compatible serial ports. COM1 is accessible at
the faceplate through an RJ-45 connector or through the J5 Rear Panel I/O connector. This
port is typically used for test access. COM2 is accessible only through the J5 Rear Panel I/O
connector. No strapping option or software control is required to use either port.
The front panel RJ-45 connector is configured as DTE. SRI (Serial Ring Indicator) and SCD
(Serial Carrier Detect) signals are not included in the front panel RJ-45 connector. Refer to the
"J10 (COM1 Serial Port)" topic in Appendix A for a connector pinout.
Note: COM1 signals are available to the front- and rear-panel simultaneously. Utilizing the
COM1 signal at the front and rear at the same time will cause a signaling conflict.
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1. Introduction
19
The ZT 5504's serial controller resides in the National Semiconductor*PC87309 SuperI/O*
device. The "SuperI/O" topic in Appendix E provides a link to the datasheet for this device.
Interrupts
Two enhanced, 8259-style interrupt controllers provide the ZT 5504 with a total of 15 interrupt
inputs. Interrupt controller features include support for:
• Level-triggered and edge-triggered inputs
• Individual input masking
• Fixed and rotating priorities
Interrupt sources include:
• Counter/Timers
• Serial I/O
• Keyboard
• Printer Port
• Floppy disk
• IDE interface
• Real-Time Clock
• CompactPCI backplane (21154)
• On-board PCI devices
Enhanced capabilities include the ability to configure each interrupt level for active high-going
edge or active low-level inputs.
The ZT 5504's interrupt controllers reside in the Intel® 82371EB (PIIX4E) device. The "Intel
440GX AGPset" topic in Appendix E provides a link to the datasheet for this device.
Counter/Timers
Three 8254-style counter/timers, as defined for the PC/AT, are included on the ZT 5504.
Operating modes supported by the counter/timers include:
• Interrupt on count
• Frequency divider
• Square wave generator
• Software triggered
• Hardware triggered
• One shot
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