Intel I5-520E - ADDENDUM User manual

Document Number: 323178-002
Intel®CoreTM i7-620LE/UE, i7-610E,
i5-520E and Intel®Celeron®
Processor P4500, P4505 Series
Datasheet Addendum
April 2010

Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505 Series
Datasheet Addendum April 2010
2Document Number: 323178-002
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Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505 Series
April 2010 Datasheet Addendum
Document Number: 323178-002 3
Contents
1 Introduction and Features Summary .........................................................................8
1.1 Introduction .......................................................................................................8
1.2 Interfaces ........................................................................................................10
1.2.1 System Memory Support.........................................................................10
1.2.2 PCI Express* ......................................................................................... 10
1.3 Package...........................................................................................................11
1.4 Terminology .....................................................................................................12
1.5 Related Documents ...........................................................................................13
2Interfaces................................................................................................................15
2.1 System Memory Interface ..................................................................................15
2.1.1 System Memory Technology Supported.....................................................15
2.1.2 System Memory Timing Support...............................................................16
2.1.3 System Memory Organization Modes.........................................................16
2.1.4 Rules for Populating Memory Slots............................................................18
2.1.5 Technology Enhancements of Intel®Fast Memory Access (Intel®FMA)..........18
2.1.6 DRAM Clock Generation...........................................................................19
2.1.7 DDR3 On-Die Termination .......................................................................19
2.2 PCI Express* Interface.......................................................................................19
2.2.1 PCI Express* Configuration Mechanism .....................................................19
2.2.2 PCI Express Port Bifurcation.....................................................................20
3 Signal Description ...................................................................................................21
3.1 System Memory Interface ..................................................................................21
3.2 Reset and Miscellaneous Signals..........................................................................24
4 Electrical Specifications...........................................................................................25
4.1 Signal Groups...................................................................................................25
4.2 DC Specifications .............................................................................................. 25
4.2.1 Voltage and Current Specifications............................................................25
5 Processor Ball and Signal Information..................................................................... 27
5.1 Processor Ball Assignments.................................................................................27
6 Processor Configuration Registers...........................................................................69
6.1 Register Terminology.........................................................................................69
6.1.1 DEVEN - Device Enable ........................................................................... 71
6.1.2 ERRSTS - Error Status ............................................................................72
6.1.3 ERRCMD - Error Command ......................................................................73
6.1.4 SMICMD - SMI Command........................................................................75
6.1.5 C0WRDATACTRL - Channel 0 Write Data Control......................................... 76
6.1.6 COECCERRLOG - Channel 0 ECC Error Log.................................................77
6.1.7 C1WRDATACTRL - Channel 1 Write Data Control......................................... 79
6.1.8 C1ECCERRLOG - Channel 1 ECC Error Log .................................................79
6.2 PCI Device 6.....................................................................................................80
6.2.1 VID6 - Vendor Identification ....................................................................84
6.2.2 DID6 - Device Identification.....................................................................84
6.2.3 PCICMD6 - PCI Command........................................................................85
6.2.4 PCISTS6 - PCI Status..............................................................................87
6.2.5 RID6 - Revision Identification...................................................................89
6.2.6 CC6 - Class Code ...................................................................................89
6.2.7 CL6 - Cache Line Size .............................................................................90
6.2.8 HDR6 - Header Type...............................................................................90
6.2.9 PBUSN6 - Primary Bus Number ................................................................91

Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505 Series
Datasheet Addendum April 2010
4Document Number: 323178-002
6.2.10 SBUSN6 - Secondary Bus Number.............................................................91
6.2.11 SUBUSN6 - Subordinate Bus Number ........................................................92
6.2.12 IOBASE6 - I/O Base Address....................................................................92
6.2.13 IOLIMIT6 - I/O Limit Address ...................................................................93
6.2.14 SSTS6 - Secondary Status .......................................................................94
6.2.15 MBASE6 - Memory Base Address...............................................................95
6.2.16 MLIMIT6 - Memory Limit Address..............................................................96
6.2.17 PMBASE6 - Prefetchable Memory Base Address...........................................97
6.2.18 PMLIMIT6 - Prefetchable Memory Limit Address ..........................................98
6.2.19 PMBASEU6 - Prefetchable Memory Base Address Upper................................99
6.2.20 PMLIMITU6 - Prefetchable Memory Limit Address Upper.............................100
6.2.21 CAPPTR6 - Capabilities Pointer................................................................101
6.2.22 INTRLINE6 - Interrupt Line ....................................................................101
6.2.23 INTRPIN6 - Interrupt Pin........................................................................102
6.2.24 BCTRL6 - Bridge Control........................................................................102
6.2.25 PM_CAPID6 - Power Management Capabilities ..........................................104
6.2.26 PM_CS6 - Power Management Control/Status...........................................105
6.2.27 SS_CAPID - Subsystem ID and Vendor ID Capabilities...............................107
6.2.28 SS - Subsystem ID and Subsystem Vendor ID..........................................107
6.2.29 MSI_CAPID - Message Signaled Interrupts Capability ID ............................108
6.2.30 MC - Message Control............................................................................108
6.2.31 MA - Message Address...........................................................................110
6.2.32 MD - Message Data...............................................................................110
6.2.33 PEG_CAPL - PCI Express-G Capability List................................................111
6.2.34 PEG_CAP - PCI Express-G Capabilities .....................................................111
6.2.35 DCAP - Device Capabilities.....................................................................112
6.2.36 DCTL - Device Control ...........................................................................113
6.2.37 DSTS - Device Status............................................................................114
6.2.38 LCAP - Link Capabilities .........................................................................115
6.2.39 LCTL - Link Control ...............................................................................118
6.2.40 LSTS - Link Status ................................................................................120
6.2.41 SLOTCAP - Slot Capabilities....................................................................122
6.2.42 SLOTCTL - Slot Control..........................................................................123
6.2.43 SLOTSTS - Slot Status...........................................................................126
6.2.44 RCTL - Root Control ..............................................................................128
6.2.45 RSTS - Root Status...............................................................................129
6.2.46 LCTL2 - Link Control 2...........................................................................129
6.2.47 LSTS2 - Link Status 2............................................................................131
6.2.48 PEGLC - PCI Express-G Legacy Control ....................................................132
6.3 PCI Device 6 - Extended Configuration................................................................133
6.3.1 VCECH - Virtual Channel Enhanced Capability Header................................133
6.3.2 PVCCAP1 - Port VC Capability Register 1..................................................133
6.3.3 PVCCAP2 - Port VC Capability Register 2..................................................134
6.3.4 PVCCTL - Port VC Control.......................................................................135
6.3.5 VC0RCAP - VC0 Resource Capability........................................................135
6.3.6 VC0RCTL - VC0 Resource Control............................................................136
6.3.7 VC0RSTS - VC0 Resource Status.............................................................137

Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505 Series
April 2010 Datasheet Addendum
Document Number: 323178-002 5
Figures
1Intel
®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor P4500, P4505
Series on the Intel®CoreTM i7 processor based low-power platform.................................9
2Intel
®Flex Memory Technology Operation................................................................... 17
3 Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes ..................18
4 PCI Express* Related Register Structures in the
Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505
Series.....................................................................................................................20
5Intel
®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505
Series Ballmap
(Top View, Upper-Left Quadrant) ...............................................................................28
6Intel
®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505
Series Ballmap
(Top View, Upper-Right Quadrant) .............................................................................29
7Intel
®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505
Series Ballmap
(Top View, Lower-Left Quadrant) ...............................................................................30
8Intel
®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505
Series Ballmap
(Top View, Lower-Right Quadrant) .............................................................................31
Tables
1 Processor Documents ...............................................................................................13
2 PCH Documents.......................................................................................................14
3 Public Specifications ................................................................................................. 14
4 Supported DIMM Module Configurations ...................................................................... 15
5 DDR3 System Memory Timing Support........................................................................16
6 Signal Description Buffer Types..................................................................................21
7 Memory Channel A...................................................................................................21
8 Memory Channel B...................................................................................................23
9 Reset and Miscellaneous Signals ................................................................................24
10 Mobile Signal Groups1 ..............................................................................................25
11 DDR3 Signal Group DC Specifications .........................................................................25
12 Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505
Series Ball List by Ball Name .....................................................................................32
13 Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505
Series Ball List by Ball Number ..................................................................................49
14 Register Terminology................................................................................................69
15 DEVEN - Device Enable Register.................................................................................71
16 Error Status Register................................................................................................72
17 Error Command Registers .........................................................................................74
18 SMI Command Registers...........................................................................................75
19 Channel 0 Write Data Control Registers.......................................................................76
20 Channel 0 ECC Error Registers...................................................................................77
21 Channel 1 Write Data Control Registers.......................................................................79
22 Channel 1 ECC Error Registers...................................................................................80
23 PCI Device 6 Register ...............................................................................................81
24 VID6 - Vendor Identification Register..........................................................................84
25 DID6 - Device Identification Register .......................................................................... 84
26 PCICMD6 - PCI Command Register.............................................................................85
27 PCISTS6 - PCI Status Register...................................................................................87
28 RID6 - Revision Identification Register........................................................................89
29 CC6 - Class Code Register.........................................................................................89
30 CL6 - Cache Line Size Register...................................................................................90
31 HDR6 - Header Type Register ....................................................................................90
32 PBUSN6 - Primary Bus Number Register......................................................................91

Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505 Series
Datasheet Addendum April 2010
6Document Number: 323178-002
33 SBUSN6 - Secondary Bus Number Register ..................................................................91
34 SUBUSN6 - Subordinate Bus Number Register..............................................................92
35 IOBASE6 - I/O Base Address Register .........................................................................93
36 IOLIMIT6 - I/O Limit Address Register.........................................................................93
37 SSTS6 - Secondary Status Register.............................................................................94
38 MBASE6 - Memory Base Address Register....................................................................95
39 MLIMIT6 - Memory Limit Address Register ...................................................................96
40 PMBASE6 - Prefetchable Memory Base Address Register ................................................97
41 PMLIMIT6 - Prefetchable Memory Limit Address Register................................................98
42 PMBASEU6 - Prefetchable Memory Base Address Upper Register.....................................99
43 PMLIMITU6 - Prefetchable Memory Limit Address Upper Register ..................................100
44 CAPPTR6 - Capabilities Pointer Register .....................................................................101
45 INTRLINE6 - Interrupt Line Register..........................................................................101
46 INTRPIN6 - Interrupt Pin Register.............................................................................102
47 BCTRL6 - Bridge Control Register .............................................................................102
48 PM_CAPID6 - Power Management Capabilities Register................................................104
49 PM_CS6 - Power Management Control/Status Register ................................................105
50 SS_CAPID - Subsystem ID and Vendor ID Capabilities Register ....................................107
51 SS - Subsystem ID and Subsystem Vendor ID Register................................................107
52 MSI_CAPID - Message Signaled Interrupts Capability ID Register..................................108
53 MC - Message Control Register.................................................................................108
54 MA - Message Address Register................................................................................110
55 MD - Message Data Register ....................................................................................110
56 PEG_CAPL - PCI Express-G Capability List Register......................................................111
57 PEG_CAP - PCI Express-G Capabilities Register...........................................................111
58 DCAP - Device Capabilities Register ..........................................................................112
59 DCTL - Device Control Register.................................................................................113
60 DSTS - Device Status Register .................................................................................114
61 LCAP - Link Capabilities Register...............................................................................115
62 LCTL - Link Control Register.....................................................................................118
63 LSTS - Link Status Register......................................................................................120
64 SLOTCAP - Slot Capabilities Register .........................................................................122
65 SLOTCTL - Slot Control Register ...............................................................................123
66 SLOTSTS - Slot Status Register ................................................................................126
67 RCTL - Root Control Register....................................................................................128
68 RSTS - Root Status Register ....................................................................................129
69 LCTL2 - Link Control 2 Register ................................................................................129
70 LSTS2 - Link Status 2 Register .................................................................................131
71 PEGLC - PCI Express-G Legacy Control Register..........................................................132
72 PCI Device 6 - Extended Configuration ......................................................................133
73 VCECH - Virtual Channel Enhanced Capability Header..................................................133
74 PVCCAP1 - Port VC Capability Register 1....................................................................134
75 PVCCAP2 - Port VC Capability Register 2....................................................................135
76 PVCCTL - Port VC Control ........................................................................................135
77 VC0RCAP - VC0 Resource Capability..........................................................................135
78 VC0RCTL - VC0 Resource Control..............................................................................137
79 VC0RSTS - VC0 Resource Status ..............................................................................138

Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505 Series
April 2010 Datasheet Addendum
Document Number: 323178-002 7
Revision History
Date Revision Description
January 2010 001 • Initial release of this document.
April 2010 002 • Added information for the Intel® Celeron® Processor P4500 and P4505 Series.
•CorrectedfirstbulletinSection 2.1.1 to “No support for mixed ECC and non-ECC DIMM
configurations.”

Introduction and Features Summary
Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505 Series
Datasheet Addendum April 2010
8Document Number: 323178-002
1 Introduction and Features
Summary
1.1 Introduction
This Datasheet Addendum is a supplement to the Intel® CoreTM i7-600, i5-500 and i3-
300 Mobile Processor Series Datasheet. It contains the additional DC and AC electrical
specifications, signal integrity, differential signaling specifications, pinout and signal
definitions, interface functional descriptions, additional feature information and
configuration registers pertinent to the implementation and operation of the Intel®
CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505
Series on its respective platform.
Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500,
P4505 Series is the next generation of 64-bit, multi-core mobile processor built on a
32- nanometer process technology. Throughout this document, Intel®CoreTM i7-
620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505 Series may
be referred to as simply the processor. The processor is designed for a two-chip
platform as opposed to the traditional three-chip platforms (processor, GMCH, and
ICH). The two-chip platform consists of a processor and the Platform Controller Hub
(PCH) and enables higher performance, lower cost, easier validation, and improved x-y
footprint. The PCH may also be referred to as Mobile Intel® 5 Series Chipset (formerly
Ibex Peak-M). Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®
Processor P4500, P4505 Series is designed for the Intel®CoreTM i7 processor based
low-power platform and is offered in a BGA1288 package.
Included in this family of processors is an integrated graphics and memory controller
die on the same package as the processor core die. This two-chip solution of a
processor core die with an integrated graphics and memory controller die is known as a
multi-chip package (MCP) processor.
Note: Integrated graphics and memory controller die is built on 45-nanometer process
technology.

Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505 Series
April 2010 Datasheet Addendum
Document Number: 323178-002 9
Introduction and Features Summary
Figure 1. Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel® Celeron® Processor
P4500, P4505 Series on the Intel®CoreTM i7 processor based low-power
platform
Intel CoreTM i7/i5 and Celeron
Processor
(MCPProcessor)
Discrete Graphics
(PEG)
Analog CRT
Gigabit
Network Connection
USB2.0
Intel® HD Audio
FWH
TPM1.2
Super I/O
PCI
Serial ATA
Mobile Intel 5 SeriesChipset
PCH
DDR3 DIMMs
PCI Express* x16
14 Por
ts
PCI
6 Ports
3 Gb/s
SPI
Digital Display x 3
Intel®Flexible
Display Int erf ace
SPI Flash
LPC
SMBUS 2 .0
PECI
GPIO
OR
GPU, Memory
Cont rol ler
Dual-core
Processor
800/1066 MT/s
2 Channels
1 DIMM/ Channel
DMI2
(x4)
LVDSFlat Panel
Intel®
Management
Engine
Embedded
DisplayPort* (eDP)
PCI Express x 1
PCI Express*
Controller Link 1
8 PCI Express* x1
Ports
(2.5 GT/s)

Introduction and Features Summary
Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505 Series
Datasheet Addendum April 2010
10 Document Number: 323178-002
1.2 Interfaces
1.2.1 System Memory Support
• One or two channels of DDR3 memory with a maximum of one DIMM per channel
• Single- and dual-channel memory organization modes
• Data burst length of eight for all memory organization modes
• Memory DDR3 data transfer rates of 800 and 1066 MT/s
• 64-bit wide channels (72-bit wide including ECC)
• DDR3 I/O Voltage of 1.5 V
• Supports ECC and non-ECC, unbuffered DDR3 DIMMs
— Mixing of ECC and Non-ECC DIMMS is not supported
• Theoretical maximum memory bandwidth of:
— 12.8 GB/s in dual-channel mode assuming DDR3 800 MT/s
— 17.1 GB/s in dual-channel mode assuming DDR3 1066 MT/s
• 1-Gb, and 2-Gb DDR3 DRAM technologies for x8 and x16 devices
• Using 2-Gb device technologies, the largest memory capacity possible is 8 GB,
assuming dual-channel mode with two x8, dual-rank, un-buffered, DIMM memory
configuration.
• Up to 32 simultaneous open pages, 16 per channel (assuming 4 Ranks of 8 Bank
Devices)
• Memory organizations:
— Single-channel modes
— Dual-channel modes
Dual-channel symmetric (Interleaved)
Dual-channel asymmetric
Intel®Flex Memory Technology
• Command launch modes of 1n/2n
• Partial Writes to memory using Data Mask (DM) signals
• On-Die Termination (ODT)
•Intel
®Fast Memory Access (Intel®FMA):
— Just-in-Time Command Scheduling
—CommandOverlap
— Out-of-Order Scheduling
1.2.2 PCI Express*
• The processor PCI Express* port(s) are fully-compliant to the PCI Express Base
Specification, Revision 2.0 at 2.5GT/s.
• The processor supports:
— One 16-lane PCI Express port for graphics or I/O.
— Two 8-lane PCI Express ports for graphics or I/O.
• PCI Express Port 0 is mapped to PCI Device 1.
• PCI Express Port 1 is mapped to PCI Device 6.

Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505 Series
April 2010 Datasheet Addendum
Document Number: 323178-002 11
Introduction and Features Summary
1.3 Package
The Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel Celeron Processor P4500,
P4505 Series are available on a 34 x 28 mm BGA package (BGA1288).
Note: Although the BGA1288 package is shared with Intel®CoreTM i7-640UM/LM, i7-620M/
UM/LM, i5-540M, i5-520M/UM and i5-430M Processor Series they are not ball-out
compatible.

Introduction and Features Summary
Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505 Series
Datasheet Addendum April 2010
12 Document Number: 323178-002
1.4 Terminology
Term Description
BLT Block Level Transfer
CRT Cathode Ray Tube
DDR3 Third generation Double Data Rate SDRAM memory technology
DP DisplayPort*
DMA Direct Memory Access
DMI Direct Media Interface
DTS Digital Thermal Sensor
ECC Error Correction Code
eDP* Embedded DisplayPort*
Intel®DPST Intel®Display Power Saving Technology
Enhanced Intel
SpeedStep®Technology Technology that provides power management capabilities to laptops.
Execute Disable Bit
The Execute Disable bit allows memory to be marked as executable or non-
executable, when combined with a supporting operating system. If code
attempts to run in non-executable memory the processor raises an error to the
operating system. This feature can prevent some classes of viruses or worms
that exploit buffer overrun vulnerabilities and can thus help improve the overall
security of the system. See the Intel® 64 and IA-32 Architectures Software
Developer's Manuals for more detailed information.
EU Execution Unit
(G)MCH Legacy component - Graphics Memory Controller Hub.
GPU Graphics Processing Unit
ICH The legacy I/O Controller Hub component that contains the main PCI interface, LPC interface, USB2, Serial ATA, and other I/O functions. It communicates with
the legacy (G)MCH over a proprietary interconnect called DMI.
IMC Integrated Memory Controller
Intel®64 Technology 64-bit memory extensions to the IA-32 architecture.
Intel®FDI Intel®Flexible Display Interface.
Intel®TXT Intel®Trusted Execution Technology
Intel®Virtualization
Technology Processor virtualization which when used in conjunction with Virtual Machine
Monitor software enables multiple, robust independent software environments
inside a single platform.
ITPM Integrated Trusted Platform Module
IOV I/O Virtualization
LCD Liquid Crystal Display
LVDS Low Voltage Differential Signaling
A high speed, low power data transmission standard used for display connections
to LCD panels.
MCP Multi-Chip Package
NCTF Non-Critical to Function: NCTF locations are typically redundant ground or non- critical reserved, so the loss of the solder joint continuity at end of life conditions
will not affect the overall product functionality.
PCH
Platform Controller Hub. The new 2009 chipset with centralized platform
capabilities including the main I/O interfaces along with display connectivity,
audio features, power management, manageability, security and storage
features. The PCH may also be referred to using the code name Ibex Peak.
PECI Platform Environment Control Interface

Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505 Series
April 2010 Datasheet Addendum
Document Number: 323178-002 13
Introduction and Features Summary
1.5 Related Documents
Refer to the documents in Table 1 for additional information.
PEG PCI Express* Graphics. External Graphics using PCI Express Architecture. A high-speed serial interface whose configuration is software compatible with the
existing PCI specifications.
Processor The 64-bit, single-core or multi-core component (package)
Processor Core The term “processor core” refers to Si die itself which can contain multiple execution cores. Each execution core has an instruction cache, data cache, and
256-KB L2 cache. All execution cores share the L3 cache.
Rank A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC. These devices are usually, but not always, mounted on a single side of a SO-
DIMM.
SCI System Control Interrupt. Used in ACPI protocol.
Storage Conditions
A non-operational state. The processor may be installed in a platform, in a tray,
or loose. Processors may be sealed in packaging or exposed to free air. Under
these conditions, processor landings should not be connected to any supply
voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air”
(i.e., unsealed packaging or a device removed from packaging material) the
processor must be handled in accordance with moisture sensitivity labeling
(MSL) as indicated on the packaging material.
TAC Thermal Averaging Constant
TDP Thermal Design Power
TOM Top of Memory
TTM Time-To-Market
VCC Processor core power supply
VSS Processor ground
VAXG Graphics core power supply
VTT L3 shared cache, memory controller, and processor I/O power rail
VDDQ DDR3 power rail
VLD Variable Length Decoding
x1 Refers to a Link or Port with one Physical Lane
x4 Refers to a Link or Port with four Physical Lanes
x8 Refers to a Link or Port with eight Physical Lanes
x16 Refers to a Link or Port with sixteen Physical Lanes
Term Description
Table 1. Processor Documents
Document Document Number/
Location
Intel® CoreTM i7-600, i5-500 and i3-300 Mobile Processor Series Datasheet http://www.intel.com
Intel®CoreTM i7-620LE/UE, i7-610E and i5-520E Processor Series Datasheet
Addendum Specification Update http://www.intel.com

Introduction and Features Summary
Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505 Series
Datasheet Addendum April 2010
14 Document Number: 323178-002
§ §
Table 2. PCH Documents
Document Document Number/
Location
Intel® 5 Series Chipset and Intel® 3400 Series Chipset Datasheet http://www.intel.com
Table 3. Public Specifications
Document Document Number/
Location
Advanced Configuration and Power Interface Specification 3.0 http://www.acpi.info/
PCI Local Bus Specification 3.0 http://www.pcisig.com/
specifications
PCI Express Base Specification 2.0 http://www.pcisig.com
DDR3 SDRAM Specification http://www.jedec.org
DisplayPort Specification http://www.vesa.org
Intel®64 and IA-32 Architectures Software Developer's Manuals http://www.intel.com/
products/processor/
manuals/index.htm
Volume 1: Basic Architecture 253665
Volume 2A: Instruction Set Reference, A-M 253666
Volume 2B: Instruction Set Reference, N-Z 253667
Volume 3A: System Programming Guide 253668
Volume 3B: System Programming Guide 253669

Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505 Series
April 2010 Datasheet Addendum
Document Number: 323178-002 15
Interfaces
2Interfaces
This chapter describes the interfaces supported by the processor.
2.1 System Memory Interface
2.1.1 System Memory Technology Supported
The Integrated Memory Controller (IMC) supports DDR3 protocols with two,
independent, 64-bit wide channels each accessing one DIMM. It supports:
— ECC and non-ECC un-buffered DIMMs. No support for mixed ECC and non-ECC
DIMM configurations.
DDR3 Data Transfer Rates:
— 800 MT/s (PC3-6400), and 1066 MT/s (PC3-8500)
• DDR3 DIMM Modules:
— Raw Card A – single rank x8 unbuffered non-ECC
— Raw Card B – dual rank x8 unbuffered non-ECC
— Raw Card C – single rank x16 unbuffered non-ECC
— Raw Card D – single rank x8 unbuffered ECC
— Raw Card E – dual rank x8 unbuffered ECC
— Raw Card F - dual rank x16 unbuffered non-ECC
• DDR3 DRAM Device Technology:
— Standard 1-Gb, and 2-Gb technologies and addressing are supported for x16
and x8 devices. There is no support for memory modules with different
technologies or capacities on opposite sides of the same memory module. If
one side of a memory module is populated, the other side is either identical or
empty.
Table 4. Supported DIMM Module Configurations (Sheet 1 of 2)
Raw
Card
Version
DIMM
Capacity
DRAM
Device
Technology
DRAM
Organization
# of
DRAM
Devices
# of
Physical
Device
Ranks
# of Row/
Col
Address
Bits
# of
Banks
Inside
DRAM
Page
Size
A
512 MB 512 Mb 64 M x 8 8 1 13/10 8 8K
1 GB 1 Gb 128 M x 8 8 1 14/10 8 8K
2 GB 2 Gb 256M x 8 8 1 15/10 8 8K
B
1 GB 512 Mb 64 M x 8 16 2 13/10 8 8K
2 GB 1 Gb 128 M x 8 16 2 14/10 8 8K
4 GB 2 Gb 256 M x 8 16 2 15/10 8 8K
C
256MB 512 Mb 32 M x 16 4 1 12/10 8 8K
512 MB 1 Gb 64 M x 8 4 1 13/10 8 8K
1 GB 2 Gb 128 M x 16 4 1 14/10 8 8K

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2.1.2 System Memory Timing Support
The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
• tCL = CAS Latency
• tRCD = Activate Command to READ or WRITE Command delay
• tRP = PRECHARGE Command Period
•CWL=CASWriteLatency
• Command Signal modes = 1n indicates a new command may be issued every clock
and 2n indicates a new command may be issued every 2 clocks. Command launch
mode programming depends on the transfer rate and memory configuration.
2.1.3 System Memory Organization Modes
The IMC supports two memory organization modes, single-channel and dual-channel.
Depending upon how the DIMM Modules are populated in each memory channel, a
number of different configurations can exist.
2.1.3.1 Single-Channel Mode
In this mode, all memory cycles are directed to a single-channel. Single-channel mode
is used when either Channel A or Channel B DIMM connectors are populated in any
order, but not both.
D
512 MB 512 Mb 64 M x 8 9 1 13/10 8 8K
1 GB 1 Gb 128 M x 8 9 1 14/10 8 8K
2 GB 2 Gb 256 M x 8 9 1 15/10 8 8K
E
1 GB 512 Mb 64M x 8 18 2 13/10 8 8K
2 GB 1 Gb 128 M x 8 18 2 14/10 8 8K
4 GB 2 Gb 256 M x 8 18 2 15/10 8 8K
F
512 MB 512 Mb 32 M x 16 8 2 12/10 8 8K
1 GB 1 Gb 64 M x 16 8 2 13/10 8 8K
2 GB 2 Gb 128 M x 16 8 2 14/10 8 8K
Table 4. Supported DIMM Module Configurations (Sheet 2 of 2)
Raw
Card
Version
DIMM
Capacity
DRAM
Device
Technology
DRAM
Organization
# of
DRAM
Devices
# of
Physical
Device
Ranks
# of Row/
Col
Address
Bits
# of
Banks
Inside
DRAM
Page
Size
Table 5. DDR3 System Memory Timing Support
Transfer
Rate
(MT/s)
tCL
(tCK) tRCD (tCK) tRP (tCK) CWL (tCK) CMD Mode Notes
800 6 6 6 5 1n and 2n 1
1066 777 61nand2n 1
888
NOTES:
1. System Memory timing support is based on availability and is subject to change.

Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505 Series
April 2010 Datasheet Addendum
Document Number: 323178-002 17
Interfaces
2.1.3.2 Dual-Channel Mode - Intel®Flex Memory Technology Mode
The IMC supports Intel®Flex Memory Technology Mode. This mode combines the
advantages of the Dual-Channel Symmetric (Interleaved) and Dual-Channel
Asymmetric Modes. Memory is divided into a symmetric and a asymmetric zone. The
symmetric zone starts at the lowest address in each channel and is contiguous until the
asymmetric zone begins or until the top address of the channel with the smaller
capacity is reached. In this mode, the system runs with one zone of dual-channel mode
and one zone of single-channel mode, simultaneously, across the whole memory array.
2.1.3.2.1 Dual-Channel Symmetric Mode
Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum
performance on real world applications. Addresses are ping-ponged between the
channels after each cache line (64-byte boundary). If there are two requests, and the
second request is to an address on the opposite channel from the first, that request can
be sent before data from the first request has returned. If two consecutive cache lines
are requested, both may be retrieved simultaneously, since they are ensured to be on
opposite channels. Use Dual-Channel Symmetric mode when both Channel A and
Channel B DIMM connectors are populated in any order, with the total amount of
memory in each channel being the same.
When both channels are populated with the same memory capacity and the boundary
between the dual channel zone and the single channel zone is the top of memory, IMC
operates completely in Dual-Channel Symmetric mode.
Note: The DRAM device technology and width may vary from one channel to the other.
2.1.3.2.2 Dual-Channel Asymmetric Mode
This mode trades performance for system design flexibility. Unlike the previous mode,
addresses start at the bottom of Channel B and stay there until the end of the highest
rank in Channel B, and then addresses continue from the bottom of Channel A to the
top. Real world applications are unlikely to make requests that alternate between
addresses that sit on opposite channels with this memory organization, so in most
cases, bandwidth is limited to a single channel.
Figure 2. Intel®Flex Memory Technology Operation
CH BCH A
CH BCH A
B B
C
BB
C
B
B
CNon interleaved
access
Dual channel
interleaved access
TOM
B – The largest physical memory amount of the smaller size memory module
C – The remaining physical memory amount of the larger size memory module

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Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505 Series
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This mode is used when Intel®Flex Memory Technology is disabled and both Channel A
and Channel B DIMM connectors are populated in any order with the total amount of
memory in each channel being different.
2.1.4 Rules for Populating Memory Slots
In all modes, the frequency of system memory is the lowest frequency of all memory
modules placed in the system, as determined through the SPD registers on the
memory modules. The system memory controller supports only one DIMM connector
per channel.For dual-channel modes both channels must have an DIMM connector
populated and for single-channel mode only a single-channel must have an DIMM
connector populated.
2.1.5 Technology Enhancements of Intel®Fast Memory Access
(Intel®FMA)
The following sections describe the Just-in-Time Scheduling, Command Overlap, and
Out-of-Order Scheduling Intel®FMA technology enhancements.
2.1.5.1 Just-in-Time Command Scheduling
The memory controller has an advanced command scheduler where all pending
requests are examined simultaneously to determine the most efficient request to be
issued next. The most efficient request is picked from all pending requests and issued
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,
instead of having all memory access requests go individually through an arbitration
mechanism forcing requests to be executed one at a time, they can be started without
Figure 3. Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes
CH. B
CH. A
CH. B
CH. A
CH. B
CH. A
CL
0
Top of
Memory
CL
0
CH. A
CH. B CH.B-top
DRB
Dual Channel Interleaved
(memory sizes must match) Dual Channel Asymmetric (memory sizes can differ)
Top of
Memory

Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor P4500, P4505 Series
April 2010 Datasheet Addendum
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Interfaces
interfering with the current request allowing for concurrent issuing of requests. This
allows for optimized bandwidth and reduced latency while maintaining appropriate
command spacing to meet system memory protocol.
2.1.5.2 Command Overlap
Command Overlap allows the insertion of the DRAM commands between the Activate,
Precharge, and Read/Write commands normally used, as long as the inserted
commands do not affect the currently executing command. Multiple commands can be
issued in an overlapping manner, increasing the efficiency of system memory protocol.
2.1.5.3 Out-of-Order Scheduling
While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,
the IMC continuously monitors pending requests to system memory for the best use of
bandwidth and reduction of latency. If there are multiple requests to the same open
page, these requests would be launched in a back to back manner to make optimum
use of the open memory page. This ability to reorder requests on the fly allows the IMC
to further reduce latency and increase bandwidth efficiency.
2.1.6 DRAM Clock Generation
Two differential clock pairs for every supported DIMM. There are total of four clock pairs
driven directly by the processor to two DIMMs.
2.1.7 DDR3 On-Die Termination
On-Die Termination (ODT) is a feature that allows a DRAM device to turn on/off internal
termination resistance for each DQ, DQS/DQS#, and DM signal via the ODT control pin.
The ODT feature improves signal integrity of the memory channel by allowing the
DRAM controller to independently turn on or off the termination resistance for any or all
DRAM devices themselves instead of on the motherboard.
The IMC drives out the required ODT signals, based on the memory configuration and
which rank is being written to or read from, to the DRAM devices on a targeted DIMM
module rank to enable or disable their termination resistance.
2.2 PCI Express* Interface
This section describes the PCI Express* interface capabilities of the processor. See the
PCI Express Base Specification for further details on PCI Express.
The processor has two options for PCI Express controllers available:
• 1 x16 PCI Express Port
or
•2x8PCIExpressPorts
— Enabled with CFG[0] strapping, see Section 2.2.2 and Section 3.2
2.2.1 PCI Express* Configuration Mechanism
The PCI Express* link is mapped through a PCI-to-PCI bridge structure.

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Datasheet Addendum April 2010
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2.2.2 PCI Express Port Bifurcation
When bifurcated, the wires which had previously been assigned to lanes 15:8 of the
single x16 primary port (Port 0) are reassigned to lanes 7:0 of the x8 secondary port
(Port 1). This assignment applies whether the lane numbering is reversed or not. The
controls for the secondary port (Port 1) and the associated virtual PCI-to-PCI bridge
can be found in PCI Device 6.
When the primary port is not bifurcated, Device 6 is hidden from the discovery
mechanism used in PCI enumeration, such that configuration of the device is neither
possible nor necessary.
Figure 4. PCI Express* Related Register Structures in the
Intel®CoreTM i7-620LE/UE, i7-610E, i5-520E and Intel®Celeron®Processor
P4500, P4505 Series
PCI-PCI Bridge
representing root
PCI Express port
(Device 1)
PCI-PCI Bridge
representing root
PCI Express port
(Device 6)
PCI Compatible
Host Bridge Device
(Device 0)
PCI Express
Device
PCI Express
Device
Port 0
Port 1
DMI