Intel i86W User manual

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i860™
64-BIT
MICROPROCESSOR
PROGRAMMER'S
REFERENCE MANUAL
1990

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Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before placing your order.
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©INTEL CORPORATION 1987, 1988, 1989 CG·101789

PREFACE
The Intel i86W
M Microprocessor (part number 80860XR) delivers supercomputer perfor-
mance in a single VLSI component. The 64-bit design
of the i860 microprocessor bal-
ances integer, floating point, and graphics performance for applications such as
engineering workstations, scientific computing, 3-D graphics workstations, and multiuser
systems. Its parallel architecture achieves high throughput with RISC design techniques,
pipelined processing units, wide data paths, large on-chip caches, and fast one micron
CHMOS IV silicon technology.
This book
is the basic source of the detailed information that enables software designers
and programmers to use the i860 microprocessor. This book explains
all programmer-
visible features
of the architecture.
Even though the principal users
of this Programmer's Reference Manual will be pro-
grammers, it contains information that
is of value to systems designers and administra-
tors
of software projects, as well. Readers of these latter categories may choose only to
read the higher-level sections
of the manual, skipping over much of the programmer-
oriented detail.
HOW TO USE THIS MANUAL
• Chapter 1, "Architectural Overview," describes the i860 microprocessor "in a nut-
shell" and presents for the first time the terms that
will be used throughout the book.
• Chapter 2, "Data Types," defines the basic units operated on by the instructions of
the i860 microprocessor.
• Chapter 3, "Registers," presents the processor's database. A detailed knowledge of
the registers is important to programmers, but this chapter may be skimmed by
administrators.
• Chapter 4, "Addressing," presents the details of operand alignment, page-oriented
virtual memory, and on-chip caches. Systems designers and administrators may
choose to read the introductory sections
of each topic.
• Chapter 5, "Core Instructions," presents detailed information about those instruc-
tions that deal with memory addressing, integer arithmetic, and control
flow.
• Chapter 6, "Floating-Point Instructions," presents detailed information about those
instructions that deal with floating-point arithmetic, long-integer arithmetic, and 3-D
graphics support. This chapter explains how extremely high performance can be
achieved
by utilizing the parallelism and pipelining of the i860 microprocessor.
• Chapter 7, "Traps and Interrupts," deals with both systems- and applications-
oriented exceptions, external interrupts, writing exception handlers, saving the state
of the processor (information that is also useful for task switching), and initialization.
• Chapter 8, "Programming Model," defines standards for the use of many features of
the i860 microprocessor. Software administrators should be aware of the need for
standards and should ensure that they are implemented. Following the standards
presented here guarantees that compilers, applications programs, and operating
sys-
tems written by different people and organizations will all work together.
iii

PREFACE
• Chapter 9, "Programming Examples," illustrates the use of the i860 microprocessor
by presenting short code sequences in assembly language.
• The appendices present instruction formats and encodings, timing information, and
summaries of instruction characteristics. These appendices are of most interest to
assembly-language programmers and to writers of assemblers, compilers, and
debuggers.
RELATED DOCUMENTATION
The following books contain additional material concerning the i860 microprocessor:
• i860™ 64-Bit Microprocessor (Data Sheet), order number 240296
• i860™ 64-Bit Microprocessor Assembler and Linker Reference Manual, order number
240436
• i860™ 64-Bit Microprocessor Simulator-Debugger Reference Manual, order number
240437
NOTATION AND CONVENTIONS
The instruction chapters contain an algorithmic description of each instruction that uses
a notation similar to that of the Algol or Pascal languages. The metalanguage uses the
following special symbols:
• A ~ B indicates that the value of B is assigned to A.
• Compound statements are enclosed between the keywords of the "if' statement (IF
... , THEN
... , ELSE ... , FI) or of the "do" statement (DO ... , OD).
• The operator ++ indicates autoincrement addressing.
• Register names and instruction mnemonics are printed in a contrasting typestyle to
make them stand out from the text; for example, dirbase. Individual programming
languages may require the use of lowercase letters.
Hexadecimal constants are written, according to the C language convention, with the
prefix
Ox. For example, OxOF is a hexadecimal number that is equivalent to decimal 15.
RESERVED BITS AND SOFTWARE COMPATIBILITY
In many register and memory layout descriptions, certain bits are marked as reserved or
undefined. When bits are thus marked, it is essential for compatibility with future pro-
cessors that software not utilize these bits. Software should follow these guidelines in
dealing with reserved or undefined bits:
• Do not depend on the states of any reserved or undefined bits when testing the values
of registers that contain such bits. Mask out the reserved and undefined bits before
testing.
• Do not depend on the states of any reserved or undefined bits when storing them in
memory or in another register.
iv

PREFACE
• Do not depend on the ability to retain information written into any reserved or
undefined bits.
• When loading a control register, always load the reserved and undefined bits with
values previously retrieved from the same register.
NOTE
Depending upon the values of reserved or undefined bits makes software depen-
dent upon the unspecified manner in which the i860 microprocessor handles
these bits. Depending upon values
of reserved or undefined bits risks making
software incompatible with future
processor~ that define usages for these bits.
AVOID ANY SOFTWARE DEPENDENCE UPON THE STATE OF RESERVED
OR UNDEFINED BITS.
v

CUSTOMER SUPPORT
INTEL'S COMPLETE SUPPORT SOLUTION WORLDWIDE
Customer Support is Intel's complete support service that provides Intel customers with hardware support,
software support, customer training, consulting services and network management services.
For detailed infor-
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After a customer purchases any system hardware
or software product, service and support become major
factors in determining whether that product will continue to meet a customer's expectations. Such support
requires an international support organization and a breadth of programs to meet a variety of customer needs.
As you might expect, Intel's customer support is quite extensive. It can start with assistance during your
development effort to network management. 100 Intel sales and service offices are located worldwide - in the
U.S., Canada, Europe and the Far East. So wherever you're using Intel technology, our professional staff is
within close reach.
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or board level products can be
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environments which represent product groupings (e.g., iRMX® environment).
CONSULTING SERVICES
Intel provides field system engineering consulting services for any phase of your development or application
effort. You can use our system engineers in a variety of ways ranging from assistance in using a new product,
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we know
our products. Working together we can help you get a successful product to market in the least
possible time.
CUSTOMER TRAINING
Intel offers a wide range of instructional programs covering various aspects of system design and implementa-
tion. In just three to ten days a limited number of individuals learn more in a single workshop than in weeks of
self-study. For optimum convenience, workshops are scheduled regularly at Training Centers worldwide or we
can take our workshops to you for on-site instruction. Covering a wide variety of topics, Intel's major course
categories include: architecture and assembly language, programming and operating systems, BITBUS™ and
LAN applications.
NETWORK MANAGEMENT SERVICES
Today's networking products are powerful and extremely flexible. The return they can provide on your invest-
ment via increased productivity and reduced costs can be very substantial.
Intel offers complete network support, from definition
of your network's physical and functional design, to
implementation, installation and maintenance.
Whether installing your first network or adding to an existing
one, Intel's Networking Specialists can optimize network performance for you.
CG/CUSTSUPP/l00389

TABLE OF CONTENTS
CHAPTER 1 Page
ARCHITECTURAL OVERVIEW
1.1 OVERVIEW ...................................................................................................................... 1-1
1.2 INTEGER CORE UNIT .................................................................................................... 1-3
1.3 FLOATING-POINT UNIT .................................................................................................. 1-4
1.4 GRAPHICS UNIT ............................................................................................................. 1-4
1.5 MEMORY MANAGEMENT UNIT ..................................................................................... 1-5
1.6 CACHES ......................................................................................................................... 1-6
1.7 PARALLEL ARCHITECTURE ........................................................................................... 1-6
1.8 SOFTWARE DEVELOPMENT ENVIRONMENT .............................................................. 1-7
1.8.1 Multiprocessing for High-Performance with Compatibility.......................................... 1-7
CHAPTER 2
DATA TYPES
2.1 INTEGER ......................................................................................................................... 2-1
2.2 ORDINAL ......................................................................................................................... 2-1
2.3 SINGLE-PRECISION REAL ............................................................................................. 2-1
2.4 DOUBLE-PRECISION REAL ........................................................................................... 2-2
2.5 PiXEL............................................................................................................................... 2-3
2.6 REAL-NUMBER ENCODING ........................................................................................... 2-3
CHAPTER 3
REGISTERS
3.1 INTEGER REGISTER FILE .............................................................................................. 3-2
3.2 FLOATING-POINT REGISTER FILE ................................................................................ 3-2
3.3 PROCESSOR STATUS REGISTER ................................................................................ 3-2
3.4 EXTENDED PROCESSOR STATUS REGISTER ............................................................ 3-4
3.5 DATA BREAKPOINT REGISTER ..................................................................................... 3-6
3.6 DIRECTORY BASE REGISTER ....................................................................................... 3-6
3.7 FAULT INSTRUCTION REGISTER ................................................................................. 3-8
3.8 FLOATING-POINT STATUS REGISTER ......................................................................... 3-8
3.9
KR, KI, T, AND MERGE REGISTERS ........................................................................... 3-11
CHAPTER 4
ADDRESSING
4.1 ALIGNMENT .................................................................................................................... 4-1
4.2 VIRTUAL ADDRESSING .................................................................................................. 4-2
4.2.1 Page Frame ................................................................................................................. 4-3
4.2.2 Virtual Address ............................................................................................................. 4-3
4.2.3 Page Tables ................................................................................................................ 4-3
4.2.4 Page-Table Entries ..................................................................................................... 4-4
4.2.4.1 PAGE FRAME ADDRESS
... ..................................................................................... 4-4
4.2.4.2 PRESENT BIT .......................................................................................................... 4-5
4.2.4.3 CACHE DISABLE BIT
.. ............................................................................................ 4-6
4.2.4.4 WRITE-THROUGH BIT ............................................................................................. 4-6
4.2.4.5 ACCESSED AND DIRTY BITS .................................................................................. 4-6
4.2.4.6 WRITABLE AND USER BITS ................................................................................... 4-7
4.2.4.7 COMBINING PROTECTION OF BOTH LEVELS OF PAGE TABLES ..................... 4-8
4.2.5 Address Translation Algorithm ................................................................................... 4-8
4.2.6 Address Translation Faults ......................................................................................... 4-9
4.2.7 Page Translation Cache .............................................................................................. 4-9
4.3 CACHING AND CACHE FLUSHING ........................................................................... 4-10
vii

TABLE OF CONTENTS
CHAPTER 5 Page
CORE INSTRUCTIONS
5.1 LOAD INTEGER .............................................................................................................. 5-3
5.2 STORE INTEGER ............................................................................................................ 5-4
5.3 TRANSFER INTEGER TO
F-P REGISTER ...................................................................... 5-5
5.4 LOAD FLOATING-POINT ................................................................................................ 5-6
5.5 STORE FLOATING-POINT .............................................................................................. 5-8
5.6 PIXEL STORE ................................................................................................................. 5-9
5.7 INTEGER ADD AND SUBTRACT .................................................................................. 5-10
5.8 SHIFT INSTRUCTIONS ................................................................................................. 5-12
5.9 SOFTWARE TRAPS ...................................................................................................... 5-13
5.10 LOGICAL INSTRUCTIONS .......................................................................................... 5-14
5.11 CONTROL-TRANSFER INSTRUCTIONS .................................................................... 5-16
5.12 CONTROL REGISTER ACCESS ................................................................................. 5-20
5.13 CACHE FLUSH ........................................................................................................... 5-21
5.14 BUS LOCK .................................................................................................................. 5-23
CHAPTER 6
FLOATING-POINT INSTRUCTIONS
6.1 PRECISION SPECIFICATION ......................................................................................... 6-1
6.2 PIPELINED AND SCALAR OPERATIONS ...................................................................... 6-2
6.2.1 Scalar Mode................................................................................................................. 6-4
6.2.2 Pipelining Status Information ....................................................................................... 6-4
6.2.3 Precision in the Pipelines ............................................................................................ 6-4
6.2.4 Transition between Scalar and Pipelined Operations .............................,................... 6-5
6.3 MULTIPLIER INSTRUCTIONS ...........................................................................,............ 6-5
6.3.1 Floating-Point Multiply ................................................................................................. 6-7
6.3.2 Floating-Point Multiply Low.......................................................................................... 6-8
6.3.3 Floating-Point Reciprocals ........................................................................................... 6-9
6.4 ADDER INSTRUCTIONS ................................................................................................. 6-9
6.4.1 Floating-Point Add and Subtract ............................................................................... 6-10
Q.4.2 Floating-Point Compares ........................................................................................... 6-12
6.4.3 Floating-Point to Integer Conversion......................................................................... 6-13
6.5 DUAL OPERAT!ON INSTRUCTIONS ............................................................................ 6-14
6.6 GRAPHICS UNIT ........................................................................................................... 6-26
6.6.1 Long-Integer Arithmetic ............................................................................................. 6-28
6.6.2 3-D Graphics Operations ........................................................................................... 6-28
6.6.2.1 Z-BUFFER CHECK INSTRUCTIONS ...................................................................... 6-29
6.6.2.2 PIXEL ADD .............................................................................................................. 6-32
6.6.2.3 Z-BUFFER ADD ...................................................................................................... 6-36
6.6.2.4 OR WITH MERGE REGISTER ................................................................................ 6-38
6.7 TRANSFER
F-P TO INTEGER REGISTER .................................................................... 6-39
6.8 DUAL-INSTRUCTION MODE ........................................................................................ 6-40
6.8.1 Core and Floating-Point Instruction Interaction .. ~.................................................... 6-41
6.8.2 Dual-Instruction Mode Restrictions .......................................................................... 6-42
CHAPTER 7
TRAPS AND INTERRUPTS
7.1 TYPES OF TRAPS .......................................................................................................... 7-1
7.2 TRAP HANDLER INVOCATION ..................................................................................... 7-1
7.2.1 Saving State ................................................................................................................. 7-2
7.2.2 Inside the Trap Handler ...............................................:............................................... 7-3
7.2.3 Returning from the Trap Handler ................................................................................ 7-3
7.2.3.1 DETERMINING WHERE TO RESUME ..................................................................... 7-4
viii

TABLE OF CONTENTS
Page
7.2.3.2 SETTING
KNF ........................................................................................................... 7-5
7.3 INSTRUCTION FAULT .................................................................................................... 7-5
7.4 FLOATING-POINT FAULT ............................................................................................... 7-5
7.4.1 Source Exception Faults .............................................................................................. 7-6
7.4.2 Result Exception Faults ............................................................................................... 7-7
7.5 INSTRUCTION-ACCESS FAULT ..................................................................................... 7-8
7.6 DATA-ACCESS FAULT ................................................................................................... 7-8
7.7 INTERRUPT
TRAP .......................................................................................................... 7-9
7.8 RESET
TRAP ................................................................................................................... 7-9
7.9 PIPELINE PREEMPTION .............................................................................................. 7-10
7.9.1 Floating-Point Pipelines ............................................................................................. 7-10
7.9.2 Load Pipeline ............................................................................................................. 7-10
7.9.3 Graphics Pipeline .......................................................................................................
7-11
7.9.4 Examples of Pipeline Preemption ............................................................................. 7-11
CHAPTER 8
PROGRAMMING MODEL
8.1 REGISTER ASSIGNMENT .............................................................................................. 8-1
8.1.1 Integer Registers .......................................................................................................... 8-2
8.1.2 Floating-Point Registers ...............................................................................
... ............. 8-3
8.1.3 Passing Mixed Integer and Floating-Point Parameters in Registers ......................... 8-3
8.1.4 Variable Length Parameter Lists
.. ....... ... .................................................................. ... 8-3
8.2 DATA ALIGNMENT ......................................................................................................... 8-4
8.3 IMPLEMENTING A STACK ............................................................................................. 8-4
8.3.1 Stack Entry and Exit Code .......................................................................................... 8-5
8.3.2 Dynamic Memory Allocation on the Stack .................................................................. 8-6
8.4 MEMORY ORGANIZATION ............................................................................................. 8-6
CHAPTER 9
PROGRAMMING EXAMPLES
9.1 SMALL INTEGERS ..................................................................................... ... ..... .......... ... 9-1
9.2 SINGLE-PRECISION DIVIDE .......................................................................................... 9-2
9.3 DOUBLE-PRECISION DIVIDE ......................................................................................... 9-3
9.4 INTEGER MULTIPLY ....................................................................................................... 9-4
9.5 CONVERSION
FROM SIGNED INTEGER TO DOUBLE ................................................ 9-5
9.6 SIGNED INTEGER DIVIDE ............................................................................................. 9-6
9.7 STRING
COpy ................................................................................................................ 9-7
9.8 FLOATING-POINT PIPELINE .......................................................................................... 9-8
9.9 PIPELINING OF DUAL-OPERATION INSTRUCTIONS ................................................... 9-9
9.10 PIPELINING OF DOUBLE-PRECISION DUAL OPERATIONS ....................................
9-11
9.11 DUAL INSTRUCTION MODE ...................................................................................... 9-13
9.12 CACHE STRATEGIES
FOR MATRIX DOT PRODUCT ............................................... 9-15
9.13 3-D RENDERING ........................................................................................................
9-21
9.13.1 Distance Interpolation .............................................................................................. 9-22
9.13.2 Color Interpolation .......................................................
... ............................ ... ....... ... 9-25
9.13.3 Boundary Conditions .........................
... ................................................................... 9-27
9.13.3.1 Z-BUFFER MASKING ............................................................................................ 9-28
9.13.3.2 ACCUMULATOR INITIALIZATION ......................................................................... 9-29
9.13.4 The Inner Loop ........................................................................................................ 9-29
ix

TABLE OF CONTENTS
APPENDIX A
INSTRUCTION SET SUMMARY
APPENDIX B
INSTRUCTION FORMAT AND ENCODING
APPENDIX C
INSTRUCTION TIMINGS
APPENDIX D
INSTRUCTION CHARACTERISTICS
Figures
Figure Title Page
1-1 Registers and Data Paths ............................................................................... 1-2
2-1 Pixel Format Examples ................................................................................... 2-4
3-1 Register Set .................................................................................................... 3-1
3-2 Processor Status Register ............................................................................ ..
3-3 Extended Processor Status Register ............................................................. 3-5
3-4 Directory Base Register .................................................................................. 3-6
3-5 Floating-Point Status Register ........................................................................ 3-9
4-1 Memory Formats ............................................................................................. 4-1
4-2 Big and Little Endian Memory Transfers ........................................................ 4-2
4-3 Format of a Virtual Address ............................................................................ 4-3
4-4 Address Translation ........................................................................................ 4-4
4-5 Format of a Page Table Entry ........................................................................ 4-5
4-6 Invalid Page Table Entry ................................................................................ 4-5
6-1 Pipelined Instruction Execution ...................................................................... 6-3
6-2 Dual-Operation Data Paths ............................................................................. 6-16
6-3 Data Paths by Instruction (1 of 8) .................................................................. 6-18
6-4 Data Path Mnemonics .................................................................................... 6-26
6-5 PSR Fields for Graphics Operations .............................................................. 6-29
6-6 FADDP with 8-Bit Pixels .................................................................................. 6-33
6-7 FADDP with 16-Bit Pixels ................................................................................ 6-34
6-8 FADDP with 32-Bit Pixels ................................................................................ 6-35
6-9 FADDZ with 16-Bit Z-Buffer ............................................................................ 6-36
6-10 64-Bit Distance Interpolation .......................................................................... 6-37
6-11 Dual-Instruction Mode Transitions (1 of 2) ..................................................... 6-40
8-1 Register Allocation .......................................................................................... 8-2
8-2 Stack Frame Format ....................................................................................... 8-6
8-3 Example Memory Layout ................................................................................ 8-7
9-1 Z-Buffer Interpolation ...................................................................................... 9-23
9-2 faddz Operands ............................................................................................. 9-24
9-3 Pixel Interpolation for Gouraud Shading ........................................................ 9-27
9-4 faddp Operands ............................................................................................. 9-27
x

Table
2-1
2-2
3-1
3-2
3-3
3-4
4-1
5-1
6-1
6-2
6-3
7-1
7-2
8-1
9-1
9-2
9-3
A-1
A-2
B-1
Example
5-1
5-2
5-3
7-1
7-2
8-1
8-2
8-3
8-4
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
9-16
9-17
TABLE OF CONTENTS
Tables
Title Page
Pixel Formats .................................................................................................. 2-3
Single and Double
Real Encodings ........................................................... ~... 2-5
Values of
PS ................................................................................................... 3-4
Values of
RB ................................................................................................... 3-7
Values of
RC ................................................................................................ ... 3-8
Values of
RM ................................................................................................... 3-9
Combining Directory and Page Protection .................................................... 4-8
Control Register Encoding for Assemblers .................................................... 5-20
Precision Specification ................................................................................... 6-2
DPC Encoding ................................................................................................ 6-17
FADDP MERGE Update ................................................................................. 6-32
Types of Traps ................................................................................................
7-1
Register and Cache Values after Reset ......................................................... 7-9
Register Allocation ..........................................................................................
8-1
faddz Visualization .......................................................................................... 9-25
Accumulator Initial Values .............................................................................. 9-29
Accumulator Initialization Table ...................................................................... 9-30
Precision Specification ................................................................................ ... A-2
FADDP MERGE Update ................................................................................. A-5
Register Encoding ..........................................................................................
B-1
Examples
Title
Example of bla Usage ...................................................................................
Cache Flush Procedure ..................................................................................
Examples of lock and unlock Usage ..........................................................
..
Saving Pipeline States ....................................................................................
Restoring Pipeline States
(1 of 2) ..................................................................
Reading Misaligned 32-Bit Value ...................................................................
Subroutine Entry and Exit with Frame Pointer ...............................................
Subroutine Entry and Exit without Frame Pointer .........................................
Possible Implementation of alloca .................................................................
Sign Extension ................................................................................................
Loading Small Unsigned Integers ..................................................................
Single-Precision Divide ...................................................................................
Double-Precision Divide .................................................................................
Integer Multiply ...............................................................................................
Single to Double Conversion .........................................................................
Signed Integer Divide .....................................................................................
String Copy .....................................................................................................
Pipelined Add .................................................................................................
Pipelined Dual-Operation Instruction .............................................................
Pipelined Double-Precision Dual Operation ................................................. ..
Dual-Instruction Mode ....................................................................................
Matrix Multiply, Cached Loads Only (Sheet 1 of
2) .......................................
Matrix Multiply, Cached and Pipelined Loads (Sheet 1 of
2) ........................
Setting Pixel Size ............................................................................................
Register Assignments .....................................................................................
Construction of Z Interpolants ........................................................................
xi
Page
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5-22
5-24
7-12
7-13
8-4
8-6
8-7
8-8
9-1
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-10
9-12
9-14
9-16
9-19
9-21
9-22
9-26

TABLE OF CONTENTS
Examples
Example Title
9-18
9-19
9-20
9-21
Construction of Color Interpolants ............................................................... ..
Z Mask Procedure ..........................................................................................
Accumulator Initialization ................................................................................
3-D Rendering (1 of 2) ...................................................................................
xii
Page
9-28
9-28
9-30
9-31

Architectural Overview 1

CHAPTER 1
ARCHITECTURAL OVERVIEW
The Intel i860™ Microprocessor defines a complete architecture that balances integer,
floating point, and graphics performance. Target applications include engineering work-
stations, scientific computing, 3-D graphics workstations, and multiuser systems. Its par-
allel architecture achieves high throughput with
RISe design techniques, pipelined
processing units, wide data paths, and large on-chip caches.
1.1 OVERVIEW
The i860 microprocessor supports more than just integer operations. The architecture
includes on a single chip:
• . Integer operations
• Floating-point operations
• Graphics operations
• Memory-management support
• Data and instruction caches
Having a data cache as an integral part of the architecture provides support for vector
operations. The data cache supports applications programs
in the conventional manner,
without explicit programming. For vector operations, however, programmers can explic-
itly use the data cache as if it were a large block of vector registers.
To sustain high performance, the i860 microprocessor incorporates wide information
paths that include:
• 64-bit external data bus
• 128-bit on-chip data bus
• 64-bit on-chip instruction bus
Floating-point vector operations use all three busses.
The i860 microprocessor includes a RISe integer core processing unit with one-clock
instruction execution. The core unit processes conventional integer programs and pro-
vides complete support for standard operating systems, such
as UNIX and OS/2. The
core unit also drives the graphics and floating point hardware.
The i860 microprocessor supports vector floating-point operations without special vector
instructions or vector registers. It accomplishes this
by using the on-chip data cache and
a variety
of parallel techniques that include:
• Pipelined instruction execution with delayed branch instructions to avoid breaks in
the pipeline.
• Instructions that automatically increment index registers so as to reduce the number
of instructions needed for vector processing.
1-1

ARCHITECTURAL OVERVIEW
• Parallel integer core and floating-point processing units.
• Parallel multiplier and adder units within the floating-point unit.
• Pipelined floating-point hardware units, with both scalar (nonpipelined) and vector
(pipelined) variants of floating-point instructions. SqftWare can switch between scalar
and pipelined modes. '
:'
• Large register set:
32 general-purpose integer registers, each 32-bits wide.
32 floating-point registers, each 32-bits wide, which can also be configured as 64-
and 128-bit registers. The floating-point registers also serve as the staging area
for data going into and out of the floating-point pipelines.
Figure
1-1 illustrates the registers and data paths of the i860 microprocessor.
240329i
Figure 1-1. Registers and Data Paths
1-2