iWave iW-RainboW-G33D Installation manual

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i.MX8M SMARC Development Platform Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
iW-RainboW-G33D
i.MX8M Quad/QuadLite/Dual
SMARC Development Platform
Hardware User Guide

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i.MX8M SMARC Development Platform Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Document Revision History
Document Number
iW-PRFGD-UM-01-R1.0-REL1.0-Hardware-i.MX8M-DevKit
Revision
Date
Description
1.0
19th Mar 2019
Initial Release Version
PROPRIETARY NOTICE: This document contains proprietary material for the sole use of the intended recipient(s). Do
not read this document if you are not the intended recipient. Any review, use, distribution or disclosure by others is
strictly prohibited. If you are not the intended recipient (or authorized to receive for the recipient), you are hereby
notified that any disclosure, copying distribution or use of any of the information contained within this document is
STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.”

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i.MX8M SMARC Development Platform Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Disclaimer
iWave Systems reserves the right to change details in this publication including but not limited to any Product
specification without notice.
No warranty of accuracy is given concerning the contents of the information contained in this publication. To the
extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by iWave
Systems, its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or
inaccuracies in this document.
CPU and other major components used in this product may have several silicon errata associated with it. Under no
circumstances, iWave Systems shall be liable for the silicon errata and associated issues.
Trademarks
All registered trademarks, product names mentioned in this publication are the property of their respective owners
and used for identification purposes only.
Certification
iWave Systems Technologies Pvt. Ltd. is an ISO 9001:2015 Certified Company.
Warranty & RMA
Warranty support for Hardware: 1 Year from iWave or iWave's EMS partner.
For warranty terms, go through the below web link,
http://www.iwavesystems.com/support/warranty.html
For Return Merchandise Authorization (RMA), go through the below web link,
http://www.iwavesystems.com/support/rma.html
Technical Support
iWave Systems technical support team is committed to provide the best possible support for our customers so that
our Hardware and Software can be easily migrated and used.
For assistance, contact our Technical Support team at,
Email : [e-mail]
Website : www.iwavesystems.com
Address : iWave Systems Technologies Pvt. Ltd.
# 7/B, 29th Main, BTM Layout 2nd Stage,
Bangalore, Karnataka,
India –560076

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i.MX8M SMARC Development Platform Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Table of Contents
1. INTRODUCTION ............................................................................................................................................8
1.1 Purpose .............................................................................................................................................................8
1.2 Overview...........................................................................................................................................................8
1.3 List of Acronyms................................................................................................................................................ 8
1.4 Terminlogy Description...................................................................................................................................10
1.5 References ......................................................................................................................................................10
2. ARCHITECTURE AND DESIGN....................................................................................................................... 11
2.1 i.MX8M Q/QL/D SMARC Development Platform Block Diagram ................................................................... 11
2.2 i.MX8M Q/QL/D SMARC Development Platform Features.............................................................................12
2.3 SMARC MXM Connector.................................................................................................................................14
2.3.1 SMARC MXM Connector Pin Assignment....................................................................................................15
2.4 Serial Interface Features.................................................................................................................................31
2.4.1 Debug UART Port ........................................................................................................................................31
2.4.2 Data UART Header ......................................................................................................................................32
2.5 High Speed Interface Features........................................................................................................................ 33
2.5.1 PCIe Port......................................................................................................................................................33
2.5.2 USB3.0 OTG as Device/Host Port ................................................................................................................38
2.5.3 USB3.0 Host Port.........................................................................................................................................39
2.6 Communication Interface Features ................................................................................................................40
2.6.1 Dual Gigabit Ethernet Ports ........................................................................................................................40
2.6.2 USB2.0 Host Port.........................................................................................................................................41
2.6.3 SDIO Port.....................................................................................................................................................42
2.7 Audio & Video Features..................................................................................................................................43
2.7.1 Audio In/Out Ports ......................................................................................................................................43
2.7.2 MIPI DSI Display ..........................................................................................................................................44
2.7.3 HDMI/DP Port .............................................................................................................................................46
2.7.4 MIPI CSI Camera (Optional).........................................................................................................................47
2.8 Additional Features.........................................................................................................................................49
2.8.1 RTC Coin Cell Holder....................................................................................................................................49
2.8.2 SPI Flash (Optional) .....................................................................................................................................49
2.9 On Board Switches..........................................................................................................................................50
2.10 Audio & Video Expansion Connector..............................................................................................................52
2.11 SOM Expansion Connector .............................................................................................................................58
2.12 Carrier Expansion Connectors......................................................................................................................... 59
3. TECHNICAL SPECIFICATION.......................................................................................................................... 73
3.1 Power Input Requirement ..............................................................................................................................73
3.2 Power Output Specification............................................................................................................................74
3.3 Environmental Characteristics........................................................................................................................75
3.3.1 Environmental Specification........................................................................................................................75
3.3.2 RoHS Compliance ........................................................................................................................................75

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3.3.3 Electrostatic Discharge................................................................................................................................75
3.4 Mechanical Characteristics.............................................................................................................................76
3.4.1 i.MX8M Q/QL/D SMARC Carrier Board Mechanical Dimensions................................................................76
4. ORDERING INFORMATION .......................................................................................................................... 78

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List of Figures
Figure 1: i.MX8M Q/QL/D SMARC Development Platform Block Diagram.....................................................................11
Figure 2: SMARC MXM Connector..................................................................................................................................14
Figure 3: Debug UART .....................................................................................................................................................31
Figure 4: Data UART Header ...........................................................................................................................................32
Figure 5: PCIex4 Connector.............................................................................................................................................33
Figure 6: Mini PCIe Connector ........................................................................................................................................36
Figure 7: USB3.0 OTG Port..............................................................................................................................................38
Figure 8: USB3.0 Host Port..............................................................................................................................................39
Figure 9: Dual Stack RJ45 Magjack..................................................................................................................................40
Figure 10: USB2.0 Host Port............................................................................................................................................41
Figure 11: SDIO Port........................................................................................................................................................42
Figure 12: Audio In/Out Ports.........................................................................................................................................43
Figure 13: MIPI DSI Display Connector ...........................................................................................................................44
Figure 14: HDMI/DP Port ................................................................................................................................................46
Figure 15: MIPI Camera Connector.................................................................................................................................47
Figure 16: RTC Coin Cell Holder ......................................................................................................................................49
Figure 17: SMARC On Board Switches ............................................................................................................................50
Figure 18: Audio & Video Expansion Connector.............................................................................................................52
Figure 19: SMARC SOM Expansion Connector................................................................................................................58
Figure 20: SMARC Expansion Connector ........................................................................................................................59
Figure 21: Power Jack......................................................................................................................................................73
Figure 22: Mechanical dimension of i.MX8M Q/QL/D SMARC Carrier Board- Top View...............................................76
Figure 23: Mechanical dimension of i.MX8M Q/QL/D SMARC Carrier Board - Side View..............................................77

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List of Tables
Table 1: Acronyms & Abbreviations..................................................................................................................................8
Table 2: Terminology ......................................................................................................................................................10
Table 3: SMARC MXM Connector Pin Assignment..........................................................................................................15
Table 4: Data UART Header Pin Out................................................................................................................................32
Table 5: PCIex4 Connector Pin Out .................................................................................................................................34
Table 6: Mini-PCIe Connector Pin Out ............................................................................................................................36
Table 7: MIPI DSI Display Connector Pin Out..................................................................................................................45
Table 8: MIPI Camera Connector Pin Out .......................................................................................................................48
Table 9: Board Configuration Switch ..............................................................................................................................51
Table 10: Audio & Video Expansion Connector Pin Out .................................................................................................53
Table 11: Carrier Expansion Connector1 Pin Out............................................................................................................60
Table 12: Carrier Expansion Connector2 Pin Out............................................................................................................66
Table 13: Power Input Requirement...............................................................................................................................74
Table 14: Power Output Specification ............................................................................................................................74
Table 15: Environmental Specification ...........................................................................................................................75
Table 16: Orderable Product Part Numbers ...................................................................................................................78

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1. INTRODUCTION
1.1 Purpose
The iW-RainboW-G33D i.MX8M SMARC SOM development platform incorporates i.MX8M Quad/QuadLite/Dual
(Q/QL/D) CPU based SMARC SOM and generic SMARC Carrier board for complete validation of i.MX8M Q/QL/D CPU
functionality. This document is the hardware user guide for the i.MX8M SMARC carrier board. This guide provides
detailed information on the overall design and usage of the SMARC carrier board from a hardware systems
perspective. Complete information about the i.MX8M SMARC SOM hardware is explained in another document “iW-
RainboW-G33M-i.MX8M-SMARC-SOM-HardwareUserGuide”.
1.2 Overview
iW-RainboW-G33D-i.MX8M development Platform comes with i.MX8M Q/QL/D based SMARC SOM, SMARC V2.0
Generic Carrier board along with 5.5-inch Capacitive Touch Display. The development board can be used for quick
prototyping of various applications targeted by the i.MX8M Q/QL/D application processor. With the 120mmx120mm
Nano ITX formfactor, SMARC carrier board is highly packed with all the necessary on-board connectors to validate the
features of i i.MX8M Q/QL/D SMARC SOM.
1.3 List of Acronyms
The following acronyms will be used throughout this document.
Table 1: Acronyms & Abbreviations
Acronyms
Abbreviations
ARM
Advanced RISC Machine
CMOS
Complementary Metal-Oxide Semiconductor
CPU
Central Processing Unit
CSI
Camera Serial Interface
DSI
Display Serial Interface
eMMC
Enhanced Multi Media Card
GB
Giga Byte
Gbps
Gigabits per sec
GPIO
General Purpose Input Output
Hz
Hertz
I2C
Inter-Integrated Circuit
I2S
Inter-IC Sound Bu
IC
Integrated Circuit
MIPI
Mobile Industry Processor Interface
PCB
Printed Circuit Board
RoHS
Restriction of Hazardous Substances

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Acronyms
Abbreviations
RTC
Real Time Clock
SD
Secure Digital
SMARC SOM
Smart Mobility ARChitecture
TBD
To Be Defined
UART
Universal Asynchronous Receiver/Transmitter
USB
Universal Serial Bus
USB OTG
USB On The Go
V
Voltage

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1.4 Terminlogy Description
In this document, wherever Signal Type is mentioned, below terminology is used.
Table 2: Terminology
Terminology
Description
I
Input Signal
O
Output Signal
IO
Bidirectional Input/output Signal
CMOS
Complementary Metal Oxide Semiconductor Signal
DIFF
Differential Signal
LVDS
Low Voltage Differential Signal
GBE
Gigabit Ethernet Media Dependent Interface differential pair signals
USB HS
Universal Serial Bus High Speed differential pair signals
USB SS
Universal Serial Bus Super Speed differential pair signals
MIPI
Mobile Industry Processor Interface signals
TMDS
Transition Minimized Differential Signaling
OD
Open Drain Signal
OC
Open Collector Signal
Power
Power Pin
PU
Pull Up
PD
Pull Down
NA
Not Applicable
NC
Not Connected
Note: Signal Type does not include internal pull-ups or pull-downs implemented by the chip vendors and only includes
the pull-ups or pull-downs implemented On-SMARC SOM.
1.5 References
•IMX8MDQLQRM.pdf
•SMARC Specification V2.0

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2. ARCHITECTURE AND DESIGN
This section provides detailed information about the i.MX8M Q/QL/D SMARC SOM development platform carrier
board features with high level block diagram and detailed information about each block.
2.1 i.MX8M Q/QL/D SMARC Development Platform Block Diagram
iW-RainboW-G33D-i.MX8M SMARC SOM Development Kit Block Diagram
80 pin
Carrier
Expansion
Connector-2
RJ45 Stack
i.MX8M SMARC Edge Connector
MIPI DSI0,
I2C4
MIPI DSI X 1 (4 lane)
HDMI ¹
MIPI DSI0
Connector
HDMI Out
Connector
MIPI CSI0 MIPI CSI0
Connector
HDMI x 1
CSI0 lane[1:0]
ENET to GBE0
Bottom
Top
10/100/100Mbps Ethernet
USB2.0 Host x 1
PCIe x 4 Slot
PCIe1
PCIe x 1
PCIe2
(Optional)
PCIe x 1
100Pin SOM Expansion Connector
(Optional)
QSPI_B ² QSPI x 1
UART (with CTS & RTS) x 1
UART3 UART x 1
UART (with CTS & RTS) x 1
I2C2, I2C3 I2C x 2
DIP Switch
(4bit X 3)
BOOT_SEL
BOOT_SEL x 3
To On-board
Peripherals
& SOM
12V Power Jack
On-Board
Regulators
12V
RTC Coin cell
Holder
VDD_RTC 3V
USB2.0
2Port Hub
Mini PCIe
Connector
USB2.0 Stack
USB2_HUBP3
(HS)
Bottom
Top
USB2.0 Host x 1
USB2_HUBP1
(HS)
PCIe Switch
CONTROL
CTRL _SIG x 9
80 pin
A&V
Expansion
Connector
MIPI CSI1 MIPI CSI X1 (4lane)
AUD_SAI3 ³ I2S x 1
I2C1, I2C4,
GPIOs
I2Cx 2, GPIOs
M.2 Module
Connector
SEL DIP SW
CSI0 lane[3:2]
80 pin
Carrier
Expansion
Connector-1
UART1
Debug Port
(Micro USB)
USB to UART
Transceiver
UART
USB
CSI0 lane[3:2]
PCIe2 to GBE1
MIPI CSI0
10/100/100Mbps Ethernet
DP ¹ Display Port
Connector
DP x 1
Note:
¹ Either HDMI or DP can be supported on SOM. By default, HDMI is supported.
² Same interface signals shared between M.2 Connector and Expansion Connector2
³ Same interface signals shared between M.2 Connector and A&V Expansion Connector
QSPI_B ²
AUD_SAI3 ³
SAI1 x 1
USB2_HUBP4
(HS)
USB2.0 Host x 1
UART4
(Optional)
I2S x 1
QSPI x 1
SAI1
UART2
UART
Header
eCSPI3
(Optional)
SPI Flash–2MB
(Optional)
SPI x 1
SPI x 1
USB3.0
Switch
USB Type-C
Connector
USB3.0 Stack
Bottom
Top
USB3.0 Host x 1
USB3.0 Host x 1
DIP SW
USB1
(SS &HS)
USB2,
USB2_HUBP2
(SS & HS)
SAI2 I2S
Audio Codec
Audio In/Out
Jack
I2S Audio In/Out
uSDHC2 Standard SD
Connector
SDIO x 1
Figure 1: i.MX8M Q/QL/D SMARC Development Platform Block Diagram

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2.2 i.MX8M Q/QL/D SMARC Development Platform Features
The i.MX8M Q/QL/D SMARC carrier board supports the following features to validate the NXP’s i.MX8M Q/QL/D
SMARC SOM Edge connector interfaces.
Serial Interface Features
•Debug UART through USB Micro AB Connector
•Data UART x 1 Port through Header
High Speed Interface Features
•PCIe x 1 Port through x4 connector or Mini-PCIe connector
•USB 3.0 OTG as Device/Host x 1 Port through Type-C Connector (or Type A connector)
•USB 3.0 Host x 1 Port through USB 3.0 Type A Connector
Communication Features
•Dual 10/100/1000Mbps Ethernet through dual stack RJ45MagJack
•USB 2.0 Host x 2 Ports through USB 2.0 dual stack USB Type A Connector
•SDHI (4bit) x 1 Port through Standard SD Connector
•M.2 connector with USB, QSPI, UART & I2S interfaces
Audio & Video Features
•5.5inch Full HD AMOLED MIPI DSI display with Capacitive Touch
•HDMI/Display Port through HDMI Connector/DP Connector
•I2S Audio codec with 3.5mm headphone In/Out Jack
•MIPI CSI 2lane/4lane Camera Connector
Additional Features
•RTC Coin Cell holder
•SPI Flash 2MB (Optional)
On Board Switches
•Reset push button
•Power ON/OFF push button
•Board Configuration DIP Switch
•Boot Selection DIP Switch

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A&V Expansion Connector
•MIPI CSI - 4 lanes x 1 Port
•MIPI DSI - 4 lanes x 1 Port
•I2S x 1 Port
•I2C x 2 Ports
Carrier board Expansion Connectors
•SPI x 1 Port (Optional - Shared with SPI Flash)
•QSPI x 1 Port (Shared with M.2 connector)
•UART x 1 Port
•I2C x 2 Ports
•SAI x 1 Port
•GPIOs
General Specification
•Power Supply : 12V, 2A Power Input Jack
•Temperature Supported: 0°C to +60°C
•Form Factor : 120mm X 120mm Nano ITX

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2.3 SMARC MXM Connector
The i.MX8M Q/QL/D SMARC carrier board supports 314Pin SMARC MXM Edge mating connector for SMARC SOM
attachment. This standard 314-pin robust connector is capable of handling high-speed serialized signals and can be
used for size constrained embedded applications. This SMARC MXM Edge mating connector (J16) is physically located
at the top of the board as shown below.
Figure 2: SMARC MXM Connector

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2.3.1 SMARC MXM Connector Pin Assignment
Table 3: SMARC MXM Connector Pin Assignment
Pin
No.
SMARC MXM
Connector Pin
Name
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
SMARC Primary Side
P1
SMB_ALERT_1V8#
GPIO_SMB_ALERT(
GPIO1_00)
GPIO1_IO00/
T6
I, 1.8V CMOS
SM Bus Alert# (interrupt)
signal through GPIO.
P2
GND
GND
NA
Power
Ground.
P3
CSI1_CK+
MIPI_CSI2_CLK_P
MIPI_CSI2_CLK_P/
B19
O, MIPI
MIPI CSI2 differential clock
positive.
P4
CSI1_CK-
MIPI_CSI2_CLK_N
MIPI_CSI2_CLK_N/
A19
O, MIPI
MIPI CSI2 differential clock
negative.
P5
GBE1_SDP
NC
NA
NA
NC.
P6
GBE0_SDP
NC
NA
NA
NC.
P7
CSI1_RX0+
MIPI_CSI2_DATA0_
P
MIPI_CSI2_D0_P/
D20
O, MIPI
MIPI CSI2 differential data
lane 0 positive.
P8
CSI1_RX0-
MIPI_CSI2_DATA0_
N
MIPI_CSI2_D0_N/
C20
O, MIPI
MIPI CSI2 differential data
lane 0 negative.
P9
GND
GND
NA
Power
Ground.
P10
CSI1_RX1+
MIPI_CSI2_DATA1_
P
MIPI_CSI2_D1_P/
B20
O, MIPI
MIPI CSI2 differential data
lane 1 positive.
P11
CSI1_RX1-
MIPI_CSI2_DATA1_
N
MIPI_CSI2_D1_N/
A20
O, MIPI
MIPI CSI2 differential data
lane 1 negative.
P12
GND
GND
NA
Power
Ground.
P13
CSI1_RX2+
MIPI_CSI2_DATA2_
P
MIPI_CSI2_D2_P/
B21
O, MIPI
MIPI CSI2 differential data
lane 2 positive.
P14
CSI1_RX2-
MIPI_CSI2_DATA2_
N
MIPI_CSI2_D2_N/
A21
O, MIPI
MIPI CSI2 differential data
lane 2 negative.
P15
GND
GND
NA
Power
Ground.
P16
CSI1_RX3+
MIPI_CSI2_DATA3_
P
MIPI_CSI2_D3_P/
D19
O, MIPI
MIPI CSI2 differential data
lane 3 positive.
P17
CSI1_RX3-
MIPI_CSI2_DATA3_
N
MIPI_CSI2_D3_N/
C19
O, MIPI
MIPI CSI2 differential data
lane 3 negative.
P18
GND
GND
NA
Power
Ground.
P19
GBE0_MDI3-
GBE0_MDI3-
NA
IO, GBE
Gigabit Ethernet0 MDI
differential pair 3 negative
to top port of Dual Magjack.
P20
GBE0_MDI3+
GBE0_MDI3+
NA
IO, GBE
Gigabit Ethernet0 MDI
differential pair 3 positive
to top port of Dual Magjack.

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Pin
No.
SMARC MXM
Connector Pin
Name
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
P21
GBE0_LINK100#
GBE0_LINK100#
NA
I, 3.3V CMOS
Ethernet0 100Mbps link
status LED signal to top port
of Dual Magjack.
P22
GBE0_LINK1000#
GBE0_LINK1000#
NA
I, 3.3V CMOS
Gigabit Ethernet0 link
status LED signal.
P23
GBE0_MDI2-
GBE0_MDI2-
NA
IO, GBE
Gigabit Ethernet0 MDI
differential pair 2 negative
to top port of Dual Magjack.
P24
GBE0_MDI2+
GBE0_MDI2+
NA
IO, GBE
Gigabit Ethernet0 MDI
differential pair 2 positive
to top port of Dual Magjack.
P25
GBE0_LINK_ACT#
GBE0_LINK_ACT#
NA
I, 3.3V CMOS
Gigabit Ethernet0 activity
status LED signal to top port
of Dual Magjack.
P26
GBE0_MDI1-
GBE0_MDI1-
NA
IO, GBE
Gigabit Ethernet0 MDI
differential pair 1 negative
to top port of Dual Magjack.
P27
GBE0_MDI1+
GBE0_MDI1+
NA
IO, GBE
Gigabit Ethernet0 MDI
differential pair 1 positive
to top port of Dual Magjack.
P28
GBE0_CTREF
VPHY0_DVDDL
NA
I, 3.3V Power
CTREF Power for Ethernet0
to Centre Tap of top port of
Dual Magjack.
P29
GBE0_MDI0-
GBE0_MDI0-
NA
IO, GBE
Gigabit Ethernet0 MDI
differential pair 0 negative
to top port of Dual Magjack.
P30
GBE0_MDI0+
GBE0_MDI0+
NA
IO, GBE
Gigabit Ethernet0 MDI
differential pair 0 positive
to top port of Dual Magjack.
P31
SPI0_CS1#
NC
NA
-
NC.
P32
GND
GND
NA
Power
Ground.
P33
SDIO_WP
SDIO_WP
SD2_WP/M21
O, 3.3V CMOS
SD Write Protect to
Standard SD connector.
P34
SDIO_CMD
SMARC_SD_CMD
SD2_CMD/M22
IO, 1.8/3.3V
CMOS
SD Command to Standard
SD connector.
P35
SDIO_CD#
SDIO_CD#
SD2_CD_B/L21
O, 3.3V/CMOS
SD Card Detect to Standard
SD connector.
P36
SDIO_CK
SMARC_SD_CLK
SD2_CLK/L22
I, 1.8/3.3V
CMOS
SD Clock to Standard SD
connector.
P37
SDIO_PWR_EN
SDIO_PWR_EN
SD2_RESET_B/R22
I, 3.3VCMOS
SD Power enable.
P38
GND
GND
NA
Power
Ground.

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Pin
No.
SMARC MXM
Connector Pin
Name
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
P39
SDIO_D0
SMARC_SD_DATA0
SD2_DATA0/N22
IO, 1.8/3.3V
CMOS
SD Data0to Standard SD
connector.
P40
SDIO_D1
SMARC_SD_DATA1
SD2_DATA1/N21
IO, 1.8/3.3V
CMOS
SD Data1to Standard SD
connector.
P41
SDIO_D2
SMARC_SD_DATA2
SD2_DATA2/P22
IO, 1.8/3.3V
CMOS
SD Data2to Standard SD
connector.
P42
SDIO_D3
SMARC_SD_DATA3
SD2_DATA3/P21
IO, 1.8/3.3V
CMOS
SD Data3to Standard SD
connector.
P43
SPI0_CS0#
SM_ECSPI1_SS0
ECSPI1_SS0/D4
I, 1.8V CMOS
eCSPI1 Chip Select 0.
P44
SPI0_CK
SM_ECSPI1_SCLK
ECSPI1_SCLK/D5
I, 1.8V CMOS
eCSPI1 Clock.
P45
SPI0_DIN
SM_ECSPI1_MISO
ECSPI1_MISO/B4
O, 1.8V CMOS
eCSPI1 Master In Slave Out.
P46
SPI0_DO
SM_ECSPI1_MOSI
ECSPI1_MOSI/A4
I, 1.8V CMOS
eCSPI1 Master Out Slave In.
P47
GND
GND
NA
Power
Ground.
P48
SATA_TX+
NC
NA
-
NC.
P49
SATA_TX-
NC
NA
-
NC.
P50
GND
GND
NA
Power
Ground.
P51
SATA_RX+
NC
NA
-
NC.
P52
SATA_RX-
NC
NA
-
NC.
P53
GND
GND
NA
Power
Ground.
P54
ESPI_CS0#
QSPI_B_SS0_B
NANAD_CE2_B/F21
I, 1.8V CMOS
QSPIB Chip Select 0.
P55
ESPI_CS1#
QSPI_B_SS1_B
NANAD_CE3_B/H20
I, 1.8V CMOS
QSPIB Chip Select 1.
P56
ESPI_CK
QSPI_B_CLK
NAND_CLE/H21
I, 1.8V CMOS
QSPIB Clock.
P57
ESPI_IO_0
QSPI_B_DATA0
NAND_DATA04/L20
IO, 1.8V CMOS
QSPIB DATA 0.
P58
ESPI_IO_1
QSPI_B_DATA1
NAND_DATA05/J22
IO, 1.8V CMOS
QSPIB DATA 1.
P59
GND
GND
NA
Power
Ground.
P60
USB0+
USB0_DP
USB1_DP/A14
IO, USB HS
USB Port0 Data Positive to
USB2.0 OTG connector
(J21). This is optional
feature in SOM.
P61
USB0-
USB0_DM
USB1_DN/B14
IO, USB HS
USB Port0 Data Negative to
USB2.0 OTG connector
(J21). This is optional
feature in SOM.
P62
USB0_EN_OC#
USB0_EN_OC
SAI5_RXFS/N4
IO, 3.3V CMOS
USB Port0 Power Enable/
Over Current Indicator.
P63
USB0_VBUS_DET
VBUS_OTG
NA
O, 5V Power
USB Port0 OTG VBUS
detection. This is optional
feature in SOM.
P64
USB0_OTG_ID
USB0_OTG_ID
USB1_ID/C14
O, 3.3V CMOS
USB Port0 OTG ID. This is
optional feature in SOM.

REL1.0
Page 18 of 80
i.MX8M SMARC Development Platform Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Pin
No.
SMARC MXM
Connector Pin
Name
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
P65
USB1+
USB_HUB1OUT_DP
NA
IO, USB HS
USB Port2 HUB OUT1 Data
Positive to 2 Port USB HUB.
P66
USB1-
USB_HUB1OUT_D
M
NA
IO, USB HS
USB Port2 HUB OUT1 Data
Negative to 2 Port USB HUB.
P67
USB1_EN_OC#
USB_HUB1_OC
NA
O, 3.3V CMOS
USB1 Port2 HUB OUT1 Over
Current Indicator.
P68
GND
GND
NA
Power
Ground.
P69
USB2+
USB_HUB2OUT_DP
NA
IO, USB HS
USB Port2 HUB OUT2 Data
Positive to bottom Port of
USB2.0 TypeA connector.
P70
USB2-
USB_HUB2OUT_D
M
NA
IO, USB HS
USB Port2 HUB OUT2 Data
Negative to bottom Port of
USB2.0 TypeA connector.
P71
USB2_EN_OC#
USB2_EN_OC
GPIO1_IO05/P7
O, 3.3V CMOS
USB Port2 HUB OUT2 Over
Current Indicator.
P72
RSVD4
NC
NA
-
NC.
P73
RSVD5
NC
NA
-
NC.
P74
USB3_EN_OC#
USB3_EN_OC
SAI5_RXFS/N4
O, 3.3V CMOS
USB Port1 Over Current
Indicator.
KEY
P75
PCIE_A_RST#
PCIE_RST_3V3(GPI
O5_4)
SPDIF_RX/G6
I, 3.3V CMOS
PCIe Reset.
P76
USB4_EN_OC#
USB_HUB3_OC
NA
O, 3.3V CMOS
USB Port2 HUB OUT3 Over
Current Indicator.
P77
RSVD6
NC
NA
-
NC.
P78
RSVD7
NC
NA
-
NC.
P79
GND
GND
NA
Power
Ground.
P80
PCIE_C_REFCK+
NC
NA
-
NC.
P81
PCIE_C_REFCK-
NC
NA
-
NC.
P82
GND
GND
NA
Power
Ground.
P83
PCIE_A_REFCK+
PCIE1_REFCLK_P
NA
I, PCIe
PCIe1 Reference Clock
Positive.
P84
PCIE_A_REFCK-
PCIE1_REFCLK_N
NA
I, PCIe
PCIe1 Reference Clock
Negative.
P85
GND
GND
NA
Power
Ground.
P86
PCIE_A_RX+
PCIE1_RXP
PCIE1_RXN_P/H25
O, PCIe
PCIe1 Receive Positive.
P87
PCIE_A_RX-
PCIE1_RXN
PCIE1_RXN_N/H24
O, PCIe
PCIe1 Receive Negative.
P88
GND
GND
NA
Power
Ground.
P89
PCIE_A_TX+
PCIE1_TXP
PCIE1_TXN_P/J25
I, PCIe
PCIe1 Transmit Positive.
P90
PCIE_A_TX-
PCIE1_TXN
PCIE1_TXN_N/J24
I, PCIe
PCIe1 Transmit Negative.
P91
GND
GND
NA
Power
Ground.

REL1.0
Page 19 of 80
i.MX8M SMARC Development Platform Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Pin
No.
SMARC MXM
Connector Pin
Name
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
P92
HDMI_D2+/
DP1_LANE0+
HDMI_TX_DATA2_
P
HDMI_TX_P_LN_2/
N2
I, TMDS
HDMI Transceiver 2 Positive
to HDMI Connector.
P93
HDMI_D2-/
DP1_LANE0-
HDMI_TX_DATA2_
N
HDMI_TX_M_LN_2/
N1
I, TMDS
HDMI Transceiver 2
Negative to HDMI
Connector.
P94
GND
GND
NA
Power
Ground.
P95
HDMI_D1+/
DP1_LANE1+
HDMI_TX_DATA1_
P
HDMI_TX_P_LN_1/
U2
I, TMDS
HDMI Transceiver 1 Positive
to HDMI Connector.
P96
HDMI_D1-/
DP1_LANE1-
HDMI_TX_DATA1_
N
HDMI_TX_M_LN_1/
U1
I, TMDS
HDMI Transceiver 1
Negative to HDMI
Connector.
P97
GND
GND
NA
Power
Ground.
P98
HDMI_D0+/
DP1_LANE2+
HDMI_TX_DATA0_
P
HDMI_TX_P_LN_0/
T1
I, TMDS
HDMI Transceiver 0 Positive
to HDMI Connector.
P99
HDMI_D0-/
DP1_LANE2-
HDMI_TX_DATA0_
N
HDMI_TX_M_LN_0/
T2
I, TMDS
HDMI Transceiver 0
Negative to HDMI
Connector.
P100
GND
GND
NA
Power
Ground.
P101
HDMI_CK+/
DP1_LANE3+
HDMI_CLK_P
HDMI_TX_P_LN_3/
M1
I, TMDS
HDMI Transceiver CLK
Positive to HDMI
Connector.
P102
HDMI_CK-/
DP1_LANE3-
HDMI_CLK_N
HDMI_TX_M_LN_3/
M2
I, TMDS
HDMI Transceiver CLK
Negative to HDMI
Connector.
P103
GND
GND
NA
Power
Ground.
P104
HDMI_HPD/
DP1_HPD
HDMI_HPD
HDMI_HPD/W2
O, 1.8V CMOS
HDMI Hot Plug Detect from
HDMI Connector.
P105
HDMI_CTRL_CK/
DP1_AUX+
HDMI_CTRL_SCL
HDMI_DDC_SCL/R3
I, 1.8V CMOS
HDMI DDC Clock to HDMI
Connector through Voltage
Level translator.
P106
HDMI_CTRL_DAT/
DP1_AUX-
HDMI_CTRL_SDA
HDMI_DDC_SDA/P3
IO, 1.8V CMOS
HDMI DDC DATA to HDMI
Connector through Voltage
Level translator.
P107
DP1_AUX_SEL
NC
NA
-
NC.
P108
GPIO0/
CAM0_PWR#
SMARC_GPIO_0(GP
IO3_16)
GPIO3_16(NAND_RE
ADY_B)/K20
IO, 1.8V CMOS
General Purpose Input/
Output 0. Connected to
CAN0 Power Down.
P109
GPIO1/
CAM1_PWR#
SMARC_GPIO_1(GP
IO1_12)
GPIO1_IO12/L7
IO, 1.8V CMOS
General Purpose Input/
Output 1. Connected to
CAN1 Transceiver Power
Down.

REL1.0
Page 20 of 80
i.MX8M SMARC Development Platform Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
Pin
No.
SMARC MXM
Connector Pin
Name
Signal Name
CPU Ball Name/
Pin Number
Signal Type/
Termination
Description
P110
GPIO2/
CAM0_RST#
SMARC_GPIO_2(GP
IO1_15)
GPIO1_IO15/J6
IO, 1.8V CMOS
General Purpose Input/
Output 2. Used for Camera
RESET.
P111
GPIO3/
CAM1_RST#
SMARC_GPIO_3(GP
IO1_11)
GPIO1_IO11/L6
IO, 1.8V CMOS
General Purpose Input/
Output 3. Connected to
A&V Expansion connector.
P112
GPIO4/HDA_RST#
SMARC_GPIO_4(GP
IO1_10)
GPIO1_IO10/M7
IO, 1.8V CMOS
General Purpose Input/
Output 4. USB Type C Port
selection.
P113
GPIO5/PWM_OU
T
SMARC_GPIO_5(GP
IO1_01)
GPIO1_IO01/T7
IO, 1.8V CMOS
General Purpose Input/
Output 5. Connected to
HDMI_CEC#.
P114
GPIO6/TACHIN
SMARC_GPIO_6(GP
IO1_09)
GPIO1_IO09/M6
IO, 1.8V CMOS
General Purpose Input/
Output 6. Connected to USB
Type C Controller interrupt.
P115
GPIO7
SMARC_GPIO_7(GP
IO1_06)
GPIO1_IO06/N5
IO, 1.8V CMOS
General Purpose Input/
Output 7. Connected to
Touch interrupt.
P116
GPIO8
SMARC_GPIO_8(GP
IO1_08)
GPIO1_IO08/N7
IO, 1.8V CMOS
General Purpose Input/
Output 8. Connected to
Headphone Detect.
P117
GPIO9
SMARC_GPIO_9(GP
IO1_03)
GPIO1_IO03/P4
IO, 1.8V CMOS
General Purpose Input/
Output 9. Connected to
MIPI Display RESET.
P118
GPIO10
SMARC_GPIO_10(G
PIO1_07)
GPIO1_IO07/N6
IO, 1.8V CMOS
General Purpose Input/
Output 10. Connected to
PCIe connector for Wireless
disable (active low).
P119
GPIO11
SMARC_GPIO_11(G
PIO1_04)
GPIO1_IO04/P5
IO, 1.8V CMOS
General Purpose Input/
Output 11. Connected to
MIC Detect.
P120
GND
GND
NA
Power
Ground.
P121
I2C_PM_CK
I2C1_SCL
I2C1_SCL/E7
I, 1.8V CMOS
I2C1 Clock.
P122
I2C_PM_DAT
I2C1_SDA
I2C1_SDA/E8
IO, 1.8V CMOS
I2C1 Data.
P123
BOOT_SEL0#
BOOT_SEL0#
NA
O, 1.8V CMOS
Boot Media Select bit 0
from 4bit DIP Switch (SW5).
P124
BOOT_SEL1#
BOOT_SEL1#
NA
O, 1.8V CMOS
Boot Media Select bit 1
from 4bit DIP Switch (SW5).
P125
BOOT_SEL2#
BOOT_SEL2#
NA
O, 1.8V CMOS
Boot Media Select bit 2
from 4bit DIP Switch (SW5).