Lattice iCE40 Ultra User manual

iCE40 Ultra Breakout Board
Evaluation Board User Guide
FPGA-EB-02034-1.2
July 2020

iCE40 Ultra Breakout Board
Evaluation Board User Guide
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-EB-02034-1.2
Disclaimers
Lattice makes no warranty, representation, or guarantee regarding the accuracy of information contained in this document or the suitability of its
products for any particular purpose. All information herein is provided AS IS and with all faults, and all risk associated with such information is
entirely with Buyer. Buyer shall not rely on any data and performance specifications or parameters provided herein. Products sold by Lattice have
been subject to limited testing and it is the Buyer's responsibility to independently determine the suitability of any products and to test and verify the
same. No Lattice products should be used in conjunction with mission- or safety-critical or any other application in which the failure of Lattice’s
product could create a situation where personal injury, death, severe property or environmental damage may occur. The information provided in this
document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any
products at any time without notice.

iCE40 Ultra Breakout Board
Evaluation Board User Guide
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02034-1.2 3
Contents
Acronyms in This Document.................................................................................................................................................5
1. Introduction..................................................................................................................................................................6
2. Features........................................................................................................................................................................6
3. iCE40 Ultra Device ........................................................................................................................................................8
4. Software Requirements................................................................................................................................................8
5. Demonstration Design Shunts......................................................................................................................................8
6. Clock Sources................................................................................................................................................................9
7. Board Power.................................................................................................................................................................9
8. Board Configuration and Programming......................................................................................................................10
9. Test Points ..................................................................................................................................................................11
10. RGB LED Demonstration Design and User Interface...............................................................................................13
11. User Interface Serial Communication Interface .....................................................................................................15
11.1. LED Control through SPI....................................................................................................................................15
11.2. SPI Protocol.......................................................................................................................................................15
11.3. Register Definitions...........................................................................................................................................15
12. Ordering Information..............................................................................................................................................18
TechnicalSupport Assistance ..............................................................................................................................................19
Appendix A. Schematic Diagrams.......................................................................................................................................20
Appendix B. Bill of Materials...............................................................................................................................................26
RevisionHistory...................................................................................................................................................................29

iCE40 Ultra Breakout Board
Evaluation Board User Guide
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-EB-02034-1.2
Figures
Figure 2.1. Top Side of the iCE40 Ultra Breakout Board.......................................................................................................7
Figure 5.1. Default Shunt Locations......................................................................................................................................8
Figure 8.1. Configuration and Programming Details ..........................................................................................................10
Figure 9.1. J6 Header A Breakouts......................................................................................................................................11
Figure 9.2. J7 Header B Breakouts......................................................................................................................................11
Figure 9.3. J5 PMOD Connector..........................................................................................................................................11
Figure 9.4. J7 Header B Breakouts......................................................................................................................................12
Figure 9.5. Breakout Headers .............................................................................................................................................12
Figure 10.1. SPI Flash Selection for J10 (Vertical)...............................................................................................................13
Figure 10.2. iCE40 Ultra Selection for J10 (Horizontal).......................................................................................................13
Figure 10.3. iCE40 Ultra LED Demonstration Interface.......................................................................................................14
Figure 11.1. SPI Physical Transaction..................................................................................................................................15
Figure A.1. Block Diagram...................................................................................................................................................20
Figure A.2. FTDI Connection ...............................................................................................................................................21
Figure A.3. DUT Connection................................................................................................................................................22
Figure A.4. LEDs and Headers.............................................................................................................................................23
Figure A.5. Regulator Connection.......................................................................................................................................24
Figure A.6. SPI.....................................................................................................................................................................25
Tables
Table 11.1. ADDR [7:0]........................................................................................................................................................15
Table 11.2. REG [15:0] ........................................................................................................................................................15
Table 11.3. RGB Color [3:0].................................................................................................................................................15
Table 11.4. Brightness [3:0] ................................................................................................................................................16
Table 11.5. Breathe Ramp [3:0]..........................................................................................................................................16
Table 11.6. Blink Rate [3:0].................................................................................................................................................17
Table 12.1. Ordering Information.......................................................................................................................................18

iCE40 Ultra Breakout Board
Evaluation Board User Guide
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02034-1.2 5
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
ESD
Electro Static Discharge
FPGA
Field-Programmable Gate Array
FTDI
Future Technology Devices International
I/O
Input/Output
LED
Light Emitting Diode
NVCM
Non Volatile Configuration Memory
PWM
Pulse-Width Modulation
SPI
Serial Peripheral Interface
WLSCP
Wafer Level Chip Scale Packaging

iCE40 Ultra Breakout Board
Evaluation Board User Guide
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-EB-02034-1.2
1. Introduction
This guide describes how to begin using the iCE40 Ultra™Breakout Board, an easy-to-use platform for demonstrating
the high-current LED drive capabilities of the iCE40 Ultra FPGA. Along with the evaluation board and accessories, this
kit includes the pre-loaded LED Driver Demo that demonstrates driving the RGB LEDs with a PWM circuit. In addition,
most of the device's I/O balls are accessible through one of the several header locations on the board, facilitating rapid
prototyping of user functions.
The contents of this user guide include demo operation, top-level functional descriptions of the various portions of the
evaluation board, descriptions of the onboard connectors, shunts, a complete set of schematics, and the bill of
materials for the iCE40 Ultra Breakout Board.
Note: Static electricity can severely shorten the lifespan of electronic components. Be careful when handling the iCE40
Ultra Breakout Board as to not damage it from ESD.
2. Features
The iCE40 Ultra Breakout Board includes:
iCE40HX-8K Evaluation Board –The iCE40 Ultra Breakout Board features the following onboard components and
circuits:
iCE40 Ultra (iCE5LP4K-SWG36) device in a 36-ball WLCSP package
Example of a board using this 0.35-pitch WLCSP package
High-current LED output
Infrared transmit
iCE40 Ultra Current Measurements
Standard USB cable for device programming
RoHS-compliant packaging and process
Pre-loaded Demo –The kit includes a pre-loaded demo to control the onboard RGB LED in conjunction with a
software run user interface.
USB Connector Cable –A mini B USB port provides power, a programming interface and communication for the
software RGB LED user interface to the iCE40 Ultra SPI port.
Figure 2.1 shows the top side of the iCE40 Ultra Breakout Board indicating the specific features that are designed on
the board.

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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02034-1.2 7
USB Interface
Socket
iCE5LP4K-SWG36
Torch
LED
IR LEDRGB
LED
D3
Power LED
Figure 2.1. Top Side of the iCE40 Ultra Breakout Board

iCE40 Ultra Breakout Board
Evaluation Board User Guide
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8 FPGA-EB-02034-1.2
3. iCE40 Ultra Device
The board features an iCE5LP4K FPGA with a 1.2 V core supply. The device is packaged in a 36-ball WLCSP. For a
complete description of this device, refer to iCE40 Ultra Family Data Sheet (FPGA-DS-02028).
4. Software Requirements
You should install the following software before you begin developing designs for the board:
Lattice iCEcube2 2014.04 (or higher)
Diamond Programmer 3.2 (or higher)
These software are available at the Lattice website Design Software and IP page. Make sure you log in to
www.latticesemi.com. Otherwise, these software downloads are not visible. It is also recommended to download the
RGB LED software user interface which interfaces with the iCE40 Ultra Breakout Board. This user interface allows you to
control the RGB LED for color, brightness, blinking, and breathing. Download the PC or MAC version of the user
interface at www.latticesemi.com.
5. Demonstration Design Shunts
Lattice provides the RGB LED Driver Demo design programmed in the board. The RGB LED Driver Demo used in
conjunction with the software user interface illustrates the use of a PWM driver controlling the LEDs on the board.
Below is a description of the control jumpers for each LED.
The RGB LED transition colors
J4 can be used to probe RGB LED (default shunted). If you remove J4, the RGB LED does not light up.
The IR LED is controlled when a shunt is placed across J50 pins 1-2.
The Bar Code LED is controlled when a shunt is placed across J29 pins 2-3 (default shunted).
Figure 5.1 shows the default board shunt locations.
J3 - Enable DONE LED
J9 – Isolate
SPI Flash CSn
J50 – Selects-
HP LED device
(IR or Torch)
J51 – Enable-
12 MHz clock
J4 – -RGB
Shunts
J10 – Program
SPI Flash or iCE5LP
Figure 5.1. Default Shunt Locations

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© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02034-1.2 9
6. Clock Sources
The board has a single 12 MHz clock source. The 12 MHz clock drives both the FTDI USB interface device and the
iCE5LP4K device. The iCE5LP4K can be disconnected from the 12 MHz oscillator using J51. This is necessary, for
example, when iCE40 Ultra device ball C2 is mistakenly programmed as an output and prevents the FTDI USB interface
from operating.
7. Board Power
The board provides the following power features:
Board Power
Board power is derived from the USB connection.
D3 Green LED indicates Board Power.
iCE40 Ultra VCC
Onboard 1.2 V supply
ICC can be measured across the series resistor R38 (1 Ω) at TP10 and TP11.
iCE40 Ultra VCCIO
Onboard 3.3 V supply
ICC0 can be measured across the series resistor R14 (1 Ω) at TP1 and TP2.
ICC1 can be measured across the series resistor R96 (1 Ω) at TP8 and TP9.
ICC2 can be measured across the series resistor R15 (1 Ω) at TP3 and TP4.
The power supplies on the iCE40 Ultra Breakout Board are simplified and suitable for booting from the external SPI
flash. The power supply sequencing does not conform to the NVCM boot requirements as specified in iCE40 Ultra
Family Data Sheet (FPGA-DS-02028). You may encounter intermittent boot success and/or higher than specified startup
currents when attempting to boot from NVCM.
There are two versions of the BOM. Early versions have D6 populated with a CDBU0520 Schottky. Later versions
populate D6 with a CDSU4148. The later version diode complies with the voltage requirements on the Vpp_2V5 pin for
NVCM programming/configuration.

iCE40 Ultra Breakout Board
Evaluation Board User Guide
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10 FPGA-EB-02034-1.2
8. Board Configuration and Programming
The board allows for programming of the iCE40 Ultra or the SPI Flash:
SPI Flash Programming J10 shunt pins 1-3 and 2-4 (default shunted)
U7 Micron Technology Inc part number N25Q032A13ESC40F
iCE40 Ultra Configuration or Programming J10 shunt pins 1-2 and 3-4
U8 iCE5LP4K-SWG36
CRESETB can be asserted by pushing SW1.
Can be probed with J2
Done LED D2
Can be probed with J3 (default shunted)
Details of the iCE40 Ultra Board for use in programming are shown in Figure 8.1.
CRESETB
Push-Button USB Interface
Socket
J2 – CRESETB Probe
D2 – DONE LED
J50 – Selects HP LED
Device (IR or Torch)
U8 –
iCE5LP4K – SWG36
J10 – Program
SPI Flash or iCE5LP
J9 – Isolate
SPI Flash CSn
U7 –
N25Q032A13ESC40F
Figure 8.1. Configuration and Programming Details

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© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02034-1.2 11
9. Test Points
The board features a number of headers and test connections which provide access to the iCE40 Ultra I/O:
Figure 9.1. J6 Header A Breakouts
Figure 9.2. J7 Header B Breakouts
Figure 9.3. J5 PMOD Connector

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© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12 FPGA-EB-02034-1.2
Figure 9.4. J7 Header B Breakouts
The breakout headers and test connectors are shown in Figure 9.5.
J6 –Header A
J7 –Header B
J1 –Aardvark SPI
emulator connector
J5 –PMOD Connector
Figure 9.5. Breakout Headers

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© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02034-1.2 13
10. RGB LED Demonstration Design and User Interface
The iCE40 Ultra Breakout Board can demonstrate a complete controller for an RGB LED.
To run the demonstration:
1. Ensure that the RGB LED user interface is installed.
2. Make sure the jumpers on J10 are both in the vertical position. This is the default pins 1-3 and 2-4 shorted.
Figure 10.1. SPI Flash Selection for J10 (Vertical)
3. Connect the iCE40 Ultra breakout board through USB cable to a PC or MAC.
4. After the iCE40 Ultra device has initialized and the RGB LED is illuminated RED, change the J10 jumper positions to
horizontal, shorting pins 1-2 and 3-4. This is required to allow the USB port to communicate with the iCE40 Ultra
device.
Figure 10.2. iCE40 Ultra Selection for J10 (Horizontal)

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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14 FPGA-EB-02034-1.2
5. Start the RBG user interface on the PC or MAC.
Figure 10.3. iCE40 Ultra LED Demonstration Interface
You can now control the RGB LED on the iCE40 Ultra Breakout Board. You can set the color, brightness, blinking rate as
well as the breathing.

iCE40 Ultra Breakout Board
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© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02034-1.2 15
11. User Interface Serial Communication Interface
11.1. LED Control through SPI
The software user interface demonstration program communicates with the iCE40 Ultra device using an SPI serial
communication channel. The SPI interface (mode 0) control link is implemented using a simple write-only protocol (see
Figure 11.1).
CSn
SCK
MOSI ADDR [7:0] REG [15:8] REG [7:0]
Figure 11.1. SPI Physical Transaction
11.2. SPI Protocol
Data on the MOSI serial line is transmitted MSB first. Addr[7:0] –Controls which of the 16 bits are updated with REG
data.
Note: Unspecified REG bits must be written, but are ignored.
Table 11.1. ADDR [7:0]
Addr
Bits Written
Bit Position
0x13
REG[3:0]
------------dddd
0x14
REG[7:4]
--------cccc----
0x15
REG[11:8]
----bbbb--------
0x16
REG[15:12]
aaaa------------
0x19
REG[15:0]
aaaabbbbccccdddd
REG[15:0] –Consists of four control fields.
Table 11.2. REG [15:0]
Field
Bits Positions
Function
aaaa
REG[15:12]
RGB Color[3:0]
bbbb
REG[11:8]
Brightness[3:0]
cccc
REG[7:4]
Breathe Ramp [3:0]
dddd
REG[3:0]
Blink Rate [3:0]
11.3. Register Definitions
Table 11.3. RGB Color [3:0]
RGB Color[3:0]
Color
Color Code
0000*
Red
#FF0000
0001
Orange
#FF7F00
0010
Yellow
#FFFF00
0011
Chartreuse
#7FFF00
0100
Green
#00FF00
0101
Spring Green
#00FF7F
0110
Cyan
#00FFFF

iCE40 Ultra Breakout Board
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16 FPGA-EB-02034-1.2
RGB Color[3:0]
Color
Color Code
0111
Azure
#007FFF
1000
Blue
#0000FF
1001
Violet
#7F00FF
1010
Magenta
#FF00FF
1011
Rose
#FF007F
1100
—
1101
—
1110
—
1111
White
#FFFFFF
*Note: Default setting (hardware, software).
Table 11.4. Brightness [3:0]
Brightness[3:0]
Level (%)
0000
6.25(dim)
0001
12.5
0010
18.75
0011
25
0100
31.25
0101
37.5
0110
43.75
0111*
50
1000
56.25
1001
62.5
1010
68.75
1011
75
1100
81.25
1101
87.5
1110
93.75
1111
100 (bright)
*Note: Default setting (hardware, software).
Table 11.5. Breathe Ramp [3:0]
Breathe Ramp [3:0]
Factor
0000*
.0x (fast)
0001
.063x
0010
.125x
0011
.25x
0100
.5x
0101
1x
0110
2x
0111
4x (slow)
1000
—
1001
—
1010
—
1011
—
1100
—
1101
—
1110
—

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FPGA-EB-02034-1.2 17
Breathe Ramp [3:0]
Factor
1111
—
*Note: Default setting (hardware, software).
Table 11.6. Blink Rate [3:0]
Blink Rate [3:0]
Off Time (s)1
0000
Always On
0001
1/16 (fast)
0010
1/8
0011
1/4
0100
1/2
01012
1
0110
2
0111
4
1000
Always Off
1001
—
1010
—
1011
—
1100
—
1101
—
1110
—
1111
—
Note:
1. By default, the LED On-Time is fixed at approximately one second. If desired, the design may be modified so that On-Time is
symmetrical to the Off-Time. To do this, replace the file LED_control.v with LED_control_sym.v and rebuild the design using the
iCEcube2 software.
2. Default setting (hardware, software).

iCE40 Ultra Breakout Board
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18 FPGA-EB-02034-1.2
12. Ordering Information
Table 12.1. Ordering Information
Description
Ordering Part Number
China RoHS Environment-Friendly
Use Period (EFUP)
iCE40 Ultra Breakout Board
ICE5LP4K-B-EVN

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FPGA-EB-02034-1.2 19
Technical Support Assistance
Submit a technical support case through www.latticesemi.com/techsupport.

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20 FPGA-EB-02034-1.2
Appendix A. Schematic Diagrams
Figure A.1. Block Diagram
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
FPGA
Power from USB 5V
SPI
BANK 0
BANK 1
BANK 2
iCE5LP4KSWG36
HEADER B
HEADER B
HEADER A
I/O
I/O
I/O
USB
CONNECTOR
USB to
SPI / RS232
LEDS
BLOCK DIAGRAM
iCE40 Ultra BREAKOUT BOARD
BLOCK DIAGRAM
SPI
Page : 3
Page : 6
Aardvark Connector
Page : 7
BANK 1
Page : 4
Page : 5
Title
Size Document Number Rev
Date: Sheet of
<Doc> AB
27Thursday, March 06, 2014
Title
Size Document Number Rev
Date: Sheet of
<Doc> AB
27Thursday, March 06, 2014
Title
Size Document Number Rev
Date: Sheet of
<Doc> AB
27Thursday, March 06, 2014