Lattice CrossLink LIF-MD6000 Master Link Board - Revision... User manual

CrossLink LIF-MD6000 Master Link Board -
Revision C
Evaluation Board User Guide
FPGA-EB-02018 Version 1.0
June 2018

CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2 FPGA-EB-02018-1.0
Contents
Acronyms in This Document .................................................................................................................................................4
1. Introduction ..................................................................................................................................................................5
2. Headers and Test Connections .....................................................................................................................................7
3. Programming Circuit .....................................................................................................................................................8
3.1. Bridging Circuit ....................................................................................................................................................8
3.2. I2C Expander ........................................................................................................................................................9
4. Power Supply ..............................................................................................................................................................10
5. Status Indicators .........................................................................................................................................................12
6. SMA IO Link Board ......................................................................................................................................................13
7. Breakout IO Link Board ...............................................................................................................................................15
8. Ordering Information..................................................................................................................................................18
References ..........................................................................................................................................................................19
Technical Support Assistance...............................................................................................................................................19
Appendix A. LIF-MD6000-ML-EVN-BRD Schematics ...........................................................................................................20
Appendix B. LIF-MD6000-ML-EVN-BRD Bill of Materials ....................................................................................................28
Appendix C. SMA-IOL-EVN-BRD Schematics .......................................................................................................................34
Appendix D. SMA-IOL-EVN-BRD Bill of Materials................................................................................................................35
Appendix E. B-IOL-EVN-BRD Schematics.............................................................................................................................36
Appendix F. B-IOL-EVN-BRD Bill of Materials .....................................................................................................................37
Revision History...................................................................................................................................................................38

CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02018-1.0 3
Figures
Figure 1.1. Top View of Master Link Board and its Key Components...................................................................................6
Figure 1.2. Bottom View of Master Link Board.....................................................................................................................6
Figure 3.1. Programming Block.............................................................................................................................................8
Figure 3.2. Bridging Block .....................................................................................................................................................9
Figure 3.3. I2C Expander Block ..............................................................................................................................................9
Figure 4.1. Power Supply Block...........................................................................................................................................10
Figure 6.1. Top View of SMA IO Link Board ........................................................................................................................14
Figure 6.2. Bottom View of SMA IO Link Board ..................................................................................................................14
Figure 7.1. Top View of Breakout IO Link Board .................................................................................................................17
Figure 7.2. Bottom View of Breakout IO Link Board...........................................................................................................17
Tables
Table 2.1. Headers and Test Connectors ..............................................................................................................................7
Table 4.1. Power LEDs ........................................................................................................................................................10
Table 4.2. Device Power Rail Summary and Test Points.....................................................................................................11
Table 5.1. Status LED I/O Map ............................................................................................................................................12
Table 6.1. Headers and Test Connectors ............................................................................................................................13
Table 6.2. U1 Connector Description..................................................................................................................................13
Table 7.1. Headers and Test Connectors ............................................................................................................................15
Table 7.2. U1 Connector Description..................................................................................................................................15
Table 7.3. J2 Header Description ........................................................................................................................................16
Table 8.1. Ordering Information.........................................................................................................................................18

CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4 FPGA-EB-02018-1.0
Acronyms in This Document
A list of acronyms used in this document.
Acronym
Definition
CMOS
Complementary Metal-Oxide Semiconductor
CSI-2
Camera Serial Interface
DSI
Display Serial Interface
FTDI
Future Technology Devices International
I2C
Inter-Integrated Circuit
IO
Input/Output
LVDS
Low-Voltage Differential Signaling
MIPI
Mobile Industry Processor Interface
SPI
Serial Peripheral Interface

CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02018-1.0 5
1. Introduction
This document describes the Lattice Semiconductor CrossLink™LIF-MD6000 Master Link Board –Revision C (Rev C) that
supports a variety of demos, encompassing different signaling logic standards bridging with MIPI®CSI-2/DSI interface.
The board‘s key component is the CrossLink Family device that features built in MIPI D-PHY hard blocks to support
different bridging solutions.
For the latest information about this board, including optional Tx/Rx Link boards, demo files, further documentation
and more, see the Lattice website at: www.latticesemi.com/masterlink.
For details about the CrossLink device, refer to CrossLink Family Data Sheet (FPGA-DS-02007).
The content of this user guide includes descriptions of on-board jumper settings, programming circuit, a complete set
of schematics, and bill of materials for LIF-MD6000 Master Link Rev C board.
Refer to Appendix A, B, C, D, E, F for the schematic and BOM of the CrossLink LIF-MD6000 Master Link Rev C board and
the schematics and BOMs of the Breakout IO Link and SMA IO Link boards that are included in the demo kit.
Circuits on the development kit board:
Programming Circuit
Mini USB Type-B connector to FTDI
FTDI to CrossLink using SPI
FTDI to CrossLink using I2C
FTDI to XO3LF device using JTAG
CrossLink
MIPI CSI-2/DSI hard block
Bridging of multiple signaling standards
SPI flash configuration
General Purpose Input/Output
LED display
LCMXO3LF-1300E
I2C muxing
Figure 1.1 shows the top view of the LIF-MD6000 Master Link Rev C board and its key components. Figure 1.2 shows
the bottom view of the board.

CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6 FPGA-EB-02018-1.0
Tx Connectors 1 and 2 (U9, U7)
Power Switch (SW1)
External Power Input
External Power Jack (J3)
LCMXO3L-1300E (U19)
USB 2.0 Mini-B (J2)
JTAG Header (J1)
FTDI Chip (U1)
SPI Flash Device (U14)
Rx Connectors (U11, U12)
Power LEDs
LIF-MD6000-CSFBGA81
Programming Header (J18)
Debug and
Configuration LEDs
Reset and wake-up buttons
Switch (SW2/SW4/SW5)
Clock Source Selection (J26, J27)
Bank 1, 2 Voltage Selection
Headers (J24, J25)
External Clock SMA Inputs
MachXO3 Reset (SW3)
Debug Header (J28)
Debug Header (J31)
Figure 1.1. Top View of Master Link Rev C Board and its Key Components
Figure 1.2. Bottom View of Master Link Rev C Board

CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02018-1.0 7
2. Headers and Test Connections
Figure 1.1 shows the top view of the Master Link Rev C board. The headers and test connections on the board provide
access to LIF-MD6000 Master Link Rev C board circuits. Table 2.1 lists the headers and test connectors.
Table 2.1. Headers and Test Connectors
Part
Description
Setting
J1
External JTAG interface - For LCMX03 only
—
J2
mini-B USB connector
—
J3
External 12V power jack
—
J4
External clock input for MIPI D-PHY reference clock
—
J7
SW2 selector
OPEN-NOP, SHORT-CONFIGURATION RESET
J8
External 12 V terminal block
Open
J9
External 5 V terminal block
Open
J16
SPI/I2C programming selector for LIF-MD6000
1-2 (SPI), 2-3 (I2C)
J18
External SP/I2C access for LIF-MD6000
—
J19
SPI Flash chip select
OPEN-OFF, SHORT-ON
J22
External reference clock input for MIPI D-PHY reference clock
—
J23
LCMXO3L debug header
—
J24
VCCIO1 Bank voltage selector
1-2 (2.5 V), 2-3 (3.3 V), 2-4 (1.2 V)
J25
VCCIO2 Bank voltage selector
1-2 (2.5 V), 2-3 (3.3 V), 2-4 (1.2 V)
J26
Internal/External clock and I2C SDA Mux
1-2 (CLK_INT), 2-3 (CLK_EXT), 2-4 (SDA)
J27
Internal/External reference clock and I2C SCL Mux
1-2 (CLK_INT_REF), 2-3 (CLK_EXT_REF), 2-4 (SCL)
J28
Reveal analyzer signal connector
—
J29
Reset signal voltage selector
1-2 (VCCIO2), 2-3 (VCCIO0)
J31
External SPI/I2C access for LCMXO3L
—
J32
LCMXO3L configuration header
—
J35
SPI/I2C programming selector for LIF-MD6000
1-2 (SPI), 2-3 (I2C)
J36
SPI/I2C programming selector for LIF-MD6000
1-2 (SPI), 2-3 (I2C)
J37
FT2232H reset
OPEN-NORMAL OP, SHORT-RESET
SW1
External adaptor power ON/OFF
—
SW2
Configuration reset for LIF-MD6000
—
SW3
External reset for LCMXO3L
—
SW4*
External reset for LIF-MD6000
—
SW5
PMU WAKEUP Switch for LIF-MD6000
—
U7
Tx Connectors for external interface
—
U9
Tx Connectors for external interface
—
U11
Rx Connectors for external interface
—
U12
Rx Connectors for external interface
—
*Note: Some CrossLink demos utilize this reset signal to ball G9 of Bank 2 while it is configured as a 1.2 V Bank. However, LVCMOS12
inputs are no longer supported across all 3 Banks. Lattice Diamond®Software 3.9 and later will not allow this signal to be placed on a
1.2 V Bank. If it is necessary to recompile one of these demo projects, the necessary modifications should be made to the project
and the board to move this reset signal to a non-1.2 V Bank on CrossLink.

CrossLink LIF-MD6000 Master Link Board - Revision C
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© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8 FPGA-EB-02018-1.0
3. Programming Circuit
The Mini-B USB connector is used for programming the board by using Lattice Diamond Programmer software.
Figure 3.1 shows the programming block of LIF-MD6000 Master Link Rev C board.
The Mini-B USB connector interfaces to the FTDI FT2232H IC. The FTDI IC works with Diamond Programmer software to
provide interfaces for:
JTAG –to program MachXO3 LCMXO3LF-1300E
SPI –to program CrossLink and/or SPI Flash Memory
I2C –to program CrossLink
USB Mini-B
(J2) FTDI Chip (U1)
SPI Flash (U14)
LIF-MD6000
CSFBGA81 (U8)
LCMXO3LF-1300E
MG121 (U19)
JTAG
SPI
SPI/I2C
Figure 3.1. Programming Block
3.1. Bridging Circuit
Figure 3.2 shows the block diagram of bridging of different standard interfaces. The CrossLink device is used as a
bridging device that supports a variety of I/O standards. This demo board supports development of the following
interface bridges:
1:1 MIPI DSI Display Interface Bridge
1:2 MIPI DSI Display Interface Bridge
2:1 MIPI CSI-2 Image Sensor Aggregator Bridge
CMOS to MIPI CSI-2 Image Sensor Interface Bridge
MIPI CSI-2 to CMOS Image Sensor Interface Bridge
MIPI DSI to CMOS Display Interface Bridge
OpenLDI LVDS to MIPI DSI Display Interface Bridge
CMOS to MIPI DSI Display Interface Bridge

CrossLink LIF-MD6000 Master Link Board - Revision C
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© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02018-1.0 9
LIF-MD6000
CSFBGA81 (U8)
Rx Connector 1
Rx Connector 2
D-PHY I/F/
CMOS
D-PHY Rx/
LVDS/CMOS
D-PHY Rx/
LVDS/CMOS
Tx Connector 2
Tx Connector 1
D-PHY I/F/
CMOS
Figure 3.2. Bridging Block
3.2. I2C Expander
Figure 3.3 shows the block diagram of the I2C expander. The LCMXO3LF-1200E device is used as an I2C expander and it
supports a single master and multiple slave devices connected to the board. The master I2C interface is connected to
the Tx header and the slave device I2C interface is connected to the Rx connectors supporting any slave device access
from the master based on the slave address.
LCMXO3LF-1200E-
MG121 (U19)
Rx Connector 1
Rx Connector 2
LIF-MD6000
CSFBGA81 (U8)
Tx
H
e
a
d
e
r
I2C
2 X I2C
2 X I2C
Figure 3.3. I2C Expander Block

CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10 FPGA-EB-02018-1.0
4. Power Supply
The power supply to the development kit is provided by the Mini-B USB connector or from an external adaptor.
Figure 4.1 shows the power supply block of the CrossLink LIF-MD6000 Master Link Rev C board. The external adaptor
provides 12 V power source through voltage regulators on the board to CrossLink and LCMXO3LF-1300E, as well as to
the external boards connected to Tx and Rx Headers. The Mini-B USB connector provides 5 V to the various voltage
regulators and is also used for device programming. Each I/O and core voltage rail on the board is accessible by a test
point on the board. The current flowing to each rail can be measured using a 1 Ω resistor placed in the path of each
voltage rail.
J3
J2
12 V to 5 V
converter
LDO
LDO
LDO
LDO
Power adaptor
Mini-B USB
5 V
5 V
U15
U5
U6
U17
12 V
U18
1.2 V
3.3 V
2.5 V
1.8 V
Figure 4.1. Power Supply Block
Table 4.1 lists the device power rails. There are five voltage regulators on the board used to supply the 5 V, 3.3 V, 2.5V
1.8 V, and 1.2 V rails. The input to these regulators is either from the Mini-B USB connector (J2), an external 12 V
adaptor (J3), or an external power supply to the terminal blocks of J8 or J9. Switch SW1 is used to connect or
disconnect power to the board.
Table 4.1. Power LEDs
Voltage Rail
LEDs
Color
12
D26
Green
5
D3
Green
3.3
D25
Green
2.5
D29
Green
1.8
D28
Green
1.2
D27
Green
Table 4.2 lists the board voltage rails, including the rail source voltage, test point number, and current sense resistor
number.

CrossLink LIF-MD6000 Master Link Board - Revision C
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© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02018-1.0 11
Table 4.2. Device Power Rail Summary and Test Points
Voltage Rail
Source Rail
Current Sense Resistor
Test Points
12 V
—
—
12V0
5 V
12 V
—
5V0
+3.3 V
5 V
—
3V3
+2.5 V
5 V
—
2V5
+1.8 V
5 V
—
—
+1.2 V
5 V
—
1V2
VCC_CORE
+1.2 V
R19
VCC_CORE1
VCCIO0
+2.5 V / +3.3 V
R20 / R24
VCCIO0
VCCIO1
+1.2 V / +2.5 V / +3.3 V
R21 / R25 / R434 / R448
VCCIO1
VCCIO2
+1.2 V / +2.5 V / +3.3 V
R28 / R33 / R435 / R449
VCCIO2
VCC_DPHY
+1.2 V
R417
VCC_DPHY
1K_VCC_CORE
+1.2 V
R190
1K_VCC_CORE1
1K_VCCIO0
+2.5 V / +3.3 V
R410 / R411
1K_VCCIO0
1K_VCCIO1
+2.5 V / +3.3 V
R184 / R185
1K_VCCIO1
1K_VCCIO2
+2.5 V / +3.3 V
R186 / R187
1K_VCCIO2
1K_VCCIO3
+2.5 V / +3.3 V
R188 / R189
1K_VCCIO3

CrossLink LIF-MD6000 Master Link Board - Revision C
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© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12 FPGA-EB-02018-1.0
5. Status Indicators
The LED status indicators on the board show power, configuration, and application status. Table 5.1 lists the status LED
I/O map.
Table 5.1. Status LED I/O Map
Device
LED
Net Name
Color
CrossLink
D6
CMOS_IO_1
Blue
CrossLink
D7
CMOS_IO_2
Blue
CrossLink
D8
CMOS_IO_3
Blue
CrossLink
D9
CMOS_IO_4
Blue
CrossLink
D10
CDONE
Green
LCMX03LF-1300E
D23
DONE
Red
LCMX03LF-1300E
D30
LED1
Blue
LCMX03LF-1300E
D31
LED2
Blue
LCMX03LF-1300E
D32
LED3
Blue
LCMX03LF-1300E
D33
LED4
Blue

CrossLink LIF-MD6000 Master Link Board - Revision C
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© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02018-1.0 13
6. SMA IO Link Board
The SMA IO Link board connects to the CrossLink LIF-MD6000 Master Link Rev C board’s Tx or Rx connectors (U7, U9,
U11 or U12) and transfers signals to the respective SMA connectors.
Table 6.1. Headers and Test Connectors
Part
Description
Mapping to U1
J1
SMA connector for DCK_TX_P
Pin 1
J2
SMA connector for DCK_TX_N
Pin 2
J3
SMA connector for DATA0_TX_P
Pin 4
J4
SMA connector for DATA0_TX_N
Pin 5
J5
SMA connector for DATA1_TX_P
Pin 7
J6
SMA connector for DATA1_TX_N
Pin 8
J7
SMA connector for DATA2_TX_P
Pin 13
J8
SMA connector for DATA2_TX_N
Pin 14
J9
SMA connector for DATA3_TX_P
Pin 16
J10
SMA connector for DATA3_TX_N
Pin 17
J11
SMA connector for DATA4_TX_P
Pin 24
J12
SMA connector for DATA4_TX_N
Pin 25
J13
SMA connector for DATA5_TX_P
Pin 27
J14
SMA connector for DATA5_TX_N
Pin 28
U1
Connector to interface to CrossLink Master Link Rev C board
N/A
Table 6.2. U1 Connector Description
Pin
Name
1
CH4_DCK_P
2
CH4_DCK_N
3
GND
4
CH4_DATA0_P
5
CH4_DATA0_N
6
GND
7
CH4_DATA1_P
8
CH4_DATA1_N
9
GND
10
SN
11
SCLK
12
GND
13
CH4_DATA2_P
14
CH4_DATA2_N
15
GND
16
CH4_DATA3_P
17
CH4_DATA3_N
18
GND
19
12V
20
12V
Pin
Name
21
TBD
22
RESETN
23
PWR_5-0V
24
GND
25
GND
26
PWR_3-3V
27
GND
28
GND
29
PWR_1-8V
30
MOSI
31
MISO
32
PWR_1-8V
33
GND
34
GND
35
PWR_3-3V
36
GND
37
GND
38
PWR_5-0V
39
SDA
40
SCL
Note: U1 connector pin names may be different than the actual signal depending on which CrossLink LIF-MD6000 Master Link Rev C
board connector this daughter board is connected to.

CrossLink LIF-MD6000 Master Link Board - Revision C
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© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14 FPGA-EB-02018-1.0
Figure 6.1. Top View of SMA IO Link Board
Figure 6.2. Bottom View of SMA IO Link Board

CrossLink LIF-MD6000 Master Link Board - Revision C
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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02018-1.0 15
7. Breakout IO Link Board
The Breakout IO Link board connects to the CrossLink LIF-MD6000 Master Link Rev C board’s Tx or Rx connectors (U7,
U9, U11 or U12) and transfers signals to the 26-pin header (J2).
Table 7.1. Headers and Test Connectors
Part
Description
Setting
J2
13x2 Header
—
U1
Connector to interface to CrossLink Master Link Rev C board
—
Table 7.2. U1 Connector Description
Pin
Name
1
CH4_DCK_P
2
CH4_DCK_N
3
GND
4
CH4_DATA0_P
5
CH4_DATA0_N
6
GND
7
CH4_DATA1_P
8
CH4_DATA1_N
9
GND
10
SN
11
SCLK
12
GND
13
CH4_DATA2_P
14
CH4_DATA2_N
15
GND
16
CH4_DATA3_P
17
CH4_DATA3_N
18
GND
19
12V
20
12V
Pin
Name
21
TBD
22
RESETN
23
PWR_5-0V
24
GND
25
GND
26
PWR_3-3V
27
GND
28
GND
29
PWR_1-8V
30
MOSI
31
MISO
32
PWR_1-8V
33
GND
34
GND
35
PWR_3-3V
36
GND
37
GND
38
PWR_5-0V
39
SDA
40
SCL
Note: U1 connector pin names may be different than the actual signal depending on which CrossLink LIF-MD6000 Master Link Rev C
board connector this daughter board is connected to.

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All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16 FPGA-EB-02018-1.0
Table 7.3. J2 Header Description
Pin
Name
Mapping to U1
1
+3.3V
N/A
2
+1.8V
N/A
3
RESETN
Pin 22
4
CH4_DCK_TX_P
Pin 1
5
SDA
Pin 39
6
CH4_DCK_TX_N
Pin 2
7
SCL
Pin 40
8
GND
N/A
9
GND
N/A
10
CH4_DATA0_TX_P
Pin 4
11
CH4_DATA3_TX_P
Pin 16
12
CH4_DATA0_TX_N
Pin 5
13
CH4_DATA3_TX_N
Pin 17
14
GND
N/A
15
GND
N/A
16
CH4_DATA1_TX_P
Pin 7
17
CH4_DATA4_TX_P
Pin 24
18
CH4_DATA1_TX_N
Pin 8
19
CH4_DATA4_TX_N
Pin 25
20
GND
N/A
21
GND
N/A
22
CH4_DATA2_TX_P
Pin 13
23
CH4_DATA5_TX_P
Pin 27
24
CH4_DATA2_TX_N
Pin 14
25
CH4_DATA5_TX_N
Pin 28
26
GND
N/A

CrossLink LIF-MD6000 Master Link Board - Revision C
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© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02018-1.0 17
Figure 7.1. Top View of Breakout IO Link Board
Figure 7.2. Bottom View of Breakout IO Link Board

CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18 FPGA-EB-02018-1.0
8. Ordering Information
Table 8.1. Ordering Information
Description
Ordering Part Number
China RoHS Environment-Friendly
Use Period (EFUP)
CrossLink: LIF-MD6000 Master Link Rev C Board
(Includes 1 SMA IO Link Board and 1 Breakout
IO Link Board)
LIF-MD6000-ML-EVN
CrossLink: LIF-MD6000 IO Link Boards
(Includes 1 SMA IO Link Board and 1 Breakout
IO Link Board)
LIFMD-IOL-EVN

CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
FPGA-EB-02018-1.0 19
References
For more information, refer to CrossLink Family Data Sheet FPGA-DS-02007 (previously DS1055).
Technical Support Assistance
Submit a technical support case through www.latticesemi.com/techsupport.

CrossLink LIF-MD6000 Master Link Board - Revision C
Evaluation Board User Guide
© 2018 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20 FPGA-EB-02018-1.0
Appendix A. LIF-MD6000-ML-EVN-BRD Schematics
LIF-MD6000 Master Link Rev C Board Block Diagram
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USB
CONNECTOR
USB to
JTAG / SPI/I2C
FTDI
USP Programming only
BANK-1,2
DPHY BLOCK
LIFMD-6000-6MG81I
MIPI TX HEADER1
I2C
MIPI TX I/O
BANK-0
LVDS RX HEADER1
SPI
Ext Power
Adaptor (12V) OnBoard LDO'S & Buck
1V2,1V8,2V5,3V3,5V
JTAG_I/F/ SPI/I2C
MIPI TX HEADER2
MIPI TX I/O
LVDS RX HEADER2
I2C
LVDS RX In
LVDS RX In
SPI
BANK-3,4
BANK-2
BANK-0
LCMXO3LF-1300-MG121
JTAG
I2C*3
I/O Expander - I2C Switch
Targeted FPGA
SPI FLASH
I2C
SPI
SPI I2C*2 I2C*1
SPI
SPI
I2C
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: [e-mail]
Board Rev
Project
28-Mar-17
B1.0
81
BLOCK Diagram
CrossLink_Master_Multi-Link_Board 1
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: [e-mail]
Board Rev
Project
28-Mar-17
B1.0
81
BLOCK Diagram
CrossLink_Master_Multi-Link_Board 1
Date:
Size Schematic Rev
ofSheet
Title
Lattice Semiconductor Applications
Email: [e-mail]
Board Rev
Project
28-Mar-17
B1.0
81
BLOCK Diagram
CrossLink_Master_Multi-Link_Board 1