Lenovo VIBE Z K910L User manual

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VIBE Z K910L
Service Manual
LENOVO

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PREAMBLE
The maintenance of the product is divided into three levels
Level 1 maintenance without some special maintenance tools, only have empirical
maintenance, generally this level do not use the hot air gun, and do not maintain the
mobile phone with IC fault, when necessary, IC fault repair is need with the company
agreement.
Level 2 maintenance is mainly to solve the problem that level 1 maintenance can't
solve, when necessary, hot air guns, electric iron, the oscilloscope, the ensemble
instrument and other professional maintenance tools are required, to solve various
fault , any a components of the phone can be modified.
Level 3 maintenance is mainly to solve the problem that the secondary maintenance
can't solves, this problem will be solved by the research and development center.
Important declaration
This handbook applies to the experienced techniques who familiar with the similar
equipment, it mainly as the technical support of electronic and mechanical
maintenance. This handbook is appropriate for the Level 2 maintenance operator of
K860 mobile phone. When out-of-range this handbook, please contact with the
customer support department or the research and development center of Lenovo
mobile communication technology co., LTD. Thank you!

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Contents
1. Technical Specifications...........................................................................................................4
2. Working Principle.....................................................................................................................4
2.1 General Description ......................................................................................................4
2.2 Application processor....................................................................................................7
2.3 Power Management.....................................................................................................12
2.4 Audio Codec ...............................................................................................................18
2.5 Wireless Connectivity.................................................................................................18
2.6 LTE RF Transceiver....................................................................................................19
3. Main board and Sub FPC layout introduction.........................................................................22
3.1 Main board top view...................................................................................................22
3.2 Main board bottom view.............................................................................................23
3.3 Sub FPC top view .......................................................................................................23
3.4 Sub FPC bottom view .................................................................................................24
4. Troubleshooting Procedure.....................................................................................................25
4.1 No Boot.......................................................................................................................25
4.2 Touch panel have no effect..........................................................................................27
4.3 Charging anomaly.......................................................................................................28
4.4 Calling receiver sound has poor quality......................................................................31
4.5 Speaker has no sound..................................................................................................32
4.6 No screen display........................................................................................................34
4.7 Phone crash.................................................................................................................37
4.8 Key has no effect.........................................................................................................39
4.9 Communication signal abnormality............................................................................41
4.10 Calling receiver has no sound.....................................................................................43
4.11 Display color distortion...............................................................................................45
4.12 Speaker tone distortion................................................................................................47
4.13 Speaker tone smaller...................................................................................................49
4.14 No charging.................................................................................................................50
5How to assemble and dissemble LENOVO K910L................................................................41

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1.Technical Specifications
Equipment
Name
LTEDigital Mobile Telephone
Trade Name
Lenovo K910L
Model
Number
Lenovo
ITEM
TRADE / MODEL
DESCRIPTION
Key Part of Host
CPU
MSM8974
4 Krait CPU 2.3GHz, 2M L2 cache
BB
MSM8974
QDSP6 600MHz
Graphics
Display
5.5" FHD IPS LCD 1080*1920
Storage(Hard
Disk)
KLMAG2GEAC-B001
16GB eMMC 21nm Samsung
Battery
Lithium polymer battery 3000mAh 3.8v
ACAdapter
Input:AC100-240V~50/60Hz 0.15A
Output:DC5V-1500mA
WWAN Module
WWAN
Module
LTE
WLAN Module
WLAN
Module
WLAN
Supports : 802.11b/g/n
Frequency(MHz) :2412~2472;5170~5805
Ant. Type : Internal
Bluetooth Module
BT Module 1
BT
Supports : BluetoothV2.0+EDR
Frequency (MHz) : 2402~2480
Ant. Type : Internal
2.Working Principle
3. General Description
The hardware system of K910L includes PMU, AP, and wireless connectivity, audio
codec, and LTE RF transceiver. The PMU is composed of PM8941 and PM8841. The
AP is composed of CPU MSM8974, related digital circuit and peripheral interface
(USB, KEYPAD, and LCD). The Wireless Connectivity is composed of WCN3680
and related digital circuit; include WLAN, BT, and FM. LTE RF transceiver is

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composed of WTR1605L and related digital circuit.
The following figure is a block diagram of the hardware design system.
The hardware of K910L is composed of the main board, USB, P-Sensor, volume
key FPC. As shown below.
The following figure is marked major chip and functional distribution on the

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main board.

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4. Application processor
4.1.1 General Description
Feature
MSM8974 capability
Processors
Applications
Four Krait uP cores up to 2+ GHz; 2 MB L2 cache
Modem system
QDSP6 v5 core at up to 600 MHz
16k L1 instruction; 32k L1 data; 256k L2 caches
RPM system
Cortex M3 - primary boot processor
–better suited for code certification and warm boot
–brings up secure root of trust (SROT) Krait uP quickly
The only master of the modem power manager (MPM)
MPM coordinates shutdown/wakeup, clock rates, and VDDs
Boot flow is RPM / applications processor-based
Low power audio
QDSP6 v5 core at 600 MHz; 16k/32k L1 and 256k L2
caches
WLAN/BT/FM
ARM9
Memory support
Internal memory via PoP & EBI
2x LPDDR3 SDRAM; 32-bit wide; up to 800 MHz
Other internal memory
1.5 MB unified SRAM pool on-chip memory (OCMEM)
External memory
Via SDC1
Via SPI
eMMC NAND flash devices
NOR memory devices (user-modified SW)
RF support
RF operating bands
Defined by WTR device
Air interfaces
GSM
CDMA
WCDMA
TD-SCDMA
LTE
WLAN/BT/FM
See 'Air interface features' section for details
Yes –all
Yes –MSM8674, MSM8974 type 2
Yes –all (supported data rates depend upon MSM variant)
Yes –MSM8274 (both types), MSM8974 type 1
Yes –MSM8974 (both types)
Yes –all (with WCN3660)
GNSS –gpsOne engine
Gen 8B; GPS and GLONASS
Multimedia
Display support
MIPI_DSI
HDMI
eDP
Example combinations
Up to three concurrent displays; two panels + external
Two; 4-lane + 4-lane
Yes; v1.4
Yes; v1.2 4-lane
2560x2048 + 1080p external
2048x1536 + 1920x1200 + 1080p external
2048x1536 + 4kx2k external

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General display features
Color depth –24-bit pp; TFT, LTPS, CSTN, OLED panels
Camera interfaces
MIPI_CSI
2D performance
3D performacne
General camera features
Qcamera; dual ISP
Three 4-lane or four at 4 + 4 + 1 + 1 lanes; 1.5 Gbps per lane
32 MP at 15 fps; 16 MP at 30 fps
12 MP at 15 to 24 fps; 8 MP at 30 fps
Pixel manipulations, camera modes, image effects, and post
processing techniques, including defective pixel correction
VFE raw dump of CSI data at line rate
SMIA++ support
I2C or SPI controls
Mobile display processor
MDP 5
Video applications performance
Encode
Decode
1080p at 120 fps; 4kx2k at 30 fps; 4x 1080p at 30 fps
–H.264/263, MPEG4, VP8
1080p at 60 fps 2-view –MVC
1080p at 120 fps; 4kx2k at 30 fps; 4x 1080p at 30 fps
–H.264/263, MPEG4/2, WMV9, VC1, VP6/8, DixX, XVID
1080p at 60 fps 2-view –MVC
Graphics
Adreno 330 450 MHz 3D graphics accelerator
225 M peak triangles/sec; 3600 M peak 3D pixels/sec
APIs include OpenGL® ES 1.1/2.0/3.0, OpenCL1.2,
DX9.3
Audio
Codec
Low power audio
Voice codec support
Audio codec support
Enhanced audio
Integrated within the WCD9320 device
7 DACs, 8 outputs; 6 inputs, 6 ADCs; 6 digital MICs
Multi-button headset control; MIC activity detection
Low power, low complexity; 7.1 surround sound
Verstile –many audio playback & voice modes; encoders
for
audio & FM recording; many concurrency modes
SILK; QCELP, EVRC, EVRC-B, EVRC-WB;
G.711, G.729A/AB; GSM-FR, -EFR, -HR; AMR-NB, -WB
MP3; AAC, +, eAAC; WMA 9/Pro; Dolby AC-3, eAC-3,
DTS
Surround sound: Dolby TrueHD; DTS-HD; DTS Express
7.1
Fluence Noise Cancellation; enhanced speaker protection
QAudioFX™ / Qconcert™ / QEnsemble
A/V output –HDMI Rev 1.4a
Yes
Integrated HDMI Tx core and HDMI PHY
1080p at 60 Hz refresh; 24-bit RGB color
Up to 8-ch audio for 7.1 surround sound
Dolby Digital Plus, Dolby True-HD, & DTS-HD Master
Web technologies
V8 JavaScript Engine optimizations

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Webkit browser JPEG hardware decode acceleration
Networking Stack IP and HTTP tuning
Flash 10.1 & Video Processor decode optimization
Messaging
Text messages; text encoding for SMS
Multimedia messaging services –combined video
(MPEG4),
still image (JPEG), voice tag (AMR), text sent as message
Digital Mobile Broadcast (DMB)
External IC required; dual TSIF for 12 segment ISDB-T
Connectivity
BLSP ports
UART
UIM
I2C
SPI (master only)
12, 4 bits each; multiplexed serial interface functions
Yes –up to 4 MHz
Yes –SIM, USIM, CSIM; dual V (1.8/2.85) is available 1x
Yes –cameras, sensors, near field communicator (NFC), etc
Yes –cameras, sensors, etc; NOR memory with SW mods
UIM (other than via BLSP)
One –dual voltage (1.8/2.85)
USB
Two USB 2.0 high-speed and One USB 3.0 super-speed
HSIC
Dual-voltage (1.2/1.8)
MSM to/from external application processor
Easy integration, low-power, & low processor loading
Secure digital interfaces
SDC1 and SDC2 are dual-V
Up to 4 ports; one 8-bit and three 4-bit; SD3.0
SD/MMC card; eMMC NAND; DMB; WLAN; eSD/eMMC
boot
TSIF
Up to two ports; DMB support
Audio interfaces
SLIMbus
I2S
MI2S
PCM
Highly multiplexed, high-speed; baseline WCD interface
Up to 4 ports (primary & seconday speakers & mics)
Microphone & speaker functions, including 7.1 audio for
HDMI
One port is available
Wireless connectivity
WLAN
Bluetooth
FM radio
WCN3660 or WCN3680
Both WCNs support 802.11a/b/g/n; WCN3680 adds
802.11/ac
BT 4.0 LE and earlier
Worldwide broadcast
Touchscreen support
Capacitive panels via ext IC (I2C, SPI, & interrupts)
DMB support
Via external DMB device (SDC or TSIF)
Configurable GPIOs
Number of GPIO ports
146 –GPIO_0 to GPIO_145
Input configurations
Pull-up, pull-down, keeper, or no pull
Output configurations
Programmable drive current
Top-level mode multiplexer
Provides a convenient way to program groups of GPIOs
Internal functions
Security
General security features
Secure boot, SFS, OMA DRM 1.0/2.1, ARM TrustZone,

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Crypto engine
QFPROM
Security controller
SEE,
secure debug, Microsoft WM DRM10, HDCP for HDMI
V4; algorithm accelerate file system encryption (AES-XTS)
and IPSec & SSL (HMAC-SHA, CCM, CBCMAC)
Large fuse array, replaces previous-generation Qfuse chains
Non-volatile memory with faster and simpler programming
Chip-wide configuration for security, feature enable, &
debug
Persistent storage of ID numbers and sensitive key data
Support for the HDCP standard needed for HDMI
Secure HDCP key provisioning and secure debug facility
Gateway for all software and JTAG accesses to the
QFPROM
Primary and secondary hardware key blocking for SFS
Boot sequence
1) RPM system, 2) application system, 3) modem system
Emergency boot over HS-USB (on USB 3.0 port)
Power-on boot to carrier splash screen < 0.4 seconds (target)
Power-on boot to network access < 20 seconds (target)
PLLs and clocks
Multiple clock regimes; watchdog & sleep timers
Inputs: 19.2M CXO, 48M WCN_XO for 5 GHz WLAN,
General-purpose outputs: M/N counter, PDM
Resource and power manager
Fundamental to bootup and power management
Key blocks: RPM core, Cortex M3, security controller,
MPM
Improved efficiency via clock control, split-rail power
collapse
& voltage scaling; several low-power sleep modes
Debug
JTAG, Design for Software Debug (DFSD), & ETM (all
cores)
Others
Thermal sensors; modes & resets; perhiperal subsystem
Chipset and RF front-end (RFFE) interface features
WTR RF transceivers
Baseband data
Status & control
4 Rx & 2 Tx analog interfaces
2 SSBIs for each RFIC plus other lines as needed via GPIOs
Power management
2-line SPMI; plus other lines as needed via GPIOs
WCD audio codec
SLIMbus
Legacy
Others
Highly muxed, high-speed audio data plus status & control
Optional I2S for audio data plus I2C for status & control
Status, control, & clock lines as needed via GPIOs
WCN wireless connectivity
WLAN baseband data
WLAN status & control
Bluetooth
FM radio
Multiplexed Rx/Tx analog interface
Secure digital
2-line data interface plus dedicated SSBI
1-line data interface plus dedicated SSBI

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Fabrication technology and package
Digital die
28 nm HPm CMOS
Small, thermally efficient
package
990 PNSP: 15 x 15 x 0.91 mm (w/o memory device on top)
Bottom pin array of PoP
Same as 990-pin nanoscale pkg (990 NSP); 0.4 mm pitch
Top pin array of PoP
Same as 216-pin chipscale pkg (216 CSP); 0.5 mm pitch
4.1.2 Block Diagram
The following block diagram of MSM8974.

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5. Power Management
5.1.1 Block Diagram
PM8941 have five major functional blocks:
1) Input power management
2) Output power management
3) General housekeeping
4) User interfaces
5) IC-level interfaces
PM8841 have two major functional blocks:
1) Output power management
2) IC-level interfaces

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5.1.2 General Features
Summary of PM8941 & PM8841 Features:
Feature
PM8941 capability
PM8841 capability
Input power management
Supported external power sources
USB and/or wall charger
Over-voltage protection
USB
Wall charger
Fully integrated up to +28 V
(integrated OVP FET)
Fully integrated up to +15 V
(integrated OVP FET);
external pass device is
supported for higher voltage
Supported battery technologies
Lithium-ion, lithium-ion
polymer
Charger regulation method
Efficient switched-mode
battery charger; 4 control
loops: USB in
current, VCHG in voltage,
VPH_PWR out voltage, &
battery current
Supported charging modes
Trickle, constant current, and

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constant voltage modes
More automated for less
software interaction
ATC indicator supply
Voltage options when
RGB_RED driver is used for
ATC indication
Battery MOSFET
Integrated
Voltage, current, & thermal
sensors
Internal and external nodes;
reported to on-chip
state-machine
Battery monitoring system
Including battery fuel gauge
for better accuracy
Coin cell or capacitor backup
Keep-alive power source;
orchestrated charging
Output voltage regulation
Switched-mode power supplies
HF-SMPS
Individual FT-SMPS
Boost (5V)
Three; two at 2.0 A each, one
at 1.0 A
One at 1.0 A
Two; one at 2.0 A, one at
1.0 A
Two; each at 3.0 A
Four; each at 3.0 A
Low-dropout linear regulators
24 total: NMOS at 1.2 A (3),
300 mA (2); PMOS at 600
mA (4), 300
mA (5), 150 mA (6), 50 mA
(2) and 2 for clocks
Pseudo-capless LDO designs
TBD of 24 LDOs
Voltage switches
Suitable for power gating
external circuitry: 3 at 1.8 V,
2 at 5 V
General housekeeping
On-chip ADC
Shared housekeeping (HK)
and XO support
Analog multiplexing for ADC
HK inputs
XO input
Many internal nodes &
external inputs including
configurable MPPs
Dedicated pin (XO_THERM)
Over-temperature protection
Multistage smart thermal
control
Automatic fault protection
At fault: PMIC powers off,
ignores all power-on triggers

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except
KPD_PWR_N, and turns
VREG_FAULT on
19.2 MHz oscillator support
XO (with on-chip ADC)
XO controller and XO outputs
5 sets: 3 low-noise outputs
(A) and 2 low-power outputs
(D)
Differential XO clock output
One
Special purpose clock outputs
Extra sleep clock; 19.2, 9.6,
4.8, 2.4, and 1.2 MHz,
including low
power mode 2.4 MHz for
MP3; 4 high-speed GPIOs for
fast clocks
32 kHz clock source (optional)
XO source eliminates 32.768
kHz crystal if desired
Realtime clock
RTC clock circuits and
alarms
User interfaces
30 V WLED boost converter
Generates supply voltage for
white LEDs
WLED sinks
Three (matched); supports
strings of up to 8 white LEDs
each
Keypad backlighting
General-purpose
sources/sinks that can be used
for backlighting
Camera flash drivers
Two; flash and torch modes
RGB drivers
Three –one for each color, 12
mA each
Other current drivers
MPPs can be configured to
sink up to 40 mA
ATC indicator (shared with
red RGB driver)
Light pulse generators
8-channels for WLEDs,
RGBs, vibration motor, and
GPIOs
4-channels for
general-purpose sources/sinks
Controls for external current
drivers
Four PWM outputs (GPIOs)
Vibration motor driver
1.2 to 3.1 V in 100 mV
increments

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IC-level interfaces
Primary status and control
2-line SPMI
2-line SPMI
PMIC control
Power-on, resets, and shared
SPMI
Power-on, resets, and shared
SPMI
Interrupt managers
Supported by SPMI
Supported by SPMI
Optional hardware configurations
OPT bits select hardware
configuration
OPT bits select hardware
configuration
Power sequencing
Power-on, power-off, and soft
resets
Power-on, power-off, and
soft resets
Extra features
Level translation; ext
regulator enables; detect ins
& interrupt outs
Level translation; ext
regulator enables; detect ins
& interrupt outs
Configurable I/Os
MPPs
8; configurable as digital ins
or outs; level-translating
bidirectional I/O s; analog
multiplexer ins; or VREF
analog outs
4; configurable as digital ins
or outs; level-translating
bidirectional I/O s; analog
mux ins; or VREF analog
outs
GPIO pins
36; configurable as digital ins
or outs or level-translating
I/Os; all
much faster than MPPs; 4
special high-speed GPIOs for
clock outs
Package
Size
5.82 ×6.15 ×0.55 mm
4.45 ×3.58 ×0.55 mm
Pin count and package type
229-pin WLNSP
98-pin WLNSP

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5.1.3 The Power on Sequence

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6. Audio Codec
6.1.1 Block Diagram
WCD9320 have four major functional blocks:
1) Rx processing
2) Tx processing
3) Additional processing (noise cancellation, etc.)
4) Shared support functions
7. Wireless Connectivity
WCN3680 have four major WCN functional blocks
1) Bluetooth radio
2) WLAN RF transceiver
3) FM radio
4) Shared support circuits

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8. LTE RF Transceiver
WTR1605L have three major functional blocks:
1) RF transmitters
2) RF receivers
3) Shared support circuits

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Summary of WTR1605/WTR1605L Features:
Feature
WTR1605/WTR1605L capability
RF operating bands
See next page
Air interfaces
GSM
CDMA
WCDMA
LTE
TD-SCDMA
See modem IC documentation for details
GSM Rel ‘99, GPRS, EDGE with DTM
1X, 1X Advanced, 1xEV-DOr0/rA/rB
WCDMA Rel ‘99, HSDPA, HSUPA, HSPA+, DC-HSPA+
1.4 to 20 MHz; FDD and TDD (1605Lonly)
Bands 34, 39, 40, and 41
GNSS –supported modes
Standalone, MS-A, MS-B, XTRAGPS, GLONASS
Integrated RF transceivers
Transmit driver amp outputs
Primary Rx LNA inputs
Diversity Rx LNA inputs
9
7
4
Integrated GNSS RF receiver
Dedicated circuits support GPS and GLONASS