Motorola V2288 User manual

V2288
Level 3
Circuit Description
17 / 02 / 99
V1.0
Ver

Motorola Internal Use 2
V2288 – Circuit Description
V2288 Level 3 Product Guide
RF: Receive
1) The RF Signal from the base station is received through the Antenna A100 and is fed
to J300, which is a purely mechanical switch which is operated when an cable is
plugged into the Aux RF socket of the phone. This connects RF to the Aux RF port or
the antenna.
2) The RX signal is then fed directly into U100 RF Switch, the switch acts as an
isolation between TX and RX, this is controlled via the signals VA and VB which are
previously created by TX_EN and RX_EN respectively through Q110.
3) Provided VB is high, then the received signal will be passed to the band pass filter
FL470, where the selected frequency band (GSM 1800 or GSM900) will be filtered
through, *Note. The front-end filter has a bandwidth that is capable of working with
the American GSM standard 1900Mhz. This gives the option of creating a PCS unit
without the need to change many components.
4) The appropriate signal is then fed onto FL472 (For GSM 1800) or FL480 (For 900)
where any existing harmonics or other unwanted frequencies are removed.
5) Our received RF frequency is now fed into the Front End IC (U432). This IC is new
to the T2288 and has several main purposes; reduce discreet part count and therefore
cost as it replaces the mixer stage and also the two other front end filters from
previous products and also the main RX VCO buffer. (Refer to Front End IC
Document for internal block diagram interpretation). The IC’s power is maintained by
RF_V2 (MAGIC), and is controlled with the aid of RVCO_250 (created by SF_OUT
(MAGIC) and GPO4 (MAGIC) through Q172), RX_EN (Whitecap) and DCS_SEL
(MAGIC). The GSM 900 signal is fed in through Pin 13, back out through Pin 12 to
matching circuitry, then returns to the IC on Pin 9, where the signal is internally
mixed with the RX VCO signal to produce a balanced + and – 400 MHz IF Signal.
The main reason for using the balanced IF output is to provide cancelling of the 3rd
harmonic. This is then fed out on Pins 3 and 4. The GSM 1800 route is of the same
description but uses the Pins 18-20-23-3 and 4.
6) The RX VCO U253 is now an integrated circuit and is controlled firstly from the
Whitecap using the MQ SPI bus to program the MAGIC and then MAGIC drives the
RX VCO IC using the CP_RX signal Pin B1. The power is supplied by RVCO_250
(SF_OUT + GPO4 through Q172).
7) The + and – IF, is now fed to the SAW FL490 filter (Surface Acoustic Wave), this
filter is the same as was used in previous 400MHz products, and is balanced to accept
the new + and – IF.
8) The signal is then passed to the MAGIC IC U200 PRE IN Pin A7
9) The signal is then demodulated internally using an external Varactor diode RX Local
Oscillator set up CR249, which is driven by PLL CP Pin A9 of MAGIC U200.
10)Where in earlier products, we used to have RX I and RXQ, these signals are now
only used in digital form within the MAGIC and cannot be measured. The
demodulated signal is now converted internally to digital form to be passed along an
RX SPI bus to the Whitecap.

Motorola Internal Use 3
V2288 – Circuit Description
11)The RX SPI signal is made up of BDR (Base band Data Receive), BFSR (Base band
Frame Synch Receive) and BCLKR (Base band Clock Receive, fed from MAGIC
Pins G8, G9 and F7 respectively.
12)The Whitecap U800 receives these signals on Pins A3, D4 and B4, within the
Whitecap the signal is digitally processed. Baud rate reduced, Error correction bits
removed, etc…
13)The digital signal is now being fed down the DI_AUD_SPI bus to the GCAP II
U900, internally, the digital signal is converted to analogue and distributed to the
correct outputs
14)For Earpiece, from GCAP II Pins H6 and H7 to speaker pads J502 and J503
15)The Alert is generated within the Whitecap, given the appropriate data from the
incoming signal, SMS, call etc… and is fed to the alert pads J510 and J511. This
signal is supported by the signal ALRT_VCC, which is generated from B+ through
Q903.
16)For the headset only the SPKR- signal is used and feeds the Stereo Audio IC U1500,
Pin 12, and is fed out on Pin 1, the exact operation of which can be found in the
Level 3 Block diagram IC description. The output is then fed out on HEADSET_L to
the Headset Jack socket J504. *NB There is no stereo headset operation for voice
calls.
RF: Transmit
1) There are 2 Mic inputs, firstly from the Xcvr mic J900, where the analogue input is
fed to the GCAP II U900 Pin J2
2) Secondly the analogue voice can be fed from the Aux Mic attached to the headset and
will be routed from connection 1 of the headset jack J504, through to GCAP II, Pin
H3.
3) Within the GCAP II the analogue audio will be converted to digital and clocked out
onto the DI_AUD SPI bus to the Whitecap U800.
4) It is within the Whitecap that all information about the transmission burst is
formulated i.e. The timing of the burst / The channel to transmit on / The error
correction protocol / In which frame the information will be carried to the base
station, etc, etc…
5) All this information is then added to the digitised audio and is transferred to the
MAGIC U200 along a TX SPI bus. The bus is made up of BCLKX (Base band Clock
Transmit) Pin B2 and BDX (Base band Data Transmit) Pin B6. The timing for this
data is already decided for the transmission burst, and therefore a frame synch is not
required.
6) The SPI comes into the MAGIC at Pin G7 (BCLKX) and Pin J2 (BDX)
7) The operation of the MAGIC is very complex and with respect to the transmit path,
intergrates the functions of the Modem and its function of GMSK (Gaussian
Minimum Shift Keying) and also the functions of the TIC (Translational Integrated
Circuit).

Motorola Internal Use 4
V2288 – Circuit Description
8) A very basic block view of how the transmit path works within the MAGIC is
demonstrated in: Fig 8.1
Internal MAGIC Operation Fig 8.1
9) The data is transmitted from Whitecap to MAGIC on TX SPI bus BDX, within the
MAGIC each bit of data is clocked into a register. The clocked bit and the 3
preceding bits on the register are then clocked into the look up ROM, which looks at
the digital word and from that information downloads the appropriate GSMK digital
representation. Channel information and AFC information from MAGIC SPI is then
added to this new digital word, this word is then representative of the TX IF
frequency of GIFSYN products. As in the case of the TIC, the TX frequency
feedback and the RX VCO frequency are mixed to give a difference signal, this is
digitally phase compared with the ‘modulation’ from the look up ROM. The
difference creates a DC error voltage TX_CP that forms part of the TX Phase locked
loop.
10)The error correction voltage TX_CP is then fed from Pin B1 of MAGIC to Pin 6 of
the TX VCO IC U301, adjoining this line is the loop filter (See Loop Filter
document).
11)The Loop filter comprises mainly of U310 / Q310 / Q311 and it’s main function is to
‘smooth’ out any overshoots when the channel is changed, see Fig 11.1. If this
overshoot were fed to the TX VCO the resulting burst would not meet the world
standards for GSM with respect to bandwidth, see Fig 11.2.
Channel 24
TX_CP
CLK
BDX
Look
Up
ROM
Σ
AFC
Channel
Info
Digital
representation
of TX VCO
F/B
Digital
representation
of RX VCO
CLK
Overshoot
Channel 56
Fig 11.1
Acceptable
3dB
Bandwidth
Unacceptable
3dB
Bandwidth
Fig 11.2

Motorola Internal Use 5
V2288 – Circuit Description
12)The Loop filter basically acts then as a huge capacitor and resistor to give a long CR
time for smoothing. It uses a small capacitor and the very high input impedance
buffer Op-Amp. During the TX_EN (Whitecap) period when the transmitter is
preparing to operate the capacitor charges, then on receipt of DM_CS (Whitecap)
when the Transmitter actually fires; the capacitor discharges through the Op-Amp
giving a smooth tuning voltage, carrying modulation to the TX VCO. The support
voltage for the Loop filter is V1_SW (V1 from GCAP II through Q913).
13)The TX VCO IC now creates our required output frequency with the support signals
DCS_TX_VCO (DCS_SEL (U110) +TX VCO_EN (Q140) through Q130) and
GSM_TX_VCO (GSM_SEL (U110) +TX VCO_EN (Q140) through Q130), to
enable either GSM or DCS frequency production and the IC Power is supported by
SF_OUT (MAGIC).
14)The signal is then fed out through a buffer amplifier Q320, which is switched on and
off via DM_CS and supported by RF_V2 (MAGIC)
15)To prevent the output frequency from the TX VCO before stabilisation has occurred,
being amplified and transmitted, there is an Isolation Diode CR320 placed. This is
biased ‘on’ by the exciter voltage from the PAC IC U350 (Power Amplifier Control
IC); this allows the TX output frequency through to the Exciter Amplifier Q330 and
at same time gives more or less drive to the exciter stage.
16)The signal is then fed to a two stage, wide bandwidth PA made up from Q331 and
Q370, these are driven by the exciter voltage from the PAC IC, and supported by B+
and REG_B+ (Q332 / Q333 B+ regulated by TX_EN).
17)PA matching is provided using the signal TX_GSM_*DCS (TXVCO_EN +
DCS_SEL through Q160) to switch on or off the diodes CR380 / 370 / 390 / 350 and
340 to match the PA between GSM and DCS using the inductive strips on the PCB.
18)The amplified signal is then fed back to the RF switch U100, as discussed in Receive,
then passed to the Ant / Aux Switch J300 and transmitted through either the antenna
A100 or the Aux testing port.
RF: Power Control Operation
1) The PAC IC U350 (Power Amplifier Control Integrated Circuit) controls the power
control of the transmitter. Below is a list of the main signals associated with the PAC
IC and their purposes.
2) The RF detector (RF_IN Pin 2) provides a DC level proportional to the peak RF
voltage out of the power amplifier, this is taken via an inductive strip from the output
of the PA Q370.
3) DET_SW Pin 11. This pin controls the variable gain stage connected between the RF
detector and the integrator. The gain of the variable stage will be unity when
DET_SW is low and will be 3 when DET_SW is high (floating).
4) TX_KEY Pin 10. This signal is used to ‘pre-charge’ the Exciter and P.A. and occurs
20µS before the start of the transmit pulse.
5) EXC Pin 7.This output drives the power control port of the exciter. An increase of
this voltage will cause the exciter to increase its output power.

Motorola Internal Use 6
V2288 – Circuit Description
6) SAT_DET Pin 12.If the feedback signal from the RF detector lags too far behind the
AOC signal then this output will go low, indicating that the loop in at or near
saturation. This signals the DSP to reduce the AOC_DRIVE signal until SAT_DET
rises. See Fig 6.1
7) AOC_DRIVE Pin 8. The voltage on this pin will determine the output power of the
transmitter. Under normal conditions the control loop will adjust the voltage on EXC
so that the power level presented to the RF detector results in equality of the voltage
present at INT and AOC. The input level will be between 0 and 2.5V.
8) ACT Pin 9. This pin will hold a high voltage when no RF is present. Once the RF
level increases enough to cause the detector to rise a few millivolts then this output
will go low. In the GSM radio a resistor is routed between this point and the AOC
input to cause the radio to ramp up the power until the detector goes active.
Logic: Power Up sequence
1) Three power sources available, battery, External Power via Charger (Battery must be
present to power up) a power source via the test adapter, to allow power to be
applied to the unit whilst there is no battery present.
2) T2288 charger will only work with NiCd and NiMH, Lithium Ion and Alkaline
batteries are not supported.
3) Battery Power Source: The unit will contain 3 X 1.2V Nickel Metal Hydride (NiMH)
cells each 700mAH, type AAAL (theses are different to AAA regular batteries) part
number SNN5518A. They are connected to the unit by battery contacts J605 and
produce B+ through Q691
4) Charger Power Source: When the charger is connected (IRQ4 goes low), V2 (GCAP)
will provide a supply onto the sense resistor within the charger, the resultant voltage
drop over the resistor is sensed by the signal MAN_TEST_AD (approximately 2.4V),
CHGR_SW must be high. This is sent to the GCAP II Pin A1, this decides the
charging current that the charger is capable of delivering. The GCAP II then checks
the MOBPORTB line (PWR_ON from COVIC U960). If the batteries are present
and in usable range, PWR_ON is pulled to 6.7V and the unit will power on. The
DMCS
goes high
TX starts
TX_KEY
goes high
SAT_DET
goes low
Linear ramp
down begins
SAT_DET
goes high
Ramp down
ceases
TX_KEY
Goes low
DMCS
goes low
Fig 6.1

Motorola Internal Use 7
V2288 – Circuit Description
presence detection of the batteries is decided within the COVIC by comparing the
actual battery voltage with the B+ created by the charger (Q960àCR960àQ691). If
B+ is higher than the normal operating voltage of the batteries, PWR_ON will go
low, powering the phone off. Battery voltage is sensed by B+ Pin E10 GCAP II when
battery not present, or BATTERY Pin F7 GCAP II when batteries are present this is
then output to Whitecap as BATT_SENSE.
5) Test Adapter Source: B+ is sent directly from the external power source i.e. replaces
the battery power source entirely and therefore the unit has no requirement for the
batteries to be present.
6) The GCAP II is programmed to Boost mode (5.6V) by PGB0 Pin G7 and PGM1 Pin
G8 both being tied to Ground. Once B+ is applied to GCAP II Pin K5, all the
appropriate voltages to supply the circuit are provided. These are:
•V1 – Programmed to 5.0V. V1 is at 2.775V at immediate power on, but is ‘boosted’
to 5.0V through the switch mode power supply L901 / C901 / CR902 and C913. See
Fig 6.1 for basic operation. V1 supplies the DSC bus drivers, negative voltage
regulators and MAGIC. V1 is created from GCAP II Pin A6 and can be measured on
C906.
The basic circuit operation for the Boost circuit is as follows the LX signal (GCAP II
Pin B10) allows a path for B+ to charge the capacitor, when the switch is on, the
capacitor then discharges through the inductor (switch off), setting up an electric
field. The field then collapses setting up a back EMF to charge the capacitor, and so
on and so on. The back EMF created by the inductor is greater than B+ with the +ve
half of the cycle passing through the diode to charge a capacitor from where the
V_BOOST voltage is taken. The frequency of the switching signal LX decides the
duty cycle of the output wave and therefore the resultant voltage. V_BOOST is fed
back into the GCAP.
•V2 – Programmed to 2.775V, available whenever the radio is on and supplies most of
the logic side of the board. V2 is supplied out of GCAP II Pin J2 and can be
measured on either C939 or C941.
•V3 – Programmed to 2.003V to support the Whitecap, but does support the normal
2.75V logic output from the Whitecap, it originates from GCAP II Pin B5 and can be
measured on C909 or C910.
•VSIM1 – Used to support either 3V or 5V SIM cards. Will dynamically be set to 3V
upon power up, but if the card cannot be read then the SIM card is powered down and
an attempt to read the card at 5V is tried. VSIM1 can be measured on C905 and is
distributed from GCAP II Pin C6 (For further information, see SIM Card Operation).
LX
Output
B+
Fig 6.1

Motorola Internal Use 8
V2288 – Circuit Description
•VREF – Programmed as V2 i.e. 2.775 and provides a reference voltage for the
MAGIC IC, distributed from GCAP II Pin G9 and can be measured on C919.
•-5V – Used to drive display and –10V –Used for RF GSM / DCS selection signals
through Q160. Both voltages produced by V1 through U903 and U904.
•SR_VCC – Power Cut Circuit - Used to buffer the SRAM U702 voltage with a built
in soft reset within the unit’s software. The reason for this is to protect the user from
any accidental loss of power up to 0.5 seconds i.e. If the unit is knocked, causing a
slight battery contact bounce, the SR_VCC will, to the user, keep the unit running
normally, whilst internally the unit resets itself. During this loss of power the unit
takes it’s power from a 10µF capacitor C960 (This is a replacement for the RTC
battery and is charged by V2 and outputs to GCAP II Pin D6)
•V1_SW – See Deep Sleep Mode
7) Once the power source has been selected to power the phone on the PWR_SW must
be toggled low. This can be done by pressing the Power Key S500 to create
PWR_SW, which is supported by ON_2 (GCAP II Pin G5).
8) The unit will then follow on as in the sequence below:
RESET
SPI_CE
R/W
VCLK
DSC_EN
V1
UPLINK
5000 50 100 200 300250 350150 400 450
EPROM CE
SRAM VB&LB
GCAP
SPI_CE MAGIC
CLK SELECT
DOWNLINK
BFSR 1.7 after RESET, BCKLR at 1.6s

Motorola Internal Use 9
V2288 – Circuit Description
On initial power up, all the backlights (DS500 – DSDS11) will be on they are
supported from the signal ALRT_VCC (B+ through Q903) and switched by
BKLT_EN (Whitecap Pin K3) through Q907.
9) 13 MHz clock. On Power Up there are 2 different reference clocks produced.
Initially, as soon as power is applied to the MAGIC IC the crystal, Y200, supported
by the CRYSTAL_BASE (MAGIC Pin E1) will emit a 26MHz signal to the
MAGIC IC, which will internally be divided by 2 to give our external 13MHz clock.
This is then fed out of the MAGIC on Pin J6 (CLK_OUT) and distributed to
Whitecap Pin H10 (CLKIN), then from Whitecap to GCAP II Pin F5 as
GCAP_CLK. At the same time the 13MHz Varactor Diode CR248 is producing an
output. This output is controlled in the following way: The 26MHz from Y200 is
divided down to 200 kHz and fed to a phase comparator within the MAGIC. The
13MHz from CR248 is also divided down and fed in to the phase comparator, the
difference in phase produces an error voltage that is fed onto the cathode of the
Varactor CR248. Which regulates the output to a stable 13MHz clock. Once the
software is running and the logic side of the board has successfully powered up, the
CLK_SELECT signal from Whitecap Pin 1 is fed to MAGIC Pin G6. This in turn
then switches the Multiplexer from the output of Y200 to the CR248 output.
Logic: SIM Card Interface
1) Once powered up, the SIM card is interrogated. The SIM interface is part of the
Whitecap U800 and it supports both ‘synchronous’ (Prepay card) and asynchronous,
serial data transmission. Although the T2288 is programmed only for asynchronous.
VSIM1 (SIM_VCC) is originally programmed to 3V but if the card is 5V then the
SIM card will be powered down and VSIM1 will be reprogrammed to 5V. The signal
levels for in and out of the SIM are now required to be level shifted within GCAP II
U900 to 3V.these signals are:
13MHz
Phase 1
Multiplexer
Y200
26MHz
F
F
2
CR248
Phase
Detector
F
F
65
Phase 2
PLL Error Voltage
13MHz Output
to Whitecap
200kHz
F
F
130
MAGIC IC
U913

Motorola Internal Use 10
V2288 – Circuit Description
•Reset (Whitecap Pin E9 – RST0) in to GCAP II Pin K7 – LS1_IN_TG1A. This
signal is then level shifted to the required voltage and fed out to SIM Contacts J803
Pin 4 from Pin J7 - LS1_OUT_TG1A.
•Clock: This is a 3.25MHz signal from Whitecap Pin E9 – CLK0 Pin E7 to GCAP II
Pin G6 – LS2_IN. This signal is then level shifted to the required voltage and fed out
to SIM Contacts J803 Pin 6 from Pin F6 – LS2_OUT.
•SIM I/O – Data transmission to and from SIM card; for TX, from SIM card contact
SIM I/O Pin 5 through to GCAP II Pin J8 SIM I/O. Through level shifter to desired
voltage and out through Pin K10 (LS3_TX_PA_B+) to Whitecap Pin F3 DAT0_TX.
For RX data from Whitecap Pin B5 DATA0_RX to GCAP II, Pin H8 – LS3_RX
where the signal is level shifted to desired voltage and outputted on Pin J8 SIM I/O
to SIM contacts Pin 5 SIM I/O.
•SIM_PD – This signal is provided by the signal BATT_SENSE, activated by GCAP
II, BATTERY Pin F7. If there are no batteries present then the unit will not power
up. If batteries are present but the SIM card is either not inserted or faulty ‘CHECK
CARD ‘ will be displayed. The reason behind this is to prevent the extra cost of a
mechanical SIM presence detect switch and to prevent the SIM card being removed
whilst connected to Aux Power.
Logic: Charger Circuit
1) The charging circuit contains the new COVIC U960 (Charging and Over Voltage
Integrated Circuit). See COVIC Block Diagram. There are 2 charge modes either full
rate charge or Trickle current charge.
2) Trickle Rate is used to safely charge a dead battery up to its usable range or to top up
a charged battery.
3) Full Rate is used to charge a battery within its usable range.
4) For the circuit operation, as mentioned before the unit must first establish what type
of charger is connected. The charger plug is inserted into the Charger Jack J904. This
then results in IRQ4 (EXT B+_DET) being pulled low through Q961 (supported by
V2). This interrupt is sent to Whitecap Pin M3.
5) Once IRQ4 is received GCAP II Pin A1 then checks the MAN_TEST_AD DC
voltage level from Charger Jack Pin 4. The type of accessory connected will give a
different voltage level, dependant on the value of the MANTEST resistor within.
Some typical value are:
•Illegal Charger - MANTEST_AD > 2.4V (unit does not beep, charge or enable
backlights)
•CLA - MANTEST_AD < 2.4V but > 1.7V (Unit beeps, enables backlights and starts
to charge)
•Easy Install Handsfree Car Kit - MANTEST_AD < 1.7V but > 0.8V (Unit beeps,
enables backlights and starts to charge)
•AC Charger - MANTEST_AD < 0.8V (Unit beeps, enables backlights and starts to
charge)
NB* CHGR_SW MUST BE HIGH FOR MANTEST_AD TO BE READ.

Motorola Internal Use 11
V2288 – Circuit Description
6) When high CHGR_SW will limit the CLA or EIHF current output to 400mA, when
low MANTEST_AD the current output is limited to 900mA. The AC charger output
a current of approximately 350mA.
7) When the batteries are discharged and we turn the phone on, for the first second, full
rate charge is delivered, (this is due to the LX signal for V_BOOST being unstable
and therefore creating a power surge). This enables the phone to consume most of the
current from the charger but at the same time trickle charge the batteries up to their
usable voltage level. This is achieved by setting ENABLE 'high': from Whitecap Pin
L7 to COVIC Pin 5 and TRLK_SET 'low' (Whitecap Pin K4 to COVIC Pin 2). The
result of this is that the signal DRV, COVIC Pin 1 opens or closes the ‘gate’ of Q960
(very similar to the CHARGC function of other GCAP II products). The charge is
then fed through CR960 and out to dual-FET Q691 to charge the battery.
8) The circuit function describing when the batteries are in the usable range and normal
full rate charging is enabled is as above, however the extra current now charges the
batteries and the support voltage for the phone is taken directly from the batteries.
9) For High Rate trickle charging, again the operation is as above but TRKL_SET is set
‘high’ and ENABLE set ‘low’.
10)For Low rate Trickle charging TRKL_SET is set ‘low’ and ENABLE is set ‘low’
11)I Sense COVIC Pin 7 is used as a control for the charging DRV signal
12)The Over Voltage protection part of the circuit works in the following way:
13)The normal operating range of the batteries is between 3V through to 4.5V and an
over voltage condition would be classed at >5.1V. If a transient above this occurred
then this would be sensed by the current Sense resistor R960, and fed back into the
COVIC on Pin 7. This would drive ENABLE ‘low’, enabling Trickle charge mode
and reducing the current to the batteries to approximately 40mA.
14)If the transient is >6.1V then all charging stops. The over voltage comparator within
the COVIC has hysterisis built in and the capacitors will begin to discharge until the
voltage level is <5.1V at this point I_SENSE is reviewed again if still > 5.1V the unit
begins to trickle charge.
15)Instrumental in both these operations being carried out successfully is a 10µF
capacitor C970 (Situated near V_BOOST circuitry). As the transient occurs this
capacitor charges up, and reduces the voltage rise to the COVIC circuit, therefore
giving the COVIC more time to operate.
Logic: Deep Sleep Mode
1) Deep sleep mode is there to provide a facility to save battery life by intermittently
shutting off part of the PCB. This is achieved in the following way. The signal
STBY_DL is generated from Whitecap Pin F1, through a standby delay circuit
CR912 and U906 and onto Q834 and Q912. This has the effect respectively of:
2) Grounding VREF which makes MAGIC inoperable
3) Grounding V2 This switches off MAGIC, Front END IC and inhibits the Transmit
path through RF_V2
4) The shutdown is only for a fraction of a second and during that time the GCAP Clock
supports the logic side of the unit. The GCAP clock is generated by Y900, which

Motorola Internal Use 12
V2288 – Circuit Description
generates a 32.768MHz clock. This clock is output from Whitecap Pin C7 and fed
directly to Whitecap Pin P4. The clock is always monitored by Whitecap and should
it fail, the unit will no longer go into deep sleep mode.
Logic: Keypad Operation
1) The keypad works as a matrix supported V2. The signals inform the Whitecap upon a
key press by dropping the signal ‘low’. Below is the Key Matrix.
KBR0 KBR1 KBR2 KBR3 KBR4 KBC0 KBC1 KBC2 KBC3 KBC4 GND
KBR0 X8 7 X X # 0 6 5 X X
KBR1 8X1X X 9SCROLL
UP 3 2 X X
KBR2 7 1 X X X * 4 MAIL
BOX CLEAR XX
KBR3 X X X X X X X X X X VOL
DOWN
KBR4 X X X X X X X X X X FM
RADIO
KBC0 #9*X X X X SHIFT SCROLL
DOWN X X
KBC1 0SCROLL
UP 4X X X X X MENU X X
KBC2 6 3 MAIL
BOX X X SHIFT X X OK X X
KBC3 5 2 CLEAR X X SCROLL
DOWN MENU OK X X X
KBC4 X X X X X X X X X X VOL UP
GND X X X VOL
DOWN FM RADIO X X X X VOL UP X
FM Radio: FM IC
1) The FM IC is new to any Motorola product and is incorporated into the V2288
Modulus II (R). It is controlled by the FM data bus, consisting of:
•RW_AM_FM: WhiteCap output Pin M2. When low, WhiteCap signal
DATA_AM_FM (Whitecap Pin N1) is configured as an input to read data from the
FM IC. When high, DATA_AM_FM is configured as an output. The Whitecap shall
then send appropriate data to the FM IC.
•CLK_AM_FM: Whitecap output, Pin D2. This has two functions. 1st: To clock the
SPI bus data (100KHz). 2nd: Tells the MO_ST output of the FM IC U1001 Pin 26 to
indicate the mono/stereo or the tuned / un-tuned status.
•DATA_AM_FM: WhiteCap data in/output.
Refer to FM IC Block Diagram
Basic FM IC Operation:
Receiver function

Motorola Internal Use 13
V2288 – Circuit Description
1) The antenna signal FMin is routed from the headset ground line through the antenna
matching circuit into the tuned front end on Pin 47 of the U1001. The front end and
the FM Oscillator are tuned by the TUNE signal from the internal PLL circuit of the
IC.
2) The output signal from the tuned front-end and the FM Oscillator are routed into the
mixer stage. The output of the mixer is a 10.7 MHz IF signal; this is due to the FM
Oscillator running 10.7 MHz above the antenna signal.
3) The 10,7 MHz IF signal than passes the first IF filter and the first amplifier stage.
Behind the amplifier the signal path is split in two-signal path.
•The first supports the AM FM Indicator Stage that converts the IF signal to an
analogue voltage. This voltage is routed to Pin 22 of the U1001 as FM_RSSI. The
FM_RSSI level is corresponding to the receiver field strength.
•The second passes the signal to the 2nd IF filter and IF amplifier to feed into the
Demodulator stage.
4) The FM demodulator stage is using the 10.7 MHz crystal Y1003 to demodulate the IF
signal. The output supports three different parallel filter stages.
•The 1st is filtering the frequency-band from 0 to 15kHz that contains the L+R
information.
•The 2nd is filtering the frequency-band from 23 to 53kHz that contains the HELP
Signal.
•The 3rd is filtering the 19KHz pilot tone and is working to detect the pilot to support
the 38 kHz PLL/VCO stage.

Motorola Internal Use 14
V2288 – Circuit Description
See Fig 4.1 for a block diagram of the transmitter stage to see how the 3 different bands
are created.
5) The 38KHz PLL/VCO Stage needs to be phased because the amplified output is used
to demodulate the HELP SIGNAL into the original L-R signal. The 2nd output of the
amplifier is multiplied by 4 to get a 152KHz signal on Pin 26 of the U1001.
•This 152 kHz /MO_ST signal output is used, while phasing, as a control signal for
the test set. The tolerance should be +/- 2KHz.
•The MO_ST part of the signal works in conjunction with the CLK_AM_FM signal
to indicate the mono/stereo or tuned/not tuned status to the WhiteCap IC. (See table
below)
CLK_AM_FM MO_ST Result to WhiteCap PA5
LOW LOW stereo
LOW HIGH mono
HIGH LOW tuned
HIGH HIGH not tuned
6) The L-R signal out of the mixer and the L+R signal from the 0-15KHz filter stage are
feeding into the Decoder Matrix. Result of sum and difference are the left FM_L and
FIG 4.1
LR
L-R
MICROPHONE
STEREO
Modulator
Time and
Phase Correction
2f
f
19kHz
Pilot
kHz
U
0,03 510 15 20 25 30 35 40 45
19 38
50
55
L+R
L+R L-R L-R
Pilot
L+R
Help signal
Sum signal
Helpsingnal
38 kHz

Motorola Internal Use 15
V2288 – Circuit Description
right FM_R audio signal at Pins 15 and 16 respectively from the U1001. These are
then fed to the Stereo Audio IC U1500.
FM Radio: Stereo Audio IC U1500
The Stereo Audio IC (sometimes referred to as JAMS IC is basically a path selector for
audio and has 6 different modes of operation. For further information refer to the Stereo
Audio IC document.
The 6 modes of operation are:
1) Voice to Earpiece Speaker – As with other GCAP II products Speech audio will be
routed through the GCAP to SPKR + and –
2) Voice to Mono Headset – GCAP II SPKR+ will be disabled and the speech will be
routed from SPKR – to VC_R_IN2 to drive SPKR_R_OUT. Left Channel will be
muted.
3) Voice to Stereo headset – As above
4) FM Radio to Earpiece Speaker – Signal routed from FM IC to JAMS, from
VC_LOUT1 of JAMS the signal will be sent to the Aux Mic I/P of the GCAP II,
within the GCAP the Codec is bypassed and both SPKR + and –are enabled. – NOT
USED
5) FM Radio to Mono headset – R Channel of FM IC will be routed to VC_R_IN1,
which will drive SPKR_R_OUT; the left channel of JAMS will be muted.
6) FM Radio to Stereo Headset – As above but in this circumstance the left channel of
the FM IC and the JAMS will be enabled driving both SPKR_R_OUT and SPKR
L_OUT respectively.
7) IRQ2 is used as a master-detect (Active Low) JAMS DIV_REF buffer and
Comparator enabled.
8) IRQ3 determines headset type i.e. Stereo or Mono
Logic: Display
1) The display is a 96 X 64 pixel graphics display and is connected to the PCB via a 16
Pin ZIF connector J902. The LCD is controlled by:
•CS1 Chip Select which originates from DP_EN_L, Whitecap Pin A11 to J902 Pin 1.
•RES which originates from RESET, Whitecap Pin P2 to J902 Pin 2.
•R/W which originates from R_W, Whitecap Pin P2 to J902 Pin 2.
•7 Data Lines from Whitecap DO – D7
•The display is supported by –5V originating from U903 and can be measured on
C963 and V2
•Also the data / command signal AO from Whitecap Pin B12.

MODOLUS 3 / SHARK 8485933H03_P11
GSM Service Support 25.10.99
SCHEMATICS Rev. 1.0
MODULUS 3 / SHARK
Michael Hansen, Ray Collins, Ralf Lorenzen Page 3 of 4
REVISIONS

MODOLUS 3 / SHARK 8485933H03_P11
GSM Service Support 25.10.99
SCHEMATICS Rev. 1.0
MODULUS 3 / SHARK
Michael Hansen, Ray Collins, Ralf Lorenzen Page 3 of 4
REVISIONS

MODOLUS 3 / SHARK 8485933H03_P11
GSM Service Support 25.10.99
SCHEMATICS Rev. 1.0
MODULUS 3 / SHARK
Michael Hansen, Ray Collins, Ralf Lorenzen Page 2 of 4
REVISIONS

GSM Service Support 25.10.99
SCHEMATICS Rev. 1.0
MODULUS 3 / SHARK
Michael Hansen, Ray Collins, Ralf Lorenzen Page 4of 4
REVISIONS
MODOLUS 3 / SHARK 8485933H03_P11

H
GSM SERVICE SUPPORT GROUP 06.01.00
LEVEL 3 SIGNAL FLOW Rev. 1.1
Moddulus III (Shark)
Michael Hansen, Ralf Lorenzen, Ray Collins Page 1
REVISIONS
Dualband Modulus III (Shark) 8485933H04_P13
SH5
REG_B+ RF_V2 DCS_TX_VCO GSM_TX_VCO B+ SF_OUT RF_V2 RF_V1 STBY_DL V1 -5V
B+ TX_EN B+ VA VB V2 V1_SW ENABLE PWR_ON ISENSE EXT_B+ TRKL_SET SR_VCC V_BOOST1
RX_EN VA RF_V2 SF_OUT GSM_TX_VCO DCS_SEL GSM_SEL TXVCO_EN GSM_SEL DCS_TX_VCO PAC_EN
RVCO_250 GP04 SF_OUT TXVCO_EN TX_GSM_*DCS TXVCO_EN -10V DCS_SEL RX_DCS_*GSM RVCO_250 GSM_SEL TX_EN V1
SH7
SH6 SH8
SH4
SH9
A
A
B
B
E
F
E
F
SH1
SH2
SH2
TX VCO IC
900-1785MHz
IPA
RF CONN.
PAC
26MHz
MAGIC
FM RADIO
SRAM
WHITE CAP
FLASH/EEPROM
AUDIO JAMS IC
SIM CONN
GCAP
COVIC
IC
POWER JACK
32kHz
FM RADIO
FRONTEND
IC
RX VCO IC
DISPLAY CONN
HEADSETJACK
1800MHz
1900MHz
900MHz
900MHz
400MHz
IF FILTER
TP878 TP864
TP875 TP877
TP866 TP865
TP1000 TP1001
TP841
TP1006
TP825
TP209
TP831
TP826
TP822
TP824
TP1004 TP1003
TP1002
TP205
TP809
TP206 TP818
TP814
TP815
TP816
TP812 TP813
TP817
TP811
TP810
TP828
TP823
TP829
TP830
TP208
TP1005
TP835
TP821
13
18
20
23 3 4
9
12
1
4
27
1
6
A7
A3
A1
B1
E2
E1
J6
PRE_IN
PRSC-IN
CP_TX
CP_RX
XTAL_EMIT
XTAL_BASE
CLK_OUT
TP200
U200
ALERT PADS
MIC CONN
J502
J506 J503
J505
SPKR PAD +
C D
C
D
J9
ALRT_VCC
K9 H7 H6 J2
ALRTOUT
SPKR+
SPKR-
MICIN-
H10CLKIN
B7GCAP_CLK
F5CLK_IN
F7
SCLK_OUT
G9
G8
SDFS
SDRX
BDR
BFSR
BCLKR
B3
B6 D4 A3
B4
BDX EFSR BDR
BCLKR BCLKX
TX_CLK
G7
SD_TX
J2
BDX
BDX
BCLKX
BCLKX
TP
TP200 MAGIC 13MHz
TP205 DX1
TP206 MQSPI_CLK1
TP208 DM_CS
TP209 TX_KEY
TP809 GND
TP810 EMU1
TP811 TMS
TP812 TDI
TP813 EMU0
TP814 V2
TP815 TD0
TP816 TRST*
TP817 TCK
TP818 VCC_BATT
TP821 PWR_SW
TP822 CE1
TP823 GCAP_CLK
TP824 CE0
TP825 CE2
TP826 CE3
TP828 VCLK
TP829 VFSRX
TP830 VDX
TP831 VDR
TP835 DR2
TP841 RX_ACQ
TP864 DCS_EN
TP865 EXT_B+
TP866 GND
TP875 ON*
TP877 UPLINK
TP878 DOWNLINK
TP1000 152kHz
TP1001 FM_RSSI
TP1002 RW_AM_FM
TP1003 DATA_AM_FM
TP1004 CLK_AM_FM
TP1005 FM_R
TP1006 FM_L
RX SIGNAL PATH
TX SIGNAL PATH
RX VCO SIGNAL PATH
TUNING VOLTAGES
13 MHz REFERENCE CLOCK
TP x TESTPOINT
from Magic
from Magic
-10V
-5V
VB TX_EN
SW_VCC RVCO_250 RX_DCS_*GSM
RX ANTENNA SIGNAL
AMPLIFIED IF 400MHz
RX SPEAKER LINE +
RX SPEAKER LINE -
RX VCO TUNING VOLTAGE
RX VCO FEEDBACK LINE TO MAGIC
HEADSET_L
FMin
FMin
2nd 10,7MHz FILTER IN
2nd 10,7MHz FILTER OUT
FM AUDIO L
FM AUDIO R
A
B
C
D
E
F
J902 DISPLAY
CONN
1/CS1
2/RES
3Data/Command
4R_W
5D0
6D1
7D2
8D3
9D4
10 D5
11 D6
12 D7
13 2,75V
14 GND
15 Negative Supply
16 NC
17 GND
18 GND
J803 SIM CONN
1GND
2SIM Vcc
3VPP
4RESET
5SIM I/O
6CLK
3
8
6
3
SPKR PAD -
12
34
56
BATT_THERM_AD
VREF
to U900
V1 VSIM1 V3 VSIM1
G
G
G
FMin
HEADSET_L
H I
1
13 24
25
37
48 47 43 40 38 36
11
12 1516
IK J
K J
LM
L
M
1
10
11 20
9
12
FM_L
FM_R
H
I
J
K
L
M