Motorola Freescale Semiconductor M-Core MMC2001 User manual

M•CORE™
MMC2001
Reference Manual
Revision 1.1
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The M•CORE name and logotype and the OnCE name are trademarks of Motorola, Inc.
© Motorola, Inc. 1998
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REFERENCE MANUAL iii
Conventions
This document uses the following notational conventions:
mnemonics Instruction mnemonics are shown in lowercase bold
0x0F Hexadecimal numbers
0b0011 Binary numbers
Nomenclature
Logic level one is the voltage that corresponds to a Boolean true (1) state.
Logic level zero is the voltage that corresponds to a Boolean false (0) state.
To set a bit or bits means to establish logic level one on the bit or bits.
To clear a bit or bits means to establish logic level zero on the bit or bits.
LSB means least significant bit or bits. MSB means most significant bit or bits. Refer-
ences to low and high bytes are spelled out.
A signal is asserted when it is in its active or true state, regardless of whether that
state is represented by a high or low voltage. A signal is negated when it is in its inac-
tive or false state.
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MMC2001 MOTOROLA
REFERENCE MANUAL v
TABLE OF CONTENTS
Paragraph Title Page
SECTION 1
INTRODUCTION
SECTION 2
INTEGER CPU
2.1 M•CORE Overview ..........................................................................................2-1
2.2 Features...........................................................................................................2-2
2.3 Microarchitecture Summary.............................................................................2-2
2.4 Programming Model.........................................................................................2-3
2.5 Data Format Summary.....................................................................................2-5
2.6 Operand Addressing Capabilities.....................................................................2-6
2.7 Instruction Set Overview..................................................................................2-6
2.8 M•CORE Bus Interface....................................................................................2-8
2.8.1 Bus Characteristics .......................................................................................2-8
2.8.2 Bus Signals ...................................................................................................2-9
2.8.3 Signal Descriptions......................................................................................2-10
2.8.4 Bus Operation .............................................................................................2-11
2.8.5 Processor Instruction/Data Transfers..........................................................2-13
2.8.6 Bus Exception Cycles..................................................................................2-14
SECTION 3
SYSTEM MEMORY MAP
3.1 Overview..........................................................................................................3-1
3.2 Peripheral Module Address Allocation.............................................................3-1
3.3 Peripheral Module Interface Operation............................................................3-2
3.4 Peripheral Module Address Assignment..........................................................3-2
SECTION 4
SIGNAL DESCRIPTIONS
4.1 Overview..........................................................................................................4-1
4.2 Signal Index .....................................................................................................4-2
4.3 Bus Signals......................................................................................................4-4
4.3.1 Address Bus (ADDR[19:0]) ...........................................................................4-4
4.3.2 Data Bus (DATA[15:0])..................................................................................4-4
4.3.3 Output Enable (OE).......................................................................................4-4
4.3.4 Read/Write Enable (R/W)..............................................................................4-4
4.3.5 Enable Byte 1 (EB1)......................................................................................4-4
4.3.6 Enable Byte 0 (EB0)......................................................................................4-4
4.3.7 Chip Selects (CS3, CS[2:0])..........................................................................4-4
4.3.8 Internal ROM Disable (MOD) ........................................................................4-4
4.4 Exception Control Signals................................................................................4-4
4.4.1 Reset (RSTIN)...............................................................................................4-4
4.4.2 Low Voltage Reset (LVRSTIN)......................................................................4-5
4.4.3 Reset Out (RSTOUT)....................................................................................4-5
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4.5 Clock Signals ...................................................................................................4-5
4.5.1 Crystal Oscillator (XOSC, EXOSC)...............................................................4-5
4.5.2 Clock Input (CLKIN) ......................................................................................4-5
4.5.3 Clock Output (CLKOUT)................................................................................4-5
4.6 Debug and Emulation Support Signals............................................................4-5
4.6.1 Test Clock (TCK)...........................................................................................4-5
4.6.2 Test Data Input (TDI).....................................................................................4-5
4.6.3 Test Data Output (TDO)................................................................................4-6
4.6.4 Test Mode Select (TMS) ...............................................................................4-6
4.6.5 Test Reset (TRST)........................................................................................4-6
4.6.6 Debug Event (DE).........................................................................................4-6
4.6.7 Factory Test Mode (TEST)............................................................................4-6
4.7 External Interrupts/GPIO Signals.....................................................................4-6
4.7.1 External Interrupts 7 – 0 (INT[7:0])................................................................4-6
4.8 Keypad Signals................................................................................................4-7
4.8.1 Column Strobes (COL[7:0])...........................................................................4-7
4.8.2 Row Senses (ROW[7:0])...............................................................................4-7
4.9 UART Module Signals......................................................................................4-7
4.9.1 Receive Data (RxD0, RxD1) .........................................................................4-7
4.9.2 Transmit Data (TxD0, TxD1).........................................................................4-7
4.9.3 Clear to Send (CTS0)....................................................................................4-7
4.9.4 Request to Send (RTS0)...............................................................................4-8
4.10 Serial Peripheral Interface Module Signals......................................................4-8
4.10.1 SPI Data Master Out/Slave In (SPI_MOSI)...................................................4-8
4.10.2 SPI Data Master In/Slave Out (SPI_MISO)...................................................4-8
4.10.3 SPI Serial Clock (SPI_CLK)..........................................................................4-8
4.10.4 SPI Enable (SPI _EN)...................................................................................4-8
4.10.5 SPI General-Purpose Output (SPI _GP).......................................................4-8
4.11 Pulse Width Modulator Signals........................................................................4-8
4.11.1 PWM[5:0].......................................................................................................4-8
4.12 Power and Ground Pins...................................................................................4-9
4.12.1 Positive Supply (VDD)....................................................................................4-9
4.12.2 Ground (GND)...............................................................................................4-9
4.12.3 Standby Battery Power (VBATT).....................................................................4-9
4.12.4 Standby Power Filter (VSTBY)........................................................................4-9
SECTION 5
ROM MODULE
5.1 Overview..........................................................................................................5-1
5.2 Functional Description......................................................................................5-1
5.3 Applications......................................................................................................5-2
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SECTION 6
STATIC RAM MODULE
6.1 Overview..........................................................................................................6-1
6.2 Functional Description......................................................................................6-1
SECTION 7
EXTERNAL INTERFACE MODULE
7.1 Overview..........................................................................................................7-1
7.2 Signals .............................................................................................................7-1
7.2.1 Address Bus..................................................................................................7-1
7.2.2 Data Bus........................................................................................................7-2
7.2.3 Read/Write ....................................................................................................7-2
7.2.4 Control Signals..............................................................................................7-2
7.2.5 Boot Mode.....................................................................................................7-2
7.2.6 Chip Select Outputs ......................................................................................7-2
7.3 Chip-Select Address Range.............................................................................7-3
7.4 EIM Interface Example.....................................................................................7-3
7.5 EIM Functionality..............................................................................................7-4
7.5.1 Configurable Bus Sizing................................................................................7-4
7.5.2 External Boot ROM Control...........................................................................7-6
7.5.3 Programmable Output Generation................................................................7-6
7.5.4 Bus Watchdog Operation..............................................................................7-6
7.5.5 Error Conditions ............................................................................................7-6
7.5.6 Show Cycles..................................................................................................7-7
7.6 EIM Programming Model .................................................................................7-7
7.6.1 Chip-Select Control Registers.......................................................................7-7
7.7 EIM Configuration Register............................................................................7-11
7.8 External Bus Timing Diagrams.......................................................................7-13
SECTION 8
CLOCK MODULE AND LOW-POWER MODES
8.1 Overview..........................................................................................................8-1
8.2 Low-Power Modes ...........................................................................................8-4
8.2.1 CPU Core Low-Power Modes.......................................................................8-4
8.2.2 Peripheral Behavior in Low-Power Modes....................................................8-5
8.2.3 General Low-Power Features .......................................................................8-7
SECTION 9
TIMER/RESET MODULE
9.1 Overview..........................................................................................................9-1
9.2 Timer/Reset Programming Model....................................................................9-1
9.3 Reset Operation...............................................................................................9-2
9.3.1 Reset Pins.....................................................................................................9-2
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9.3.2 Reset Sources...............................................................................................9-2
9.3.3 Reset Sequence............................................................................................9-3
9.3.4 Reset Source/Chip Configuration Register (RSCR)......................................9-3
9.4 Time-of-Day Timer...........................................................................................9-4
9.4.1 TOD Operation..............................................................................................9-5
9.4.2 TOD in Low-Power Modes............................................................................9-5
9.4.3 Time-of-Day Control/Status Register (TODCSR)..........................................9-5
9.4.4 TOD Seconds Register (TODSR) .................................................................9-6
9.4.5 TOD Fraction Register (TODFR)...................................................................9-6
9.4.6 TOD Seconds Alarm Register (TODSAR).....................................................9-7
9.4.7 TOD Fraction Alarm Register (TODFAR)......................................................9-7
9.5 Watchdog Timer...............................................................................................9-8
9.5.1 Watchdog Timing Specifications...................................................................9-9
9.5.2 Watchdog Timer after Reset .........................................................................9-9
9.5.3 Watchdog Timer Service Operation..............................................................9-9
9.5.4 Watchdog Timer in Wait Mode......................................................................9-9
9.5.5 Watchdog Timer in Doze Mode.....................................................................9-9
9.5.6 Watchdog Timer in Stop Mode......................................................................9-9
9.5.7 Watchdog Timer in Debug Mode.................................................................9-10
9.5.8 Watchdog Timer Programming Model.........................................................9-10
9.6 Interval Timer (PIT)........................................................................................9-11
9.6.1 PIT Operation..............................................................................................9-12
9.6.2 PIT as a “Set-and-Forget” Timer.................................................................9-12
9.6.3 PIT as a “Free-Running” Timer ...................................................................9-13
9.6.4 Interval Timer Registers ..............................................................................9-13
9.6.5 PIT Control/Status Register (ITCSR) ..........................................................9-14
9.6.6 PIT Data Register (ITDR)............................................................................9-15
9.6.7 PIT Alternate Data Register (ITADR) ..........................................................9-16
9.6.8 PIT in Low-Power Modes............................................................................9-16
9.6.9 PIT in Debug Mode .....................................................................................9-16
SECTION 10
INTERRUPT CONTROLLER
10.1 Overview........................................................................................................10-1
10.2 Interrupt Controller Programming Model........................................................10-2
10.2.1 Interrupt Source Register (INTSRC) ...........................................................10-2
10.2.2 Normal Interrupt Enable Register (NIER)....................................................10-3
10.2.3 Fast Interrupt Enable Register (FIER).........................................................10-3
10.2.4 Normal Interrupt Pending Register (NIPND)...............................................10-4
10.2.5 Fast Interrupt Pending Register (FIPND)....................................................10-5
10.2.6 Interrupt Request Input Assignments..........................................................10-5
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TABLE OF CONTENTS
Paragraph Title Page
SECTION 11
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE
11.1 Overview........................................................................................................11-1
11.2 UART Signals.................................................................................................11-2
11.2.1 RTS — Request to Send (UART0)..............................................................11-2
11.2.2 CTS — Clear to Send (UART0) ..................................................................11-2
11.2.3 TXD — UART Transmit...............................................................................11-3
11.2.4 RXD — UART Receive ...............................................................................11-3
11.3 Sub-Block Description....................................................................................11-3
11.3.1 Transmitter..................................................................................................11-3
11.3.2 Receiver......................................................................................................11-3
11.3.3 Infrared Interface.........................................................................................11-4
11.3.4 16x Bit Clock Generator..............................................................................11-4
11.3.5 General UART Definitions...........................................................................11-4
11.4 UART Programming Model............................................................................11-5
11.4.1 UART Receive Register (URX)...................................................................11-7
11.4.2 UART Transmitter Register (UTX) ..............................................................11-8
11.4.3 UART Control Register 1 (UCR1) ...............................................................11-9
11.4.4 UART Control Register 2 (UCR2) .............................................................11-11
11.4.5 UART BRG Register (UBRGR).................................................................11-13
11.4.6 UART Status Register (USR)...................................................................11-14
11.4.7 UART Test Register (UTS)........................................................................11-15
11.5 GPIO Pins and Registers.............................................................................11-16
11.5.1 UART Port Control Register (UPCR) ........................................................11-16
11.5.2 UART Data Direction Register (UDDR).....................................................11-16
11.5.3 UART Port Data Register (UPDR) ............................................................11-17
11.6 Data Sampling Technique on the Receiver..................................................11-17
11.7 UART Operation in Low-Power System Modes...........................................11-23
11.8 UART Operation in System Debug Mode....................................................11-24
SECTION 12
INTERVAL MODE SERIAL PERIPHERAL INTERFACE
12.1 Overview........................................................................................................12-1
12.2 Operation .......................................................................................................12-1
12.2.1 Manual (Master) Mode................................................................................12-2
12.2.2 Interval (Master) Mode................................................................................12-3
12.2.3 Slave Mode .................................................................................................12-3
12.3 Signal Descriptions ........................................................................................12-3
12.3.1 SPI_MISO (Master In, Slave Out) ...............................................................12-3
12.3.2 SPI_MOSI (Master Out, Slave In)...............................................................12-4
12.3.3 SPI_EN........................................................................................................12-4
12.3.4 SPI_CLK......................................................................................................12-4
12.3.5 SPI_GP .......................................................................................................12-4
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12.4 ISPI Programming Model...............................................................................12-4
12.4.1 ISPI Data Register.......................................................................................12-5
12.4.2 ISPI Control Register...................................................................................12-5
12.4.3 ISPI Interval Control Register......................................................................12-8
12.4.4 ISPI Status Register....................................................................................12-8
12.5 ISPI Programming Examples.........................................................................12-9
12.5.1 Manual Mode Example................................................................................12-9
12.5.2 Slave Mode Example ................................................................................12-10
12.5.3 Interval Model Example.............................................................................12-10
12.6 ISPI Operation in Low-Power System Modes..............................................12-11
12.7 ISPI Operation in System Debug Mode.......................................................12-11
SECTION 13
EXTERNAL INTERRUPTS/GPIO (EDGE PORT)
13.1 Overview........................................................................................................13-1
13.2 Interrupt/General-Purpose I/O Pin Descriptions (INT[0:7]) ............................13-1
13.3 Edge Port Programming Model......................................................................13-2
13.3.1 Edge Port Pin Assignment Register (EPPAR) ............................................13-2
13.3.2 Edge Port Data Direction Register (EPDDR)..............................................13-3
13.3.3 Edge Port Data Register (EPDR)................................................................13-3
13.3.4 Edge Port Flag Register (EPFR).................................................................13-4
SECTION 14
KEYPAD PORT
14.1 Overview........................................................................................................14-1
14.2 KPP Pin Description.......................................................................................14-2
14.2.1 Input Pins ....................................................................................................14-2
14.2.2 Output Pins..................................................................................................14-2
14.3 KPP Programming Model...............................................................................14-2
14.3.1 Keypad Control Register (KPCR)................................................................14-2
14.3.2 Keypad Status Register (KPSR) .................................................................14-3
14.3.3 Keypad Data Direction Register (KDDR) ....................................................14-5
14.3.4 Keypad Data Register (KPDR)....................................................................14-5
14.4 Keypad Operation..........................................................................................14-6
14.4.1 Keypad Matrix Construction........................................................................14-6
14.4.2 Keypad Port Configuration..........................................................................14-6
14.4.3 Keypad Matrix Scanning .............................................................................14-6
14.4.4 Keypad Standby.........................................................................................14-7
14.4.5 Glitch Suppression on Keypad Inputs.........................................................14-7
14.4.6 Multiple Key Closures..................................................................................14-8
14.4.7 Typical Keypad Configuration and Scanning Sequence.............................14-9
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SECTION 15
PULSE WIDTH MODULATOR
15.1 Overview........................................................................................................15-1
15.2 PWM Programming Model.............................................................................15-2
15.2.1 PWM Control Register.................................................................................15-4
15.2.2 PWM Period Register..................................................................................15-6
15.2.3 PWM Width Register...................................................................................15-7
15.2.4 PWM Counter Register ...............................................................................15-7
15.3 PWM Operating Range..................................................................................15-8
15.4 PWM Operation in Low-Power System Modes..............................................15-8
SECTION 16
OnCE™ DEBUG MODULE
16.1 Overview........................................................................................................16-1
16.2 Operation .......................................................................................................16-1
16.3 OnCE Pins .....................................................................................................16-3
16.3.1 Debug Serial Input (TDI) .............................................................................16-3
16.3.2 Debug Serial Clock (TCK)...........................................................................16-3
16.3.3 Debug Serial Output (TDO).........................................................................16-3
16.3.4 Debug Mode Select (TMS)..........................................................................16-3
16.3.5 Test Reset (TRST)......................................................................................16-4
16.3.6 Debug Event (DE).......................................................................................16-4
16.4 OnCE Controller and Serial Interface.............................................................16-4
16.5 OnCE Interface Signals..................................................................................16-5
16.5.1 Internal Debug Request Input (IDR)............................................................16-5
16.5.2 CPU Debug Request (DBGRQ)..................................................................16-5
16.5.3 CPU Debug Acknowledge (DBGACK)........................................................16-5
16.5.4 CPU Breakpoint Request (BRKRQ)............................................................16-5
16.5.5 CPU Address, Attributes (ADDR, ATTR) ....................................................16-5
16.5.6 CPU Status (PSTAT)...................................................................................16-5
16.5.7 OnCE Debug Output (DEBUG)...................................................................16-6
16.6 OnCE Controller Registers.............................................................................16-6
16.6.1 OnCE Command Register (OCMR)............................................................16-6
16.6.2 OnCE Control Register (OCR) ....................................................................16-8
16.6.3 OnCE Status Register (OSR)....................................................................16-11
16.7 OnCE Decoder (ODEC)...............................................................................16-12
16.8 Memory Breakpoint Logic ............................................................................16-12
16.8.1 Memory Address Latch (MAL)...................................................................16-13
16.8.2 Breakpoint Address Base Registers (BABA, BABB).................................16-14
16.8.3 Breakpoint Address Mask Registers (BAMA, BAMB) ...............................16-14
16.8.4 Breakpoint Address Comparators.............................................................16-14
16.8.5 Memory Breakpoint Counters (MBCA, MBCB) .........................................16-14
16.9 OnCE Trace Logic........................................................................................16-14
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16.9.1 Trace Counter (OTC) ................................................................................16-15
16.9.2 Trace Operation ........................................................................................16-15
16.10 Methods of Entering Debug Mode ...............................................................16-16
16.10.1 Debug Request During RESET.................................................................16-16
16.10.2 Debug Request During Normal Activity.....................................................16-16
16.10.3 Debug Request During Stop, Doze, or Wait Mode....................................16-16
16.10.4 Software Request During Normal Activity .................................................16-16
16.10.5 Enabling OnCE Trace Mode .....................................................................16-16
16.10.6 Enabling OnCE Memory Breakpoints........................................................16-17
16.11 Pipeline Information and Write-Back Bus Register......................................16-17
16.11.1 Program Counter Register (PC)................................................................16-18
16.11.2 Instruction Register (IR) ............................................................................16-18
16.11.3 Control State Register (CTL).....................................................................16-18
16.11.4 Write-Back Bus Register (WBBR).............................................................16-19
16.11.5 Processor Status Register (PSR)..............................................................16-19
16.12 Instruction Address FIFO Buffer (PC FIFO).................................................16-20
16.12.1 Reserved Test Control Registers (Reserved, MEM_BIST, FTCR, LSRL) 16-21
16.13 Serial Protocol Description...........................................................................16-21
16.13.1 OnCE Commands.....................................................................................16-21
16.14 Target Site Debug System Requirements....................................................16-21
16.15 Interface Connector For JTAG/OnCE Serial Port ........................................16-22
APPENDIX A
ELECTRICAL CHARACTERISTICS
A.1 Maximum Ratings ............................................................................................A-1
A.2 DC Electrical Specifications.............................................................................A-1
A.3 Clock Input Specifications................................................................................A-2
A.4 AC Electrical Specifications .............................................................................A-2
A.4.1 Reset, MOD Timing Specifications..............................................................A-2
A.4.2 External Interrupt Timing Specifications......................................................A-3
A.4.3 EIM Timing Specifications ...........................................................................A-4
A.4.4 ISPI Timing Specifications...........................................................................A-6
A.4.5 OnCE Timing Specifications........................................................................A-9
APPENDIX B
PACKAGING AND PIN ASSIGNMENTS
B.1 Overview..........................................................................................................B-1
APPENDIX C
PROGRAMMING REFERENCE
C.1 Peripheral Module Address Assignment..........................................................C-1
C.2 Interrupt Controller Programming Model..........................................................C-2
C.2.1 Interrupt Source Register (INTSRC)............................................................C-2
C.2.2 Normal Interrupt Enable Register (NIER) ....................................................C-2
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C.2.3 Fast Interrupt Enable Register (FIER).........................................................C-3
C.2.4 Normal Interrupt Pending Register (NIPND)................................................C-4
C.2.5 Fast Interrupt Pending Register (FIPND).....................................................C-4
C.3 Timer/Reset Programming Model....................................................................C-5
C.3.1 Reset Source/Chip Configuration Register (RSCR)....................................C-5
C.3.2 Time-of-Day Control/Status Register (TODCSR)........................................C-7
C.3.3 TOD Seconds Register (TODSR)................................................................C-7
C.3.4 TOD Fraction Register (TODFR).................................................................C-8
C.3.5 TOD Seconds Alarm Register (TODSAR)...................................................C-8
C.3.6 TOD Fraction Alarm Register (TODFAR)....................................................C-9
C.3.7 Watchdog Control Register (WCR)..............................................................C-9
C.3.8 Watchdog Service Register (WSR) ...........................................................C-10
C.3.9 PIT Control/Status Register (ITCSR).........................................................C-11
C.3.10 PIT Data Register (ITDR) ..........................................................................C-12
C.3.11 PIT Alternate Data Register (ITADR).........................................................C-13
C.4 KPP Programming Model...............................................................................C-13
C.4.1 Keypad Control Register (KPCR)..............................................................C-14
C.4.2 Keypad Status Register (KPSR)................................................................C-14
C.4.3 Keypad Data Direction Register (KDDR)...................................................C-15
C.4.4 Keypad Data Register (KPDR)..................................................................C-15
C.5 EIM Programming Model ...............................................................................C-16
C.5.1 Chip-Select Control Registers ...................................................................C-16
C.5.2 EIM Configuration Register........................................................................C-20
C.6 PWM Module..................................................................................................C-22
C.6.1 PWM Control Register...............................................................................C-23
C.6.2 PWM Period Register................................................................................C-25
C.6.3 PWM Width Register .................................................................................C-26
C.6.4 PWM Counter Register..............................................................................C-27
C.7 Edge Port Programming Model......................................................................C-27
C.7.1 Edge Port Pin Assignment Register (EPPAR)...........................................C-27
C.7.2 Edge Port Data Direction Register (EPDDR).............................................C-28
C.7.3 Edge Port Data Register (EPDR) ..............................................................C-29
C.7.4 Edge Port Flag Register (EPFR) ...............................................................C-29
C.8 ISPI Programming Model...............................................................................C-30
C.8.1 ISPI Send/Receive Data Register..............................................................C-30
C.8.2 ISPI Control Register.................................................................................C-31
C.8.3 ISPI Interval Control Register....................................................................C-33
C.8.4 ISPI Status Register ..................................................................................C-34
C.9 UART Programming Model............................................................................C-34
C.9.1 UART Receive Register (URX)..................................................................C-36
C.9.2 UART Transmit Register (UTX).................................................................C-37
C.9.3 UART Control Register 1 (UCR1)..............................................................C-38
C.9.4 UART Control Register 2 (UCR2)..............................................................C-40
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xiv REFERENCE MANUAL
TABLE OF CONTENTS
Paragraph Title Page
C.9.5 UART BRG Register (UBRGR) .................................................................C-42
C.9.6 UART Status Register (USR) ...................................................................C-42
C.9.7 UART Test Register (UTSR) .....................................................................C-43
C.9.8 UART Port Control Register (UPCR).........................................................C-44
C.9.9 UART Data Direction Register (UDDR).....................................................C-45
C.9.10 UART Port Data Register (UPDR).............................................................C-45
C.10 OnCE Registers.............................................................................................C-46
C.10.1 OnCE Command Register (OCMR)...........................................................C-46
C.10.2 OnCE Control Register (OCR)...................................................................C-47
C.10.3 OnCE Status Register (OSR)....................................................................C-50
C.10.4 Memory Address Latch (MAL)...................................................................C-51
C.10.5 Breakpoint Address Base Registers (BABA, BABB) .................................C-51
C.10.6 Breakpoint Address Mask Registers (BAMA, BAMB)................................C-51
C.10.7 Breakpoint Address Comparators..............................................................C-51
C.10.8 Memory Breakpoint Counters (MBCA, MBCB)..........................................C-51
C.10.9 Program Counter Register (PC) ................................................................C-51
C.10.10 Instruction Register (IR).............................................................................C-52
C.10.11 Control State Register (CTL).....................................................................C-52
C.10.12 Write-Back Bus Register (WBBR) .............................................................C-53
C.10.13 Processor Status Register (PSR)..............................................................C-53
C.10.14 Reserved Test Control Registers (Reserved, MEM_BIST, FTCR, LSRL).C-53
INDEX
RECORD OF CHANGES
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MMC2001 MOTOROLA
REFERENCE MANUAL xv
LIST OF ILLUSTRATIONS
Paragraph Title Page
1-1 MMC2001 Block Diagram................................................................................1-2
2-1 Programming Model.........................................................................................2-4
2-2 Data Organization in Memory ..........................................................................2-5
2-3 Data Organization in Registers........................................................................2-5
2-4 Signal Relationships to Clocks.........................................................................2-9
2-5 M•CORE Bus Signals ....................................................................................2-10
2-6 External Multiplexer Connections...................................................................2-13
4-1 Functional Signal Groups.................................................................................4-1
7-1 EIM Block Diagram ..........................................................................................7-1
7-2 EIM Interface to Memory and Peripherals........................................................7-4
7-3 CS0 Control Register.......................................................................................7-7
7-4 CS1, CS2, CS3 Control Registers ...................................................................7-8
7-5 EIM Configuration Register............................................................................7-11
7-6 Read Memory Access (CSA = 0, WSC = 1)...................................................7-14
7-7 Write Memory Access (CSA = 0, WSC = 1, WWS = 0) .................................7-15
7-8 Word Read Access from Halfword Width Memory.........................................7-16
7-9 Word Write Access to Halfword Width Memory.............................................7-17
7-10 Write after Read Memory Access (CSA = 0, WSC = 2, EDC = 0) .................7-18
7-11 Write after Read Memory Access (CSA = 0, WSC = 1, EDC = 1) .................7-19
7-12 Peripheral Read Access (CSA = 1, WSC = 5)...............................................7-20
7-13 Peripheral Write Access (CSA = 1, WSC = 5) ...............................................7-21
7-14 Read and Write Fast Memory Access (CSA = 0, WSC = 0, WWS = 0).........7-22
8-1 MMC2001 Clock Module..................................................................................8-3
9-1 Reset Functional Block Diagram......................................................................9-2
9-2 Reset Source Register.....................................................................................9-3
9-3 TOD Block Diagram.........................................................................................9-4
9-4 TOD Control/Status Register ...........................................................................9-5
9-5 TOD Seconds Register....................................................................................9-6
9-6 TOD Fraction Register.....................................................................................9-7
9-7 TOD Seconds Alarm Register..........................................................................9-7
9-8 TOD Fraction Alarm Register...........................................................................9-8
9-9 Watchdog Timer Block Diagram ......................................................................9-8
9-10 Watchdog Control Register............................................................................9-10
9-11 Watchdog Service Register............................................................................9-11
9-12 PIT Block Diagram.........................................................................................9-12
9-13 Starting a Count from an Off State.................................................................9-12
9-14 Counter Reloading from the Modulus Latch...................................................9-13
9-15 Counter in Free-Running Mode......................................................................9-13
9-16 PIT Control and Status Register ....................................................................9-14
9-17 PIT Data Register...........................................................................................9-15
9-18 PIT Alternate Data Register...........................................................................9-16
10-1 Interrupt Source Register...............................................................................10-2
10-2 Normal Interrupt Enable Register...................................................................10-3
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LIST OF ILLUSTRATIONS
Paragraph Title Page
10-3 Fast Interrupt Enable Register.......................................................................10-3
10-4 Normal Interrupt Pending Register.................................................................10-4
10-5 Fast Interrupt Pending Register.....................................................................10-5
11-1 UART Channel Block Diagram.......................................................................11-2
11-2 UART Receive Register.................................................................................11-7
11-3 UART Transmitter Register............................................................................11-9
11-4 UART Control Register 1 ...............................................................................11-9
11-5 UART Control Register 2 .............................................................................11-12
11-6 UART BRG Register....................................................................................11-13
11-7 UART Status Register..................................................................................11-14
11-8 UART Test Register.....................................................................................11-15
11-9 UART Port Control Register.........................................................................11-16
11-10 UART Data Direction Register.....................................................................11-16
11-11 UART Port Data Register.............................................................................11-17
11-12 Start Bit — Ideal Case..................................................................................11-19
11-13 Start Bit — Noise Case One ........................................................................11-20
11-14 Start Bit — Noise Case Two ........................................................................11-21
11-15 Start Bit — Noise Case Three......................................................................11-22
11-16 Start Bit — Noise Case Four........................................................................11-23
12-1 ISPI Channel Block Diagram..........................................................................12-1
12-2 Timing Diagram of ISPI 8-Bit Operation.........................................................12-2
12-3 ISPI Data Register .........................................................................................12-5
12-4 ISPI Control Register .....................................................................................12-5
12-5 ISPI Interval Control Register.........................................................................12-8
12-6 ISPI Status Register.......................................................................................12-8
13-1 External Interrupt/GPIO Block Diagram.........................................................13-1
13-2 Edge Port Pin Assignment Register...............................................................13-2
13-3 Edge Port Data Direction Register.................................................................13-3
13-4 Edge Port Data Register................................................................................13-3
13-5 Edge Port Flag Register.................................................................................13-4
14-1 KPP Block Diagram........................................................................................14-1
14-2 Keypad Control Register................................................................................14-3
14-3 Keypad Status Register .................................................................................14-4
14-4 Keypad Data Direction Register.....................................................................14-5
14-5 Keypad Data Register....................................................................................14-5
14-6 Keypad Synchronizer Functional Diagram.....................................................14-8
14-7 Decoding Wrong Three Key Presses.............................................................14-9
15-1 PWM Block Diagram......................................................................................15-1
15-2 PWM Generating Audio .................................................................................15-1
15-3 PWM Prescaler..............................................................................................15-2
15-4 PWM Control Registers..................................................................................15-4
15-5 PWM Period Registers...................................................................................15-6
15-6 PWM Width Registers....................................................................................15-7
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MMC2001 MOTOROLA
REFERENCE MANUAL xvii
LIST OF ILLUSTRATIONS
Paragraph Title Page
15-7 PWM Count Registers....................................................................................15-7
16-1 OnCE Block Diagram.....................................................................................16-1
16-2 OnCE Controller.............................................................................................16-2
16-3 OnCE Controller and Serial Interface.............................................................16-4
16-4 OnCE Command Register .............................................................................16-7
16-5 OnCE Control Register ..................................................................................16-8
16-6 OnCE Status Register..................................................................................16-11
16-7 OnCE Memory Breakpoint Logic..................................................................16-13
16-8 OnCE Trace Logic Block Diagram...............................................................16-15
16-9 CPU Scan Chain Register (CPUSCR).........................................................16-17
16-10 Control State Register..................................................................................16-18
16-11 OnCE PC FIFO............................................................................................16-20
16-12 Recommended Connector Interface to JTAG/OnCE Port............................16-22
A-1 CLKIN Timing (for Square Wave Input) ...........................................................A-2
A-2 Reset Timing....................................................................................................A-3
A-3 MOD Timing.....................................................................................................A-3
A-4 External Interrupt Timing..................................................................................A-4
A-5 EIM Read/Write Timing....................................................................................A-5
A-6 SPI Slave Timing (PHA = 0).............................................................................A-7
A-7 SPI Slave Timing (PHA = 1).............................................................................A-7
A-8 SPI Manual/Interval Mode Timing (PHA = 0)...................................................A-8
A-9 SPI Manual/Interval Mode Timing (PHA = 1)...................................................A-8
A-10 Test Clock Input Timing ...................................................................................A-9
A-11 TRST Timing....................................................................................................A-9
A-12 Test Access Port Timing................................................................................A-10
B-1 144-Lead Plastic Thin Quad Flat Pack Pin Assignment...................................B-1
C-1 Interrupt Source Register.................................................................................C-2
C-2 Normal Interrupt Enable Register.....................................................................C-3
C-3 Fast Interrupt Enable Register.........................................................................C-3
C-4 Normal Interrupt Pending Register...................................................................C-4
C-5 Fast Interrupt Pending Register.......................................................................C-4
C-6 Reset Source Register.....................................................................................C-6
C-7 TOD Control/Status Register ...........................................................................C-7
C-8 TOD Seconds Register....................................................................................C-8
C-9 TOD Fraction Register.....................................................................................C-8
C-10 TOD Seconds Alarm Register..........................................................................C-9
C-11 TOD Fraction Alarm Register...........................................................................C-9
C-12 Watchdog Control Register............................................................................C-10
C-13 Watchdog Service Register............................................................................C-11
C-14 PIT Control and Status Register ....................................................................C-11
C-15 PIT Data Register...........................................................................................C-13
C-16 PIT Alternate Data Register...........................................................................C-13
C-17 Keypad Control Register................................................................................C-14
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xviii REFERENCE MANUAL
LIST OF ILLUSTRATIONS
Paragraph Title Page
C-18 Keypad Status Register .................................................................................C-14
C-19 Keypad Data Direction Register.....................................................................C-15
C-20 Keypad Data Register....................................................................................C-16
C-21 CS0 Control Register.....................................................................................C-17
C-22 CS1, CS2, CS3 Control Registers .................................................................C-17
C-23 EIM Configuration Register............................................................................C-21
C-24 PWM Control Registers..................................................................................C-23
C-25 PWM Period Registers...................................................................................C-26
C-26 PWM Width Registers....................................................................................C-26
C-27 PWM Count Registers....................................................................................C-27
C-28 Edge Port Pin Assignment Register...............................................................C-28
C-29 Edge Port Data Direction Register.................................................................C-28
C-30 Edge Port Data Register................................................................................C-29
C-31 Edge Port Flag Register.................................................................................C-29
C-32 ISPI Data Register.........................................................................................C-30
C-33 ISPI Control Register .....................................................................................C-31
C-34 ISPI Interval Control Register.........................................................................C-33
C-35 ISPI Status Register.......................................................................................C-34
C-36 UART Receive Register.................................................................................C-36
C-37 UART Transmit Register................................................................................C-37
C-38 UART Control Register 1 ...............................................................................C-38
C-39 UART Control Register 2 ...............................................................................C-40
C-40 UART BRG Register......................................................................................C-42
C-41 UART Status Register....................................................................................C-42
C-42 UART Test Register.......................................................................................C-44
C-43 UART Port Control Register...........................................................................C-44
C-44 UART Data Direction Register.......................................................................C-45
C-45 UART Port Data Register...............................................................................C-45
C-46 OnCE Command Register .............................................................................C-46
C-47 OnCE Control Register ..................................................................................C-47
C-48 OnCE Status Register....................................................................................C-50
C-49 Control State Register....................................................................................C-52
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MMC2001 MOTOROLA
REFERENCE MANUAL xix
LIST OF TABLES
Paragraph Title Page
2-1 M•CORE Instruction Set .................................................................................2-6
2-2 M•CORE Bus Signals ..................................................................................2-11
2-3 Interface Requirements for Read and Write Cycles.......................................2-12
2-4 Termination Result Summary.........................................................................2-14
3-1 MMC2001 Module Address Map......................................................................3-1
3-2 MMC2001 Address Map ..................................................................................3-2
4-1 Pin Requirements in 144-Pin Package ..........................................................4-2
5-1 ROM Module Address Map..............................................................................5-1
6-1 Static RAM Module Address Map....................................................................6-1
7-1 Chip Select Address Range.............................................................................7-3
7-2 Interface Requirements for Read and Write Cycles .......................................7-5
7-3 EIM Memory Map ............................................................................................7-7
7-4 Wait State Control Field Settings....................................................................7-9
7-5 Data Port Size Field Settings.........................................................................7-10
7-6 Show Cycle Enable Field Settings.................................................................7-13
8-1 CPU Core and Peripherals Clock Source........................................................8-1
8-2 CPU Core and Peripherals in Low-Power Modes............................................8-7
9-1 Timer/Reset Module Address Map ..................................................................9-1
10-1 Interrupt Controller Address Map ..................................................................10-2
10-2 Interrupt Source Assignment ........................................................................10-6
11-1 UART Module Address Map ..........................................................................11-6
11-2 TxFL Field Settings........................................................................................11-9
11-3 RxFL Field Settings......................................................................................11-10
11-4 UART Pins GPIO Assignment......................................................................11-16
11-5 UART Low-Power Mode Operation..............................................................11-23
12-1 ISPI Module Address Map .............................................................................12-4
12-2 BAUD RATE Field Settings............................................................................12-7
12-3 CLOCK COUNT Field Settings......................................................................12-7
12-4 ISPI Low-Power Mode Operation.................................................................12-11
13-1 GPIO Edge Port Address Map ......................................................................13-2
13-2 EPPAx Field Settings.....................................................................................13-3
14-1 Keypad Port Column Modes..........................................................................14-2
14-2 Keypad Port Address Map ............................................................................14-2
15-1 PWM Address Map........................................................................................15-3
15-2 CLK SEL Field Settings..................................................................................15-6
15-3 PWM Range at 16 MHz .................................................................................15-8
15-4 PWM Low-Power Mode Operation.................................................................15-8
16-1 OnCE Register Addressing ...........................................................................16-8
16-2 Sequential Control Field Settings...................................................................16-9
16-3 Memory Breakpoint Control Field Settings...................................................16-10
16-4 Processor Mode Field Settings....................................................................16-12
A-1 Maximum Ratings ............................................................................................A-1
A-2 DC Electrical Specifications ...........................................................................A-1
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MOTOROLA MMC2001
xx REFERENCE MANUAL
LIST OF TABLES
Paragraph Title Page
A-3 Clock Input Specifications................................................................................A-2
A-4 Reset, MOD Timing Specifications ................................................................A-2
A-5 External Interrupt Timing Specifications...........................................................A-3
A-6 EIM Timing Specifications................................................................................A-4
A-7 ISPI Timing Specifications ...............................................................................A-6
A-8 OnCE Timing Specifications ............................................................................A-9
C-1 MMC2001 Address Map ..................................................................................C-1
C-2 Interrupt Controller Address Map ....................................................................C-2
C-3 Timer/Reset Module Address Map .................................................................C-5
C-4 Keypad Port Address Map ............................................................................C-13
C-5 EIM Address Map ..........................................................................................C-16
C-6 Wait State Control Field Settings..................................................................C-18
C-7 Data Port Size Field Settings.........................................................................C-19
C-8 Chip-Select Address Range...........................................................................C-20
C-9 Show Cycle Enable Field Settings.................................................................C-22
C-10 PWM Address Map ......................................................................................C-22
C-11 Clock Select Field Values ..............................................................................C-25
C-12 GPIO Edge Port Address Map ......................................................................C-27
C-13 EPPAx Field Settings.....................................................................................C-28
C-14 Interval Mode Serial Peripheral Interface Address Map.................................C-30
C-15 BAUD RATE Values.......................................................................................C-32
C-16 CLOCK COUNT Values.................................................................................C-33
C-17 UART Module Address Map ..........................................................................C-35
C-18 TxFL Field Settings........................................................................................C-38
C-19 RxFL Field Settings........................................................................................C-39
C-20 OnCE Register Addressing............................................................................C-47
C-21 Sequential Control Field Definition.................................................................C-48
C-22 Memory Breakpoint Control Field Definition...................................................C-49
C-23 Processor Mode Field Definition....................................................................C-51
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MMC2001 INTRODUCTION MOTOROLA
REFERENCE MANUAL 1-1
SECTION 1
INTRODUCTION
The MMC2001 integrated processor incorporates the following functional units:
• M•CORE™ Integer Processor
— 32-bit RISC architecture
— Low power, high performance
• On-chip, 256-Kbyte ROM
• On-chip, 32-Kbyte SRAM with battery backup supply support
• Interrupt Controller
— Support for up to 32 interrupt sources
• External Interface Module (EIM)
— Transfers information between the MMC2001 and external memory or periph-
erals
— 22 address lines
— 16 data lines
— Chip select and wait state generation
— Bus watchdog timer
• Timer/Reset Module
— Crystal oscillator: generates the master clock signal for the time-of-day timer
from a 32.768-kHz external crystal
— Time-of-day timer: provides time-of-day information as well as an alarm clock
function
— Watchdog timer: resets the chip to recover from system failure
— Reset unit: provides low voltage detection input and backup power switching
for SRAM and the time-of-day timer
— Periodic interrupt timer
• Universal Asynchronous Receiver/Transmitter Module (UART)
— Two independent UART channels
— Asynchronous operation
— Baud rate generation
— Infrared (IR) interface support
• 16-bit general-purpose I/O port with support for keyboard scan/encode
• 8-bit general-purpose I/O port with support for edge/level sensitive external inter-
rupts
• Pulse-Width Modulation Module (PWM)
— Six independent PWM channels
— Programmable period
— Programmable duty cycle
— Periodic interrupt capability
— Pins can be configured as general-purpose I/O
• Interval Mode Serial Peripheral Interface (ISPI)
— Efficient communication with slower serial peripherals
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