Motorola Freescale Semiconductor M-Core MMC2001 User manual

M•CORE™
MMC2001
Reference Manual
Revision 1.1
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The M•CORE name and logotype and the OnCE name are trademarks of Motorola, Inc.
© Motorola, Inc. 1998
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REFERENCE MANUAL iii
Conventions
This document uses the following notational conventions:
mnemonics Instruction mnemonics are shown in lowercase bold
0x0F Hexadecimal numbers
0b0011 Binary numbers
Nomenclature
Logic level one is the voltage that corresponds to a Boolean true (1) state.
Logic level zero is the voltage that corresponds to a Boolean false (0) state.
To set a bit or bits means to establish logic level one on the bit or bits.
To clear a bit or bits means to establish logic level zero on the bit or bits.
LSB means least significant bit or bits. MSB means most significant bit or bits. Refer-
ences to low and high bytes are spelled out.
A signal is asserted when it is in its active or true state, regardless of whether that
state is represented by a high or low voltage. A signal is negated when it is in its inac-
tive or false state.
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MMC2001 MOTOROLA
REFERENCE MANUAL v
TABLE OF CONTENTS
Paragraph Title Page
SECTION 1
INTRODUCTION
SECTION 2
INTEGER CPU
2.1 M•CORE Overview ..........................................................................................2-1
2.2 Features...........................................................................................................2-2
2.3 Microarchitecture Summary.............................................................................2-2
2.4 Programming Model.........................................................................................2-3
2.5 Data Format Summary.....................................................................................2-5
2.6 Operand Addressing Capabilities.....................................................................2-6
2.7 Instruction Set Overview..................................................................................2-6
2.8 M•CORE Bus Interface....................................................................................2-8
2.8.1 Bus Characteristics .......................................................................................2-8
2.8.2 Bus Signals ...................................................................................................2-9
2.8.3 Signal Descriptions......................................................................................2-10
2.8.4 Bus Operation .............................................................................................2-11
2.8.5 Processor Instruction/Data Transfers..........................................................2-13
2.8.6 Bus Exception Cycles..................................................................................2-14
SECTION 3
SYSTEM MEMORY MAP
3.1 Overview..........................................................................................................3-1
3.2 Peripheral Module Address Allocation.............................................................3-1
3.3 Peripheral Module Interface Operation............................................................3-2
3.4 Peripheral Module Address Assignment..........................................................3-2
SECTION 4
SIGNAL DESCRIPTIONS
4.1 Overview..........................................................................................................4-1
4.2 Signal Index .....................................................................................................4-2
4.3 Bus Signals......................................................................................................4-4
4.3.1 Address Bus (ADDR[19:0]) ...........................................................................4-4
4.3.2 Data Bus (DATA[15:0])..................................................................................4-4
4.3.3 Output Enable (OE).......................................................................................4-4
4.3.4 Read/Write Enable (R/W)..............................................................................4-4
4.3.5 Enable Byte 1 (EB1)......................................................................................4-4
4.3.6 Enable Byte 0 (EB0)......................................................................................4-4
4.3.7 Chip Selects (CS3, CS[2:0])..........................................................................4-4
4.3.8 Internal ROM Disable (MOD) ........................................................................4-4
4.4 Exception Control Signals................................................................................4-4
4.4.1 Reset (RSTIN)...............................................................................................4-4
4.4.2 Low Voltage Reset (LVRSTIN)......................................................................4-5
4.4.3 Reset Out (RSTOUT)....................................................................................4-5
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4.5 Clock Signals ...................................................................................................4-5
4.5.1 Crystal Oscillator (XOSC, EXOSC)...............................................................4-5
4.5.2 Clock Input (CLKIN) ......................................................................................4-5
4.5.3 Clock Output (CLKOUT)................................................................................4-5
4.6 Debug and Emulation Support Signals............................................................4-5
4.6.1 Test Clock (TCK)...........................................................................................4-5
4.6.2 Test Data Input (TDI).....................................................................................4-5
4.6.3 Test Data Output (TDO)................................................................................4-6
4.6.4 Test Mode Select (TMS) ...............................................................................4-6
4.6.5 Test Reset (TRST)........................................................................................4-6
4.6.6 Debug Event (DE).........................................................................................4-6
4.6.7 Factory Test Mode (TEST)............................................................................4-6
4.7 External Interrupts/GPIO Signals.....................................................................4-6
4.7.1 External Interrupts 7 – 0 (INT[7:0])................................................................4-6
4.8 Keypad Signals................................................................................................4-7
4.8.1 Column Strobes (COL[7:0])...........................................................................4-7
4.8.2 Row Senses (ROW[7:0])...............................................................................4-7
4.9 UART Module Signals......................................................................................4-7
4.9.1 Receive Data (RxD0, RxD1) .........................................................................4-7
4.9.2 Transmit Data (TxD0, TxD1).........................................................................4-7
4.9.3 Clear to Send (CTS0)....................................................................................4-7
4.9.4 Request to Send (RTS0)...............................................................................4-8
4.10 Serial Peripheral Interface Module Signals......................................................4-8
4.10.1 SPI Data Master Out/Slave In (SPI_MOSI)...................................................4-8
4.10.2 SPI Data Master In/Slave Out (SPI_MISO)...................................................4-8
4.10.3 SPI Serial Clock (SPI_CLK)..........................................................................4-8
4.10.4 SPI Enable (SPI _EN)...................................................................................4-8
4.10.5 SPI General-Purpose Output (SPI _GP).......................................................4-8
4.11 Pulse Width Modulator Signals........................................................................4-8
4.11.1 PWM[5:0].......................................................................................................4-8
4.12 Power and Ground Pins...................................................................................4-9
4.12.1 Positive Supply (VDD)....................................................................................4-9
4.12.2 Ground (GND)...............................................................................................4-9
4.12.3 Standby Battery Power (VBATT).....................................................................4-9
4.12.4 Standby Power Filter (VSTBY)........................................................................4-9
SECTION 5
ROM MODULE
5.1 Overview..........................................................................................................5-1
5.2 Functional Description......................................................................................5-1
5.3 Applications......................................................................................................5-2
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SECTION 6
STATIC RAM MODULE
6.1 Overview..........................................................................................................6-1
6.2 Functional Description......................................................................................6-1
SECTION 7
EXTERNAL INTERFACE MODULE
7.1 Overview..........................................................................................................7-1
7.2 Signals .............................................................................................................7-1
7.2.1 Address Bus..................................................................................................7-1
7.2.2 Data Bus........................................................................................................7-2
7.2.3 Read/Write ....................................................................................................7-2
7.2.4 Control Signals..............................................................................................7-2
7.2.5 Boot Mode.....................................................................................................7-2
7.2.6 Chip Select Outputs ......................................................................................7-2
7.3 Chip-Select Address Range.............................................................................7-3
7.4 EIM Interface Example.....................................................................................7-3
7.5 EIM Functionality..............................................................................................7-4
7.5.1 Configurable Bus Sizing................................................................................7-4
7.5.2 External Boot ROM Control...........................................................................7-6
7.5.3 Programmable Output Generation................................................................7-6
7.5.4 Bus Watchdog Operation..............................................................................7-6
7.5.5 Error Conditions ............................................................................................7-6
7.5.6 Show Cycles..................................................................................................7-7
7.6 EIM Programming Model .................................................................................7-7
7.6.1 Chip-Select Control Registers.......................................................................7-7
7.7 EIM Configuration Register............................................................................7-11
7.8 External Bus Timing Diagrams.......................................................................7-13
SECTION 8
CLOCK MODULE AND LOW-POWER MODES
8.1 Overview..........................................................................................................8-1
8.2 Low-Power Modes ...........................................................................................8-4
8.2.1 CPU Core Low-Power Modes.......................................................................8-4
8.2.2 Peripheral Behavior in Low-Power Modes....................................................8-5
8.2.3 General Low-Power Features .......................................................................8-7
SECTION 9
TIMER/RESET MODULE
9.1 Overview..........................................................................................................9-1
9.2 Timer/Reset Programming Model....................................................................9-1
9.3 Reset Operation...............................................................................................9-2
9.3.1 Reset Pins.....................................................................................................9-2
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9.3.2 Reset Sources...............................................................................................9-2
9.3.3 Reset Sequence............................................................................................9-3
9.3.4 Reset Source/Chip Configuration Register (RSCR)......................................9-3
9.4 Time-of-Day Timer...........................................................................................9-4
9.4.1 TOD Operation..............................................................................................9-5
9.4.2 TOD in Low-Power Modes............................................................................9-5
9.4.3 Time-of-Day Control/Status Register (TODCSR)..........................................9-5
9.4.4 TOD Seconds Register (TODSR) .................................................................9-6
9.4.5 TOD Fraction Register (TODFR)...................................................................9-6
9.4.6 TOD Seconds Alarm Register (TODSAR).....................................................9-7
9.4.7 TOD Fraction Alarm Register (TODFAR)......................................................9-7
9.5 Watchdog Timer...............................................................................................9-8
9.5.1 Watchdog Timing Specifications...................................................................9-9
9.5.2 Watchdog Timer after Reset .........................................................................9-9
9.5.3 Watchdog Timer Service Operation..............................................................9-9
9.5.4 Watchdog Timer in Wait Mode......................................................................9-9
9.5.5 Watchdog Timer in Doze Mode.....................................................................9-9
9.5.6 Watchdog Timer in Stop Mode......................................................................9-9
9.5.7 Watchdog Timer in Debug Mode.................................................................9-10
9.5.8 Watchdog Timer Programming Model.........................................................9-10
9.6 Interval Timer (PIT)........................................................................................9-11
9.6.1 PIT Operation..............................................................................................9-12
9.6.2 PIT as a “Set-and-Forget” Timer.................................................................9-12
9.6.3 PIT as a “Free-Running” Timer ...................................................................9-13
9.6.4 Interval Timer Registers ..............................................................................9-13
9.6.5 PIT Control/Status Register (ITCSR) ..........................................................9-14
9.6.6 PIT Data Register (ITDR)............................................................................9-15
9.6.7 PIT Alternate Data Register (ITADR) ..........................................................9-16
9.6.8 PIT in Low-Power Modes............................................................................9-16
9.6.9 PIT in Debug Mode .....................................................................................9-16
SECTION 10
INTERRUPT CONTROLLER
10.1 Overview........................................................................................................10-1
10.2 Interrupt Controller Programming Model........................................................10-2
10.2.1 Interrupt Source Register (INTSRC) ...........................................................10-2
10.2.2 Normal Interrupt Enable Register (NIER)....................................................10-3
10.2.3 Fast Interrupt Enable Register (FIER).........................................................10-3
10.2.4 Normal Interrupt Pending Register (NIPND)...............................................10-4
10.2.5 Fast Interrupt Pending Register (FIPND)....................................................10-5
10.2.6 Interrupt Request Input Assignments..........................................................10-5
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TABLE OF CONTENTS
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SECTION 11
UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER MODULE
11.1 Overview........................................................................................................11-1
11.2 UART Signals.................................................................................................11-2
11.2.1 RTS — Request to Send (UART0)..............................................................11-2
11.2.2 CTS — Clear to Send (UART0) ..................................................................11-2
11.2.3 TXD — UART Transmit...............................................................................11-3
11.2.4 RXD — UART Receive ...............................................................................11-3
11.3 Sub-Block Description....................................................................................11-3
11.3.1 Transmitter..................................................................................................11-3
11.3.2 Receiver......................................................................................................11-3
11.3.3 Infrared Interface.........................................................................................11-4
11.3.4 16x Bit Clock Generator..............................................................................11-4
11.3.5 General UART Definitions...........................................................................11-4
11.4 UART Programming Model............................................................................11-5
11.4.1 UART Receive Register (URX)...................................................................11-7
11.4.2 UART Transmitter Register (UTX) ..............................................................11-8
11.4.3 UART Control Register 1 (UCR1) ...............................................................11-9
11.4.4 UART Control Register 2 (UCR2) .............................................................11-11
11.4.5 UART BRG Register (UBRGR).................................................................11-13
11.4.6 UART Status Register (USR)...................................................................11-14
11.4.7 UART Test Register (UTS)........................................................................11-15
11.5 GPIO Pins and Registers.............................................................................11-16
11.5.1 UART Port Control Register (UPCR) ........................................................11-16
11.5.2 UART Data Direction Register (UDDR).....................................................11-16
11.5.3 UART Port Data Register (UPDR) ............................................................11-17
11.6 Data Sampling Technique on the Receiver..................................................11-17
11.7 UART Operation in Low-Power System Modes...........................................11-23
11.8 UART Operation in System Debug Mode....................................................11-24
SECTION 12
INTERVAL MODE SERIAL PERIPHERAL INTERFACE
12.1 Overview........................................................................................................12-1
12.2 Operation .......................................................................................................12-1
12.2.1 Manual (Master) Mode................................................................................12-2
12.2.2 Interval (Master) Mode................................................................................12-3
12.2.3 Slave Mode .................................................................................................12-3
12.3 Signal Descriptions ........................................................................................12-3
12.3.1 SPI_MISO (Master In, Slave Out) ...............................................................12-3
12.3.2 SPI_MOSI (Master Out, Slave In)...............................................................12-4
12.3.3 SPI_EN........................................................................................................12-4
12.3.4 SPI_CLK......................................................................................................12-4
12.3.5 SPI_GP .......................................................................................................12-4
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12.4 ISPI Programming Model...............................................................................12-4
12.4.1 ISPI Data Register.......................................................................................12-5
12.4.2 ISPI Control Register...................................................................................12-5
12.4.3 ISPI Interval Control Register......................................................................12-8
12.4.4 ISPI Status Register....................................................................................12-8
12.5 ISPI Programming Examples.........................................................................12-9
12.5.1 Manual Mode Example................................................................................12-9
12.5.2 Slave Mode Example ................................................................................12-10
12.5.3 Interval Model Example.............................................................................12-10
12.6 ISPI Operation in Low-Power System Modes..............................................12-11
12.7 ISPI Operation in System Debug Mode.......................................................12-11
SECTION 13
EXTERNAL INTERRUPTS/GPIO (EDGE PORT)
13.1 Overview........................................................................................................13-1
13.2 Interrupt/General-Purpose I/O Pin Descriptions (INT[0:7]) ............................13-1
13.3 Edge Port Programming Model......................................................................13-2
13.3.1 Edge Port Pin Assignment Register (EPPAR) ............................................13-2
13.3.2 Edge Port Data Direction Register (EPDDR)..............................................13-3
13.3.3 Edge Port Data Register (EPDR)................................................................13-3
13.3.4 Edge Port Flag Register (EPFR).................................................................13-4
SECTION 14
KEYPAD PORT
14.1 Overview........................................................................................................14-1
14.2 KPP Pin Description.......................................................................................14-2
14.2.1 Input Pins ....................................................................................................14-2
14.2.2 Output Pins..................................................................................................14-2
14.3 KPP Programming Model...............................................................................14-2
14.3.1 Keypad Control Register (KPCR)................................................................14-2
14.3.2 Keypad Status Register (KPSR) .................................................................14-3
14.3.3 Keypad Data Direction Register (KDDR) ....................................................14-5
14.3.4 Keypad Data Register (KPDR)....................................................................14-5
14.4 Keypad Operation..........................................................................................14-6
14.4.1 Keypad Matrix Construction........................................................................14-6
14.4.2 Keypad Port Configuration..........................................................................14-6
14.4.3 Keypad Matrix Scanning .............................................................................14-6
14.4.4 Keypad Standby.........................................................................................14-7
14.4.5 Glitch Suppression on Keypad Inputs.........................................................14-7
14.4.6 Multiple Key Closures..................................................................................14-8
14.4.7 Typical Keypad Configuration and Scanning Sequence.............................14-9
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SECTION 15
PULSE WIDTH MODULATOR
15.1 Overview........................................................................................................15-1
15.2 PWM Programming Model.............................................................................15-2
15.2.1 PWM Control Register.................................................................................15-4
15.2.2 PWM Period Register..................................................................................15-6
15.2.3 PWM Width Register...................................................................................15-7
15.2.4 PWM Counter Register ...............................................................................15-7
15.3 PWM Operating Range..................................................................................15-8
15.4 PWM Operation in Low-Power System Modes..............................................15-8
SECTION 16
OnCE™ DEBUG MODULE
16.1 Overview........................................................................................................16-1
16.2 Operation .......................................................................................................16-1
16.3 OnCE Pins .....................................................................................................16-3
16.3.1 Debug Serial Input (TDI) .............................................................................16-3
16.3.2 Debug Serial Clock (TCK)...........................................................................16-3
16.3.3 Debug Serial Output (TDO).........................................................................16-3
16.3.4 Debug Mode Select (TMS)..........................................................................16-3
16.3.5 Test Reset (TRST)......................................................................................16-4
16.3.6 Debug Event (DE).......................................................................................16-4
16.4 OnCE Controller and Serial Interface.............................................................16-4
16.5 OnCE Interface Signals..................................................................................16-5
16.5.1 Internal Debug Request Input (IDR)............................................................16-5
16.5.2 CPU Debug Request (DBGRQ)..................................................................16-5
16.5.3 CPU Debug Acknowledge (DBGACK)........................................................16-5
16.5.4 CPU Breakpoint Request (BRKRQ)............................................................16-5
16.5.5 CPU Address, Attributes (ADDR, ATTR) ....................................................16-5
16.5.6 CPU Status (PSTAT)...................................................................................16-5
16.5.7 OnCE Debug Output (DEBUG)...................................................................16-6
16.6 OnCE Controller Registers.............................................................................16-6
16.6.1 OnCE Command Register (OCMR)............................................................16-6
16.6.2 OnCE Control Register (OCR) ....................................................................16-8
16.6.3 OnCE Status Register (OSR)....................................................................16-11
16.7 OnCE Decoder (ODEC)...............................................................................16-12
16.8 Memory Breakpoint Logic ............................................................................16-12
16.8.1 Memory Address Latch (MAL)...................................................................16-13
16.8.2 Breakpoint Address Base Registers (BABA, BABB).................................16-14
16.8.3 Breakpoint Address Mask Registers (BAMA, BAMB) ...............................16-14
16.8.4 Breakpoint Address Comparators.............................................................16-14
16.8.5 Memory Breakpoint Counters (MBCA, MBCB) .........................................16-14
16.9 OnCE Trace Logic........................................................................................16-14
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