Motorola MPC860 PowerQUICC User manual

MPC860 Overview
Memory Map
Hardware Interface Overview
PowerPC Core Overview
PowerPC Core Register Set
MPC860 Instruction Set
PowerPC Exceptions
Instruction and Data Caches
Memory Management Unit
Instruction Execution Timing
System Interface Unit
Reset
External Signals
MPC860 External Bus Interface
Clocks and Power Control
Memory Controller
PCMCIA Interface
Communications Processor Module and CPM Timers
Communications Processor
SDMA Channels and IDMA Emulation
Serial Interface
SCC Introduction
SCC UART Mode
SCC HDLC Mode
SCC AppleTalk Mode
SCC Asynchronous HDLC Mode and IrDA
SCC BISYNC Mode
SCC Ethernet Mode
SCC Transparent Mode
Serial Management Controller
Serial Peripheral Interface
I C Controller
Parallel Interface Port
Parallel I/O Port
CPM Interrupt Controller
Digital Signal Processing
System Development and Debugging
IEEE 1149.1 Test Access Port
Byte Ordering
Serial Communciation Performance
Register Quick Reference Guide
MPC860 Instruction Set
Glossary
Index
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MPC860 Overview
Memory Map
Hardware Interface Overview
PowerPC Core Overview
PowerPC Core Register Set
MPC860 Instruction Set
PowerPC Exceptions
Instruction and Data Caches
Memory Management Unit
Instruction Execution Timing
System Interface Unit
Reset
External Signals
MPC860 External Bus Interface
Clocks and Power Control
Memory Controller
PCMCIA Interface
Communications Processor Module and CPM Timers
Communications Processor
SDMA Channels and IDMA Emulation
Serial Interface
SCC Introduction
SCC UART Mode
SCC HDLC Mode
SCC AppleTalk Mode
SCC Asynchronous HDLC Mode and IrDA
SCC BISYNC Mode
SCC Ethernet Mode
SCC Transparent Mode
Serial Management Controller
Serial Peripheral Interface
I C Controller
Parallel Interface Port
Parallel I/O Port
CPM Interrupt Controller
Digital Signal Processing
System Development and Debugging
IEEE 1149.1 Test Access Port
Byte Ordering
Serial Communciation Performance
Register Quick Reference Guide
MPC860 Instruction Set
Glossary
Index
2
2
3
4
5
6
7
8
9
A
B
C
1
GLO
IND
11
12
13
14
15
16
17
18
10
19
21
22
23
24
25
26
27
28
20
29
31
32
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MPC860UM/AD
07/98
REV. 1
MPC860 PowerQUICC
ª
UserÕs Manual

This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without
notice. Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no
express or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information
in this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
or circuit, and speciÞcally disclaims any and all liability, including without limitation consequential or incidental damages. ÒTypicalÓ parameters can and do
vary in different applications. All operating parameters, including ÒTypicalsÓ must be validated for each customer application by customerÕs technical
experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other
application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its ofÞcers, employees, subsidiaries,
afÞliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent
regarding the design or manufacture of the part.
Motorola and are registered trademarks and QUICC and PowerQUICC are trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/
AfÞrmative Action Employer.
The PowerPC name, the PowerPC logotype, PowerPC 601, PowerPC 603, PowerPC 603e, PowerPC 604, and RS/6000 are trademarks of International
Business Machines Corporation used by Motorola under license from International Business Machines Corporation.
I2C is a registered trademark of Phillips Corporation.
© Motorola Inc. 1998. All rights reserved.
Portions hereof © International Business Machines Corp. 1991Ð1998. All rights reserved.

MOTOROLA Contents v
CONTENTS
Paragraph
Number Title Page
Number
About This Book
Before Using this Manual ...................................................................................lxiii
Audience..............................................................................................................lxiii
Organization ........................................................................................................ lxiv
Suggested Reading ............................................................................................lxviii
MPC8xx Documentation.................................................................................. lxviii
PowerPC Documentation ................................................................................. lxviii
Conventions.........................................................................................................lxix
Acronyms and Abbreviations............................................................................... lxx
PowerPC Architecture Terminology Conventions............................................lxxiii
Intended Audience.............................................................................................. lxxv
Contents.............................................................................................................. lxxv
Conventions........................................................................................................ lxxv
Acronyms and Abbreviations............................................................................lxxvi
Chapter 1
MPC860 Overview
1.1 Features ................................................................................................................1-1
1.2 Architecture Overview .........................................................................................1-5
1.3 Embedded PowerPC Core....................................................................................1-6
1.4 System Interface Unit (SIU).................................................................................1-7
1.5 PCMCIA Controller .............................................................................................1-7
1.6 Power Management..............................................................................................1-7
1.7 Communications Processor Module (CPM) ........................................................1-8
1.8 Software Compatibility Issues .............................................................................1-9
Chapter 2
Memory Map
Chapter 3
Hardware Interface Overview
3.1 System Bus Signals ..............................................................................................3-3
3.2 System Bus Signals ..............................................................................................3-3

vi MPC860 PowerQUICC UserÕs Manual MOTOROLA
CONTENTS
Paragraph
Number Title Page
Number
Chapter 4
The PowerPC Core
4.1 PowerPC Architecture Overview .........................................................................4-1
4.1.1 Levels of the PowerPC Architecture ................................................................4-3
4.2 Features.................................................................................................................4-4
4.3 Basic Structure of the Core...................................................................................4-5
4.3.1 Instruction Flow................................................................................................4-6
4.3.2 Basic Instruction Pipeline.................................................................................4-7
4.3.3 Instruction Unit.................................................................................................4-7
4.3.3.1 Branch Operations........................................................................................4-7
4.3.3.2 Dispatching Instructions...............................................................................4-9
4.4 Register Set...........................................................................................................4-9
4.5 Execution Units ....................................................................................................4-9
4.5.1 Branch Processing Unit ..................................................................................4-10
4.5.2 Integer Unit.....................................................................................................4-10
4.5.3 Load/Store Unit ..............................................................................................4-10
4.5.3.1 Executing Load/Store Instructions .............................................................4-12
4.5.3.2 Serializing Load/Store Instructions ............................................................4-12
4.5.3.3 Store Accesses............................................................................................4-12
4.5.3.4 Nonspeculative Load Instructions ..............................................................4-12
4.5.3.5 Unaligned Accesses....................................................................................4-13
4.5.3.6 Atomic Update Primitives ..........................................................................4-13
4.6 The MPC860 and the PowerPC Architecture.....................................................4-14
Chapter 5
PowerPC Core Register Set
5.1 MPC860 Register Implementation .......................................................................5-1
5.1.1 PowerPC RegistersÑUser Registers................................................................5-2
5.1.1.1 PowerPC User-Level Register Bit Assignments ..........................................5-2
5.1.1.1.1 Condition Register (CR)...........................................................................5-2
5.1.1.1.2 Condition Register CR0 Field Definition.................................................5-3
5.1.1.1.3 XER..........................................................................................................5-3
5.1.1.1.4 Time Base Registers.................................................................................5-4
5.1.2 PowerPC RegistersÑSupervisor Registers......................................................5-4
5.1.2.1 DAR, DSISR, and BAR Operation ..............................................................5-5
5.1.2.2 Unsupported Registers .................................................................................5-6
5.1.2.3 PowerPC Supervisor-Level Register Bit Assignments ................................5-6
5.1.2.3.1 Machine State Register (MSR) ................................................................5-6
5.1.2.3.2 Processor Version Register ......................................................................5-8
5.1.3 MPC860-Specific SPRs....................................................................................5-8

MOTOROLA Contents vii
CONTENTS
Paragraph
Number Title Page
Number
5.1.3.1 Accessing SPRs..........................................................................................5-11
5.2 Register Initialization at Reset ...........................................................................5-11
Chapter 6
MPC860 Instruction Set
6.1 Operand Conventions...........................................................................................6-1
6.1.1 Data Organization in Memory and Data Transfers ..........................................6-1
6.1.2 Aligned and Misaligned Accesses ...................................................................6-1
6.2 Instruction Set Summary......................................................................................6-2
6.2.1 Classes of Instructions......................................................................................6-3
6.2.1.1 Definition of Boundedly Undefined ............................................................6-4
6.2.1.2 Defined Instruction Class.............................................................................6-4
6.2.1.3 Illegal Instruction Class ...............................................................................6-4
6.2.1.4 Reserved Instruction Class...........................................................................6-5
6.2.2 Addressing Modes............................................................................................6-5
6.2.2.1 Memory Addressing.....................................................................................6-5
6.2.2.2 Effective Address Calculation .....................................................................6-6
6.2.2.3 Synchronization ...........................................................................................6-6
6.2.2.3.1 Context Synchronization..........................................................................6-6
6.2.2.3.2 Execution Synchronization ......................................................................6-7
6.2.2.3.3 Instruction-Related Exceptions................................................................6-7
6.2.3 Instruction Set Overview..................................................................................6-7
6.2.4 PowerPC UISA Instructions ............................................................................6-8
6.2.4.1 Integer Instructions ......................................................................................6-8
6.2.4.1.1 Integer Arithmetic Instructions ................................................................6-8
6.2.4.1.2 Integer Compare Instructions...................................................................6-9
6.2.4.1.3 Integer Logical Instructions ...................................................................6-10
6.2.4.1.4 Integer Rotate and Shift Instructions .....................................................6-10
6.2.4.2 Load and Store Instructions .......................................................................6-11
6.2.4.2.1 Integer Load and Store Address Generation ..........................................6-11
6.2.4.2.2 Register Indirect Integer Load Instructions ...........................................6-12
6.2.4.2.3 Integer Store Instructions.......................................................................6-13
6.2.4.2.4 Integer Load and Store with Byte-Reverse Instructions ........................6-13
6.2.4.2.5 Integer Load and Store Multiple Instructions ........................................6-14
6.2.4.2.6 Integer Load and Store String Instructions ............................................6-14
6.2.4.3 Branch and Flow Control Instructions .......................................................6-15
6.2.4.3.1 Branch Instruction Address Calculation ................................................6-15
6.2.4.3.2 Branch Instructions ................................................................................6-16
6.2.4.3.3 Condition Register Logical Instructions ................................................6-16
6.2.4.4 Trap Instructions ........................................................................................6-17
6.2.4.5 Processor Control Instructions ...................................................................6-17

viii MPC860 PowerQUICC UserÕs Manual MOTOROLA
CONTENTS
Paragraph
Number Title Page
Number
6.2.4.5.1 Move to/from Condition Register Instructions ......................................6-17
6.2.4.6 Memory Synchronization InstructionsÑUISA..........................................6-17
6.2.5 PowerPC VEA Instructions............................................................................6-19
6.2.5.1 Processor Control Instructions ...................................................................6-20
6.2.5.2 Memory Synchronization InstructionsÑVEA...........................................6-20
6.2.5.2.1 eieio Behavior ........................................................................................6-20
6.2.5.2.2 isync Behavior........................................................................................6-21
6.2.5.3 Memory Control InstructionsÑVEA.........................................................6-21
6.2.6 PowerPC OEA Instructions............................................................................6-22
6.2.6.1 System Linkage Instructions ......................................................................6-22
6.2.6.2 Processor Control InstructionsÑOEA .......................................................6-22
6.2.6.2.1 Move to/from Machine State Register Instructions ...............................6-22
6.2.6.2.2 Move to/from Special-Purpose Register Instructions ............................6-23
6.2.6.3 Memory Control InstructionsÑOEA.........................................................6-23
6.2.6.3.1 Supervisor-Level Cache Management Instruction .................................6-23
6.2.6.3.2 Translation Lookaside Buffer Management Instructions.......................6-23
6.2.7 Recommended Simplified Mnemonics ..........................................................6-24
Chapter 7
Exceptions
7.1 Exceptions ............................................................................................................7-2
7.1.1 Exception Ordering ..........................................................................................7-3
7.1.2 PowerPC-Defined Exceptions ..........................................................................7-4
7.1.2.1 System Reset Interrupt (0x00100)................................................................7-5
7.1.2.2 Machine Check Interrupt (0x00200) ............................................................7-5
7.1.2.3 DSI Exception (0x00300).............................................................................7-6
7.1.2.4 ISI Exception (0x00400) ..............................................................................7-6
7.1.2.5 External Interrupt Exception (0x00500).......................................................7-6
7.1.2.6 Alignment Exception (0x00600) ..................................................................7-7
7.1.2.6.1 Integer Alignment Exceptions..................................................................7-8
7.1.2.7 Program Exception (0x00700) .....................................................................7-9
7.1.2.8 Decrementer Exception (0x00900) ............................................................7-10
7.1.2.9 System Call Exception (0x00C00) .............................................................7-10
7.1.2.10 Trace Exception (0x00D00) .......................................................................7-11
7.1.2.11 Floating-Point Assist Exception.................................................................7-12
7.1.3 Implementation-Specific Exceptions..............................................................7-12
7.1.3.1 Software Emulation Exception (0x01000) .................................................7-12
7.1.3.2 Instruction TLB Miss Exception (0x01100) ..............................................7-12
7.1.3.3 Data TLB Miss Exception (0x01200) ........................................................7-13
7.1.3.4 Instruction TLB Error Exception (0x01300)..............................................7-13
7.1.3.5 Data TLB Error Exception (0x014000)......................................................7-14

MOTOROLA Contents ix
CONTENTS
Paragraph
Number Title Page
Number
7.1.3.6 Debug Exceptions (0x01C00Ð0x01F00)....................................................7-15
7.1.4 Implementing the Precise Exception Model ..................................................7-16
7.1.5 Recoverability after an Exception..................................................................7-17
7.1.6 Exception Latency..........................................................................................7-18
7.1.7 Partially Completed Instructions....................................................................7-19
Chapter 8
Instruction and Data Caches
8.1 Instruction Cache Organization............................................................................8-2
8.2 Data Cache Organization .....................................................................................8-5
8.3 Cache Control Registers.......................................................................................8-6
8.3.1 Instruction Cache Control Registers ................................................................8-6
8.3.1.1 Reading Data and Tags within the Instruction Cache..................................8-8
8.3.1.2 IC_CST Commands .....................................................................................8-9
8.3.1.2.1 Instruction Cache Enable/Disable Commands.........................................8-9
8.3.1.2.2 Instruction Cache Load & Lock Cache Block Command......................8-10
8.3.1.2.3 Instruction Cache Unlock Cache Block Command ...............................8-11
8.3.1.2.4 Instruction Cache Unlock All Command...............................................8-11
8.3.1.2.5 Instruction Cache Invalidate All Command...........................................8-11
8.3.2 Data Cache Control Registers ........................................................................8-11
8.3.2.1 Reading Data Cache Tags and Copyback Buffer.......................................8-14
8.3.2.2 DC_CST Commands..................................................................................8-15
8.3.2.2.1 Data Cache Enable/Disable Commands ................................................8-16
8.3.2.2.2 Data Cache Load & Lock Cache Block Command ...............................8-16
8.3.2.2.3 Data Cache Unlock Cache Block Command .........................................8-17
8.3.2.2.4 Data Cache Unlock All Command ........................................................8-17
8.3.2.2.5 Data Cache Invalidate All Command ....................................................8-17
8.3.2.2.6 Data Cache Flush Cache Block Command............................................8-17
8.4 PowerPC Cache Control Instructions.................................................................8-18
8.4.1 Instruction Cache Block Invalidate (
icbi ) ......................................................8-18
8.4.2 Data Cache Block Touch (
dcbt ) and Data Cache Block Touch
for Store (
dcbtst ) .......................................................................................8-18
8.4.3 Data Cache Block Zero (
dcbz ) ......................................................................8-19
8.4.4 Data Cache Block Store (
dcbst ) ....................................................................8-19
8.4.5 Data Cache Block Flush (
dcbf )......................................................................8-20
8.4.6 Data Cache Block Invalidate (
dcbi )...............................................................8-20
8.5 Instruction Cache Operations .............................................................................8-20
8.5.1 Instruction Cache Hit .....................................................................................8-22
8.5.2 Instruction Cache Miss...................................................................................8-22
8.5.3 Instruction Fetching on a Predicted Path .......................................................8-23
8.5.4 Fetching Instructions from Caching-Inhibited Regions.................................8-23

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CONTENTS
Paragraph
Number Title Page
Number
8.5.5 Updating Code And Memory Region Attributes............................................8-24
8.6 Data Cache Operation.........................................................................................8-24
8.6.1 Data Cache Load Hit ......................................................................................8-25
8.6.2 Data Cache Read Miss....................................................................................8-25
8.6.3 Write-Through Mode......................................................................................8-26
8.6.3.1 Data Cache Store Hit in Write-Through Mode ..........................................8-26
8.6.3.2 Data Cache Store Miss in Write-Through Mode........................................8-26
8.6.4 Write-Back Mode ...........................................................................................8-26
8.6.4.1 Data Cache Store Hit in Write-Back Mode................................................8-26
8.6.4.2 Data Cache Store Miss in Write-Back Mode .............................................8-27
8.6.5 Data Accesses to Caching-Inhibited Memory Regions..................................8-27
8.6.6 Atomic Memory References...........................................................................8-28
8.7 Cache Initialization after Reset...........................................................................8-29
8.8 Debug Support....................................................................................................8-29
8.8.1 Instruction and Data Cache Operation in Debug Mode .................................8-29
8.8.2 Instruction and Data Cache Operation with a Software Monitor Debugger ..8-30
Chapter 9
Memory Management Unit (MMU)
9.1 Features.................................................................................................................9-1
9.2 PowerPC Architecture Compliance......................................................................9-2
9.3 Address Translation..............................................................................................9-3
9.3.1 Translation Disabled.........................................................................................9-3
9.3.2 Translation Enabled..........................................................................................9-3
9.3.3 TLB Operation..................................................................................................9-5
9.4 Using Access Protection Groups ..........................................................................9-6
9.5 Protection Resolution Modes................................................................................9-7
9.6 Memory Attributes ...............................................................................................9-8
9.7 Translation Table Structure ..................................................................................9-9
9.7.1 Level-One Descriptor .....................................................................................9-13
9.7.2 Level-Two Descriptor ....................................................................................9-14
9.8 Programming Model...........................................................................................9-14
9.8.1 IMMU Control Register (MI_CTR)...............................................................9-16
9.8.2 DMMU Control Register (MD_CTR)............................................................9-17
9.8.3 IMMU/DMMU Effective Page Number Register (Mx_EPN) .......................9-18
9.8.4 IMMU Tablewalk Control Register (MI_TWC)............................................9-18
9.8.5 DMMU Tablewalk Control Register (MD_TWC).........................................9-19
9.8.6 IMMU Real Page Number Register (MI_RPN).............................................9-20
9.8.7 DMMU Real Page Number Register (MD_RPN)..........................................9-22
9.8.8 MMU Tablewalk Base Register (M_TWB) ...................................................9-23
9.8.9 MMU Current Address Space ID Register (M_CASID) ...............................9-23