Motorola M68MM01 User manual

M68MM01
MONOBOARD MICROCOMPUTER 1
MICROMODULE 1
The information in this document has been carefullychecked
and is be li eved to be entirely reliable. However, no responsibility
is assumed for inaccuracies.Furthermore, such information does
not convey to the purchaser of the product described any license
under the patent rights of Motorola, Inc. or others.
Motorola reserves the right to change speci fi cationswithout
notice.
EXORciser and EXbug are trademarks of Motorola Inc.
Fourth Edition
Copyright 1979 by Motorola Inc.
Previous Edition Copyright 1977
"All Ri ghts Reserved"
M68MM01(D4)
April, 1979

TABLE OF CONTENTS
Chapter Page
1. GENERAL INFORMATION ........•• • •... .. ...... •. •••... . ............ 1-1
1.1 Introduction ...............• •. ............. . .•• . ... ... . . . .. . . ... 1-1
1.2 Features ..................••...... . ...... . .••• •................. 1-1
1.3 Specifications ..................... . ...... . ..................•... 1-1
1.4 General Oescription .... . ........................................ 1-1
2. INSTALLATION INSTRUCTIONS. PROGRAMMING AND
INTERCONNECTION CONSiDERATIONS ........... . ........ . ... 2-1
2.1 Introduction .................................................... 2-1
2.2 Unpacking Instructions .......... . .......... . ..•. . ............... 2-1
2.3 Inspection ...................•• • .. . . .. .. . ......••... . ........... 2-1
2.4 Installation Instructions .......•........ . .... .•. .••... . ... . .. ..... 2-1
2.5 Programming ..................... . ... . ..... •. • •................ 2-1
2.6 Module Interconnections ....• . ............ . .•••............. . ... 2-5
3. THEORY OF OPERATION
.. . .......• • ... .. . ... .. .. .. •.• .............. 3-1
3.1 Introduction ..................• . .. .. ... .. ......••. . ... .. ........ 3-1
3.2 Block Diagram Description .... . ... .. ...........•............ . ... 3-1
4. MAINTENANCE INFORMATION ....... • ........•........••..... .. ..... 4-1
4.1 Introduction .................................... . .• ........ " ... 4-1
Figure
1-1
1-2
3-1
3-2
4-1
Table
1-1
2-1
2-2
2-3
2-4
-
4-1
LIST OF ILLUSTRATIONS
Page
Monoboard Micr ocomputer 1 ...................... . ...... ....... 1-2
Monoboard
Microcomputer 1 Address Map ....................... 1-4
Monoboard
Microcomputer 1 Block Diagram ..................... 3-3
Monoboard
Microcomputer 1 Schematic Diagram ................. 3-5
Monoboard Microcomputer 1 Parts Location
........................ 4-3
LIST OF TABLES
Page
Monoboard Microcomputer 1 Specifications .. . ... . ... . .......... . 1-5
Connector P1 Bus Interface Signals .............................. 2-6
Connector P2 PIA Interface Signals ... . ......... • ............... 2-11
Connector P3 PIA Interface Signals ................. .•. ......... 2-15
Connector P4 . PIA Interface Signals .. . ............... . . . .. . ..... 2-18
Monoboard Microcomputer 1 (M68MM01) Parts List
................. 4 -1

1.1 INTRODUCTIO N
CHAPTER 1
GENERAL
INFORMATION
Monoboard Microcomputer 1 (Micromodule 1), as shown in Figure 1-1 , is a
complete computer-on-a-board which will provide the OEM with a so lution to most of
his processing and cont ro l applications. This module, one of a family of
Micromodules, conlains Ihe Microprocessor, the program ER OM or ROM mem ory, R AM
memory,programmable input/oulput interfaces, and Ihe r eq uir ed clock, restart, bus inler-
f ace ,and co n tro l circuitr y. All add re ss r eferences within thi sma nu al are shown in hexadec-
ima l unless otherwise indicated .
1.2 FEATURES
The features of Monoboard Microcomputer 1 include:
• MC6800 Microprocessing Unit (MPU) with its associated clock oscillator,
power on reset timer, and memory decoding logic.
• 1024 bytes of Random Access Memory (RAM).
• Sockets for up 10 4096 bytes of Erasable Read Only Memory ( ER OM) or mask
programmable Read Only Memory (ROM).
•
Thr ee programmable Peripheral Interface Adapter (PIA) devices providing 60
programmable Inpu t/ Output and control lines.
• Address, data, and control bus drivers to interface Monoboa rd Microcomputer
1 wilh other modules in the family or with the E XO Rciser.
• TTL signal level inputs and TTL signal teve l, three state, or open collector
outp ut s.
• Oplional ma ling connectors, and pullup resistors for PIA oulput lines (available on
M 68 M MO H an d M68MM01 -2 onl y. See schemalic an d parts list.)
1.3
SPECIFICATIONS
Monoboard Microcomputer 1 specifications are identif ied in Table 1-1.
1.4 GENERAL DESCRIPTION
The Monoboard Microcomputer 1 provides the user with all of the processing
and
control power of an MC6800 Microprocessing Unit (MPU) working with 1K of
RAM, up
10 4K of EROM or ROM for programming, and three programmable
Peripheral Interface Adapters (
PI A). Additionally, the user has the option of
interfacing Monoboard
Microcomputer 1 (via its address, data, and cont rol bus
buffers) with other modules in the
Micromodule family and with the EX ORci se r.The
board al so contains th e required two-phase clock generator, th e reset tim er for power
turn-on initializati
on , addr ess bus decoding for establishing the addr esses for each
part, and th e refresh circuit for use with optional external dynamic memories. The
PIA's input/ou tput signals are identified in Table 1- 1.
1-1

1-2
" '"
o
-"
o
c:
o
:;;

•
The 16-bit MPU address bus is decoded on the board and provides RAM (0000-
03FF), the three PIA's (5800-580B) and ROM
(COOO-CFFF) addresses. Since these
addresses are not fully decoded, there are certain nonavailable ambiguous addresses
as shown in Figure 1-2. If additional Micromodules are to be used with Monoboard
Microcomputer 1, their address must beselected to fall within the available memory
locations(200Q-4FFF and 6000-BFFF).
Monoboard Microcomputer 1 is also bus compatible with the M6800EXORciser.
This versatility provides the user with the means to develop and debug both his
hardware and software and to troubleshoot
production hardware. Thus,the usercan
take advantage
of the EXORciser's optional memory and I/O modules.
1-3

ROM
AVAILABLE
fOR
EXTERNAL
MEMORY
(24K)
AVAILABLE
fOR
EXTERNAL
MEMORY
(12K)
6000
580C
57FF
4F
FF
RAM
FFFF
'000
DFFF
0000
ccoo
C800
C400
cooo
5FFF
5BOC
5808
5804
5800
57FF
5000
IFFF
0< 00
AMBIGUOUS ROM ADDRESSES
IA
12 AND A 13 ARE DON'T CARE)
PREFERABLE ROM ADDRESSES
} NOT AVAILABLE
(All NOT INCLUDED IN MEM ·N OT·S ELD)
} MODULE PIA (3) ADORE SSES
} NOT AVA ILABLE
(A ll N OT I NClUDED IN MEM·NOT·SEL D)
AMBIGUOUS RAM ADDRESSES
(AIO, A
II. A12 ARE DON 'T CARE)
03FF }
0000 MODULE RAM ADDRESSES
Figure 1- 2. Monoboard Microcomputer 1 Address Map
1-4

•
Table 1- 1. Monoboard Microcomputer 1 Specifications
CHARACTERISTICS
Microprocessor
Power Requirements
Without EROMs/ROMs
With four EROMs/ROMs
Word Size
Data
Address
Instructions
Instruc
ti ons
Addressing Modes
Clock Signal
Memory Size Capability
ROM/EROM Memory (on board)
RAM (on board)
I/O Addressing (on board)
External Memo ry
Interrupts
Internal
External
SPECIFICATIONS
MC6800 MPU
+5Vdc at 1.
lA(max)
+12Vdc at OmA
-12Vdc at 5mA(max)
+5Vdc at 1.1 A (max)
+12Vdc at 260mA (max)
-12Vdc at 180mA (max)
8 bits
16 bits
8, 16,
or 24 bits
72 variable length instructions.
Seven Add re ssing Modes:
Direct, Relative, Immediate, Indexed,
Extended, Implied, and Accumulator.
Crystal controlled 1 MHz
with
capability to wo rk wi th dynamic
memories.
4K bytes of memory (sockets only)
1K byte of memory
3 MC6820 PIA
48 data lines
12 interrupt/control lines
36K bytes av ai lable for external
memory and I/O.
IRQ maskable
interrupt from PIA's
IRQ maskable
interrupt and
NMI nonmaskable interrupt.
1-5

Table 1-1. Monoboard Microcomputer 1 Specifications (Contd)
CHARACTERISTICS
PIA1 Interface Signals
CAl
CA2
PAD-PA7
CBl
CB2
PBO-PB7
PIA2 I
nterface Signals
CAl
CA2
PAO-PA7
CBl
CB2
PBO-PB3
SPECIFICATIONS
TTL voltage compatible interrupt input
with programmable active transition.
TTL voltagecompatible line;programmable
to act as an interrupt input or as a
peripheral control output.
Eight TTL voltage compatible data
lines that can be programmed to
function as inputs or outputs.
TTL voltage compatible interrupt input
with programmable active transition
and buffered with inverting driver.
Peripheral control output buffered
with inverting
open-collector driver.
Eight data output lines buffered
with inverting
open-collector drivers.
TTL voltage compatible interrupt
input with programmable active
transition.
TTL voltagecompatibleline;programmable
to act as an interrupt input or as a
peripheral control output.
Eight TTL voltage compatible data
lines that can be programmed to function
as inputs
or outputs.
TTL voltage compatible interrupt
input with programmable active
transition and buffered with inverting
driver.
Pe ripheral control output buffered with
inverting open-collector driver.
Four data output lines buffered with
inverting open-collector drivers.
1-6

Table 1-1 . Mo nobo ard Microc ompul er 1 Specifications (Contd)
CHARACTERISTICS
SPECIFICATIONS
PB4-PB7
Four TT L voltage compatible data lines
that are har dware configured inverting input
or output lines. These data lines must be
programmed to correspond tothe optionally
installed input or output buffers.
PIA3 Interface Signals
CAl
TTL voltage compatible interrupt input
with programmab le active transition.
CA2
TTL voltage compatible li ne; programmable
to act as an interrupt input or as a
peripheral control output.
PAO-PA7 Eight
TT L voltage compatible data lines
that can be programmed to function as
inputs or outputs.
CBl
TTL voltage compatible interrupt input
with programmab le active transition and
buffered with inverting driver.
CB2 Peripheral
control-output buffered
with inverting open-collector dri ve r.
PBO-PB7 Eight TTL voltage
compatible data lin es
that are hardwar e configured inverting input
or output lines. These data lines must be
programmed
to correspond to the
optionally installed input or output
buffers.
Line Terminators
Optional pull-up resistor divider or terminator
(C B2 and PBO-PB7 on allthree (available on M68MM01-l and
PIA' s) M68MMOI-2 only)
Operating Temperature 0' to
70 'C.
Physical Characteristics
Width x Height 9.75 in. x 6.00 in.
Board Thickness 0.062 in.
Bus Mating
Connector Types
Connector PI (86 pin) Stanford
Applied Engineering
SAC-43D/1-2 or equivalent
Connectors P2 and P4 (50 pin) 3M type 3415-0001
or equivalent
Connector P3 (20 pin)
3M type 3461-0001 or equivalent
1-7

CHAPTER 2
INSTALLATION INSTRUCTIONS, PROGRAMMING
AND
INTERCONNECTION CONSIDERATIONS
2.1 INTRODU C TIO N
This chapter provides the unpacking, inspection, installation,programming,and
interconnection instructions for the M68MM01 Monoboard Microcomputer 1. This
chapter also discusses the module's interconnection signal s.
2.2 UNPA CK ING IN S TRUCTIONS
Unpack the Monoboard Mi crocomputer 1 from its sh ipping carton and.referring
to the packing list. verify that all of the items are present. Save the packing materials
for storing and reshipping of the module. If the shipping carton is damaged upon
receipt, request that the carrier's agent be present while the module
is being
unpacked and inspected.
2.3 INSPECTION
Monoboard Microcomputer 1 should be inspected upon receipt for broken,
damaged. or missing parts and physical damage to the printed circuit board.
2.4 IN ST A LLAT ION INSTRUCTIONS
Since Monoboard Microcomputer 1 is intended for user designed
microcomputer based systems, no special instatlation instructions are provided.
However, before installing the unit into the user's system or into the EXORciser,
insta ll the desired EROM or ROM devices intothe appropriate sockets and remove a ll
power from the system.
CAUT I ON
Inserting Monoboard Microcomputer 1into a system while
power is applied may result in damage to the components
on the Mi cromodule .
2.5 PROGRA MMING
Devel opment of the user's program f or use with Monoboard Microcomputer 1 is
quite straightforward as long as the user observes a few simple ground ru l es which
are listed
as fo ll ows:
a. The Random Access Memory (RAM) is assigned addresses 0000 through 03FF
to take advantage of the direct addressi ng mode. Therefore, the initialization
portion of the user"s program should load the MPU Stack Po inter with 03FF
unless an additional RAM module is used with the Micromodule.
2-1

• Using the EXORciser's PR OM ProgrammerModule to program the PR OMS.
•
Tr oubl es h ooting suspect systems.
2.5.2 HARDWARE PREPARATION
Thr ee different on-board modifica ti ons provide the user with additional
flexibility
in using Monoboard Microcomputer 1. These modifications are described
in the following paragraphs.
2.5.2.1 Operation With/Without Debug Module
A wirewrap socket (
K1 ) is located on the board to configure Monoboard
Microcomputer 1 for operation with the EXORciser's Debug Module (EXbug
program). When operation with the Debug Module is desired, the VUA signal is
supplied by the Debug Module and the jumper connections required are shown in
note A. When the Debug Module is not used,the V UA signal must be the same as th e
VMA signal generated by the MPU. Therefore, the jumper
co nnections required are
shown in note B.
Kl Kl
i if - .,J --, "'CROPRoc'sseR 1- - - - -1 "'C ROP ROC,sse R
MICROMODULE 1 3 § I VMA MICROMOOULE ~ 3 VM A
VM A I _ I VMA I I
i I _ ,. MICRQMODU LE ~ MI CR DMDOULE
DEBUG ~ 0 -E I VUA MICRQMOOULE I 61 VUA
VUA L~_~ _ .J VUA L.:_~ __ ..J
MICROPROCESSOR MIC R OPROCESSO A
V"A V"A
NOTE A NOTE B
2.5.2.2 Operating wi th External Memory Devices
Externalmemory devices ca nbe used in place of the four on-board E ROM devices by
cutting the printed circuit wiring between terminals ( E1 / E3 and E2/ E4 )on the boa rd .These
terminal s also permit the user to use jumper wires to reconnect the ci r cuit for using the
on-board EROM devices. Th is change is pr esented in schematic form in note A and in
hardware form in note 8 .
U"
El E3 U23
PROM EFiA:2
E2 E4
CUT
TRACK
NO
TE A
2-3
COMPONENT SIDE VIEW
U13 E4 El
.......
CU T
TRA CK
NOTE B
U"
1

2.5.2.3 Operating With Optionallnpul Configura tion
As de li ve red. the sec tion B per iph eral data lin es (PSO-PB7) of the three PI As
(U20, U21 and U22) are configured as out put s. Data lin es PB4 through PB 7 of PIA2
and PBO through PB 7 of PIA3, however, may be re configured as inputs by replacing
the socket mounted MC7400 devices (U 30 , U31 and U33) with MC7402 devices and
connecting jumper wir es to wire-w rap socket K3 as shown be l ow .
PIA2
P64 -P87
.3
r-----
I
I E5 E4
I
I ~5 E4
L ___ _
PB4 -
PB1
1
.., PIAJ
'-7
1
--- peO -PBl
E3 I
I
E3 I
-.J
2.5.3 PIA PROGRAMMING INFORMATION
The MPU addr esses th ePIAs as if they were memory.Therefore,allcommands to
the PI As are executed by the MPU as memory reference instructions. The M6800
Microprocessor Ap plications Manual illustrat es the PI A addr ess i ng and the
operation being perf or med on the se lected PIA register. Note that bit 2 of the PIA
co ntrol r eg ist er is u sed to specify either the PIA'speripheral interface registers or the
data direction register.Theproperstate of the CRA2 and CRB2 bit must be loaded into the
cor re spo nding PIA con trol register before addressing i ts peripheral interface or direction
register. For additional PIA programming information and consideration s, refer to the
M6800 Microprocessor Applications Manual.
2-4

2.5.4 I RQ (INTERRUPT REQUEST) AND INTERRUPT PR IORITIES
Monobo a rd Microcomputer 1 h as seven pot en t ia l so urces of generating an IR Q
input to the MPU;two from each of the thr ee PIAs (depen ding on theuser's program)
a nd an a va il able user input on the control bus. The MPU completes th e instruction it
is executing before it recogniz es an IRQ input. Then, if the interrupt mask bit in the
MPU's
condition code register is not se t, the MPU reads the vector address of the
user's I RQ routine in memory locations CFF8 and CFF9 .
If you are using more than one peripheral device capable of interrupting th e
MPU, you mu st prepare a software interrupt polling ro utine to interrogate each of
these devices and determine
th e device initiating the interrupt. This polling rout in e,
on determining
th e I RQ initiated device, cau ses the MPU to vector to th e appropriate
service routine.
In preparing th e interrogation routine, you must assign priorities to the devices
by assigning their position in th e in terrogation polling routine. The device
interrogated first has the highest priority and the device interrogated last has the
lowest priority.
2 .6 MODULE INTERCONNECTIONS
Monoboa rd Mic ro computer 1 is bus compatible with either th e Micromodule bus
or the EXORciser bus. These bus signals are identified in Table 2 -1 . Thi s table lists
each pin connection, signal mnemonic, and signal characteristic. Tables 2-2 through
2-4 identify th e various PIA interface signals.
2-5

Table 2- 1. Conn eclor P1 Bus Inlerface Si gn als
PIN SIGNAL
NUMBER MNEMONICS SIGNAL NAME ANDDESCRIPTION
A.B.C
+5 VDC +5 Vdc -Used lor Ihe module's
logic circuits.
- -
D IRQ INTERRUPTREQUEST -This l
ow level
sensitive input signal requests that aMPU
interrupt sequence be generated within the
machine . The MPU will wail unlil il compleles
the
instruction being executed before
it recognizes the request. At that time,
if
Ihe inlerrupl mask bit in the MPU
condition code register is not set, the
MPU will begin the
interrupt sequence.
E NMI
NQN-MASKABLE INTERRUPT-This l ow-
going edgesensitive in put signal
requests thata non-maskable interrupt
be generated within the machin e. The MPU
will wait unti l it completes thein struct ion
being executed before it recognizes
the NMI
Sig nal. At thattime,the MPU
will begin its non-maskable interrupt
sequence.
F VMA VA
LID MEMORYADDRESS - Thisoutput
is available, jumper- selected,when Monoboard
Microcomputer 1 is used with the EXORciser
Debug Module to indicate that there is a
va lid memory addresson the address bus.
This pin is
not used when Monoboard
Microcomputer 1is not configured for
operation with the Debug Module.
H
Nol Used.
J
</>2
Phase 2 clock signal.
K
Not Used.
L MEMCLK MEMORY
CLOCK -This signal is an
ungated TTL le vel</>2 clock used to refresh
any
dynamic memory used in the system
M
-12VDC -12 Vdc - Used to generate
the -5 Vdc required
by the Erasable
Read
ani
y Memories (EROM's).
2-6 _
..

•
PIN
NUMBER
N
P
R ,S
T
U-z
A-F
H
J
K
L
M
N
P
Table 2-1 . Connector P1 Bus Interface Signals (Contd)
SIGNAL
MNEMONICS SIGNAL NAME AND DESCRIPTION
BA
+12 VDe
07
0 2
06
A14
A13
A10
Not Used
BUS AVAILABLE- Thisoutput signal
will
normally be a low level. When
activated,it will
go high indicating
the MPU has halted and theaddress
busis availabl
e. Thiswill occur if
the
Go /Halt line is in the Halt
(low) state
or the MPU is in the Wa it
state as a result of executing a Wait
instruction. At such time,all the MPU
thr ee-state output dr iverswill go
totheiro ff (high imp edance) state
and oth er outpu ts to their normally
inacti ve state. Amaskable interrupt
or
non-maskable interrupt removes the
MPU from the Wait state.
Not Used
+ 12 Vdc -Used by the Erasable Read On ly
Memories (EROM's).
Not Used.
Not Used.
DATA bus (bit 3) - Thi s bi-directionalline ,
when ena bl ed , prov id es a two-way data
transfer
between Monoboard Microcomputer 1
and any
ot h er plug- in modules in the system.
DATA bus (bit 7) -Same as 03 on P1-H.
D ATA bus (bit2) -Same as 03 on P1-H.
DATA bus (bit 6) -Same as 03 on P1-H.
ADDRE
SS bus ( bit 14 )-Th iso ut put
addr ess line,when enabled,allows
the MPU to addressanyexternal memory
locations used in the system.
ADDRE SS bus (bit 13) -Same as A 14 on P1-M.
ADDRE
SS bus (bit 10) -Same as A 14 on P1-M.
2-7

Table 2-1. Connec tor P1 Bus In ter face Signals (Contd)
PIN SIGNAL
NUMBER MNEMONICS
SIGNAL NAME AND DESCRIPTION
11
A9 ADDRESS bus (bit9) -Same as A 14 on P1 -M.
- -
S A6 ADDRESS bus (bit6) -Same as A
14 on P1-M.
--
T A5 ADDRESS bus (bit 5) -Same as A 14 on P1-M.
--
U A2 ADDRESS bus (bit 2) - Same as A
14 on P1-M.
- -
V A1 ADDRESS bus (bit 1) - Same asA 14 on P1-M.
--
-
W, X, Y COM
COMMON (ground)
1, 2, 3 +5 VDC +5Vdc -Used
for the modules's logic
circuits.
4 G/H
GO / HA LT -When this input is in the high
state,the MPU will fetch the instruction
addressed by the program counter and start
execution. When l ow ,a ll activity in the MP U
w il l be halted.This input is l eve l sens it ive.
In the Halt mode ,the MPU will stopatthe
end of an instruction, Bus Available will be
at a high level,Valid Memory Address will be
at al ow l ev el, and a ll other three-state
li nes will be in their off or high impedance
state.
T he Halt li ne must go low with the
l
eading edge of the phase one clock
( cJ>1 )to in su re single instruction operation.
lit he Haltline does not go low with the
leading edge of the phase one clock ,
one or two instruction ope ra ti ons may
result, depending on when the halt line
goes l ow re lative to the phasing of the
clock.
5 RESET RESET -
Th is buffered inp ut/ output signal,
when used as an output ,provides Mo noboard
Mi crocomputer 1reset circuit output to
any external devices r equ iring a Reset
signal. An external switch closure to
ground may be applied to this pin to
restart
Monoboard Microcomputer 1.
6 R/W READIWRI
TE - This MPU output signal
indicates to any externa l plug-in modules
2-8

Table 2-1. Connector P1 Bus Interface Signals (Contd)
PIN
SIGNAL
NUMBER
MNEMONICS SIGNAL NAME AND DESCRIPTION
6 whether the MC6800 MPU is perform ing
(
contd)
a memory read (high) or wr ite (low) operation.
T he normal standby state of this signal is
read (high) .Also,when the MC6800 is
halted , this signa l will be in the read state.
7, 8, 9 Not Used.
10 VUA VALID USER' SADDRESS -When
Monoboard Microcomputer 1 is not being
used with the EXORciser Debug Module ,
this pin is connected wit h a jumperto
the buffered Va lid Memory Address (VMA)
signal. When Mo n oboa rd Microcomputer 1 is
con fi gured for use wi th the Debug Module,
VUA is supplied as an input by the Debug
Module .
11 -12 VDC
-12 Vdc -Same as -12 Vdc on P1-M.
12 REFREQ REFRESH REQUEST-
Thi s input signal,
when low , initiates a memory refresh cy cle of the
dynam ic memory modu les. During the refresh
operation , the clock c ir cuit is inhibited
from generating its </> 1 and</>2 MPU cl ock
signals but still generates the MEMCLK
signal.
13 REF GRA
NT REFRESH GRANT - This output signal,
when high, instructs t he dynamic memo ry
mod
ul es to refresh their memories.
14, 15 Not Used
16 +12 VDC +12Vdc-Sameas +12
Vdc on P1-T.
17-28 Not Used
--
29
D1 DATA bus (bit 1) -Sameas D3 on P1-H.
-
30 D5 DA TA bus (bit 5) -Sameas D3on P1-H.
--
31
DO DATA bus (bit0) -Same as D3 on P1-H.
--
32 D4
DATA bus (b it4 ) -Sameas D30n P1-H. -
33
A15 ADDRE
SS bus (bit 15) -Sameas A14on P1-M.
2-9

Table 2-1. Connector P1 Bus Interface Signals (Contd)
PIN SIGNAL
NUMBER MNEMONICS
SIGNALNAME AND DESCRIPTION
34 A12 ADDRESS bus (bit 12) -Same as A 140n P1-M.
35
A11 ADDRESS bus (biI11) -Sameas A 140n P1-M.
36
A8 ADDRESS bus (bit 8) -Same asA 140n P1-M.
37 A7 ADDRESS bus
(bit 7) -Same asA 140n P1-M.
38 A4 ADDRESS bus
(bit 6) -Same as A 140n P1-M.
39 A3 ADDRESS bus
(bit 3) -Sameas A 140n P1-M.
40 AO
ADDRESS bus (bitO) -Sameas A 14 on P1-M.
41 42 43 COM COMMON (aroundl
2-10

PIN
NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
Table 2-2 Conn ec lor P2 PIA Inlerf ace Siqna s
SIGNAL
MNEMONICS SIGNAL NAME AND DESCRIPTION
PAO-1 PERIPHERALdata line(section A,
GND
PA1-1
GND
PA2 -1
GND
PA3-1
GND
PA4 -1
GND
PA5-1
GND
PA6-1
bit 0, PIA 1) - This peripheral data line in
SectionA of
PI A1 (U20) can be programmed
to act either as an input line or as an ou tput
line.A "0" in bit 0of the A data direct ion
registercauses this
li ne to function as an
input and a"1" ca u ses this line tofunction
as an o ut put.
GROUND - Signal return lin e.
PERIPHERALdata line (Section A,
bit 1,PIA1)- Same
as P AO-1 on pin 1except
bit 1of theA datadirection register
controls this line.
GROUND -Signal re turn line.
PER I PH ERALdata line (Section 1,
bit 2,PIA 1) -Same as PAO-1 on pin 1
except bit2
of theAdata direction
register cont rols this line.
GROUND -Signal return line.
PERIPHERALdata line (Section A,
bit 3,PIA 1) -Same as PAO-1 on pin 1
except bit3
of the A data direction
register co ntrols this line.
GROUND -Signal return line.
PERIPHERALdata line (Section A,
bit4,PIA1) - Same
as P AO- 1 on pin 1
except
bit 4 of the A datadirection
register controls this line.
GROUND - Signal return line.
PERIPHERALdata line (Section A,
bit5,PIA1)- Same
as P AO- 1on pin 1
except bit 5
of the A data direction
register controls thi s line.
GROUND -Sign al re turn line.
PER IPHERALdata line (Section A,
bit6 ,PIA1) - Sa me as P AO- 1on pin 1
2
-11