NEC mPD98410 User manual

Document No. S12523EJ2V0UMJ1 (2nd edition)
Date Published October 2000 N CP(K)
Printed in Japan
1998©
User’s Manual
µ
µµ
µ
PD98410
(NEASCOT-X10™)
1.2G ATM SWITCH LSI

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NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimatelydegradethedeviceoperation. Stepsmustbetakentostopgenerationofstaticelectricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulatorsthateasilybuildstaticelectricity. Semiconductordevicesmustbestoredandtransported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wriststrap. Semiconductordevicesmustnotbetouchedwith barehands. Similar precautionsneed
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
totheinputpins, it is possible that aninternalinputlevelmaybegenerated due to noise, etc., hence
causingmalfunction. CMOSdevicesbehave differentlythanBipolarorNMOS devices. Inputlevels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

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NEASCOT-X10 is a trademark of NEC Corporation.
The export of this product from Japan is prohibited without governmental license. To export or re-export this product from
a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
M8E 00.4
The information in this document is current as of October, 1998. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
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PREFACE
Readers This manual is intended for user engineers who wish to understand the functions of
the
µ PD98410 and design application systems using it.
Purpose This manual explains the hardware functions of the
µ PD98410 in the following
organization.
Organization This manual consists of the following chapters.
• General
• Pin functions
• Functional outline
• Internal registers
• JTAG boundary scan
• Limitations
• FAQ (Frequency Asked Questions)
How to Read This Manual It is assumed that the readers of this manual have a general knowledge of electricity,
logic circuits, and microcomputers.
To understand the overall functions of the µ PD98410
→Read this manual in the order of Table of Contents.
If you have any questions about the operation of the µ PD98410
→Read CHAPTER 7 FAQ (Frequently Asked Questions).
Conventions Data significance : Left: high-order digit, right: low-order digit
Active low : ×××_B (_B following pin or signal name)
Memory map address : Top: high-order, bottom: low-order
Note : Explanation of part of text marked Note
Caution : Important information
Remark : Supplementary information
Numeric notation : Binary ... ×××× or ×××B
Decimal ... ××××
Hexadecimal ... ××××H
Related documentation Some of the related documents are preliminary editions but are not so specified
below.
• Pamphlet : S12131E
• Data sheet : S12624E
• Application Note: S13107E

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CONTENTS
CHAPTER 1 GENERAL........................................................................................................................ 15
1.1 Features................................................................................................................................................ 15
1.2 Ordering Information ........................................................................................................................... 15
1.3 Example of System Configuration (Application)............................................................................... 16
1.4 Block Diagram...................................................................................................................................... 17
1.5 Pin Configuration................................................................................................................................. 18
CHAPTER 2 PIN FUNCTIONS............................................................................................................. 19
2.1 Pin Configuration (Bottom View)........................................................................................................ 19
2.2 Pin Layout............................................................................................................................................. 21
2.3 Pin Functions ....................................................................................................................................... 27
2.3.1 Power supply............................................................................................................................... 27
2.3.2 UTOPIA interface........................................................................................................................ 28
2.4 Memory Interface Signals.................................................................................................................... 32
2.4.1 Microprocessor interface signals................................................................................................. 34
2.4.2 JTAG........................................................................................................................................... 36
2.4.3 Others ......................................................................................................................................... 36
2.5 Recommended Connections of Unused Pins.................................................................................... 37
2.6 Pin Status at Reset............................................................................................................................... 38
CHAPTER 3 FUNCTIONAL OUTLINE ................................................................................................39
3.1 UTOPIA Interfaces................................................................................................................................ 39
3.1.1 Input port interface...................................................................................................................... 40
3.1.2 Output port interface ................................................................................................................... 41
3.2 Polling................................................................................................................................................... 42
3.2.1 Outline of polling ......................................................................................................................... 42
3.2.2 Polling during cell output............................................................................................................. 44
3.2.3 Polling during cell input............................................................................................................... 50
3.3 Header Translation............................................................................................................................... 56
3.3.1 HTT (Header Translation Table) memory map ........................................................................... 56
3.3.2 General ....................................................................................................................................... 57
3.3.3 Format of HTT............................................................................................................................. 60
3.3.4 Accessing HTT............................................................................................................................ 63
3.3.5 Flow of header translation........................................................................................................... 68
3.3.6 Accessing HTT with RM cell ....................................................................................................... 72
3.4 Queue Control ...................................................................................................................................... 75
3.4.1 Single cast................................................................................................................................... 75
3.4.2 Multi-cast..................................................................................................................................... 76
3.4.3 Congestion control...................................................................................................................... 77
3.4.4 Cell discard by class................................................................................................................... 81
3.4.5 EPD (Early Packet Discard) control............................................................................................ 82
3.4.6 PPD (Partial Packet Discard) control.......................................................................................... 84
3.4.7 Minimum queue length................................................................................................................ 85

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3.5 ABR Congestion Control ..................................................................................................................... 88
3.5.1 EFCI (Explicit Forward Congestion Indicator)............................................................................. 88
3.5.2 RM cell CI/NI marking (Resource Management Cell CI/NI Congestion Indication Marking)....... 88
3.5.3 RM cell merge (Resource Management Cell Merge).................................................................. 89
3.6 WFQ (Weighted Fairness Queue)........................................................................................................ 90
3.6.1 General........................................................................................................................................ 90
3.6.2 Counters and flags used ............................................................................................................. 90
3.7 Peak Rate Shaping Function............................................................................................................... 93
3.7.1 General........................................................................................................................................ 93
3.7.2 Details ......................................................................................................................................... 95
3.8 Successive Transmission ................................................................................................................... 99
3.9 Interrupt Request.................................................................................................................................. 103
3.9.1 Parity error................................................................................................................................... 103
3.9.2 Input port overrun........................................................................................................................ 103
3.9.3 Queue pointer error..................................................................................................................... 103
3.9.4 Cast count error........................................................................................................................... 104
3.9.5 Cell buffer memory shortage....................................................................................................... 104
3.9.6 Control memory shortage............................................................................................................ 104
3.9.7 HEC/CRC error............................................................................................................................ 104
3.9.8 Header translation error .............................................................................................................. 105
3.9.9 Exceeding buffer threshold value................................................................................................ 105
3.9.10 Count over detection................................................................................................................. 105
3.10 Monitoring............................................................................................................................................. 106
3.10.1 Monitor register ......................................................................................................................... 106
3.10.2 Cell discard count due to exceeded threshold value................................................................. 106
3.10.3 Cell discard count due to header translation error.................................................................... 106
3.10.4 Cell discard count due to HEC error or CRC error.................................................................... 107
3.10.5 Cell discard count due to control/cell buffer memory shortage ................................................. 107
3.10.6 Counting number of received cells............................................................................................ 108
3.11 Microprocessor Interface..................................................................................................................... 109
3.11.1 I/O mapping and memory mapping........................................................................................... 110
3.11.2 32-bit multiplexed synchronous bus (HSEL = Low)................................................................... 113
3.11.3 16-bit separated asynchronous bus (HSEL = High).................................................................. 115
3.12 External Memory Interface................................................................................................................... 118
3.12.1 HTT & control memory interface................................................................................................ 118
3.12.2 Cell buffer interface................................................................................................................... 119
CHAPTER 4 INTERNAL REGISTERS................................................................................................. 123
4.1 Register List.......................................................................................................................................... 123
4.2 Register Map......................................................................................................................................... 125
4.3 Register Functions............................................................................................................................... 133
4.3.1 Command register (0000h)........................................................................................................... 133
4.3.2 Memory bank register (0004h) .................................................................................................... 134
4.3.3 Memory mode register (0006h)................................................................................................... 134
4.3.4 Interrupt mask register (0008h)................................................................................................... 136
4.3.5 Status register (000Ch)............................................................................................................... 137
4.3.6 Threshold value exceeding discard indication mask register (0010h)......................................... 139
4.3.7 Threshold value exceeding discard indication register (0014h).................................................. 139

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4.3.8 Header translation error discard indication register (0018h)....................................................... 142
4.3.9 HEC/CRC error discard indication register (001Ah).................................................................... 144
4.3.10 Input port overrun error discard indication register (001Ch) ..................................................... 145
4.3.11 Threshold value exceeding discard cell count enable register (0020h).................................... 146
4.3.12 Header translation error discard cell count enable register (0024h)......................................... 147
4.3.13 HEC/CRC error discard cell count enable register (0026h) ...................................................... 148
4.3.14 Control/cell buffer memory shortage discard cell count enable register (0028h)...................... 149
4.3.15 Receive cell count enable register (002Ah).............................................................................. 150
4.3.16 Receive cell count register (002Ch).......................................................................................... 151
4.3.17 Threshold value exceeding discard cell count register (0030h)................................................ 152
4.3.18 Header translation error discard cell count register (0034h)..................................................... 153
4.3.19 HEC/CRC error discard cell count register (0038h).................................................................. 154
4.3.20 Control/cell buffer memory shortage discard cell count register (003Ch)................................. 155
4.3.21 Output queue minimum threshold value registers (0040h, 0044h, 0048h, 004Ch)................... 156
4.3.22 Multi-cast queue minimum threshold value registers (0050h, 0054h, 0058h, 005Ch).............. 157
4.3.23 TC (Total Cell) counter minimum threshold registers (0060h, 0064h, 0068h, 006Ch).............. 158
4.3.24 Total number of cells minimum threshold value register (007Eh)............................................. 159
4.3.25 Output queue maximum threshold value registers
(0080h, 0082h, 0090h, 0092h, 00A0h, 00B0h)......................................................................... 160
4.3.26 Output queue EPD threshold value registers (00A2h, 00B2h).................................................. 161
4.3.27 Output queue EFCI threshold value registers (0094h, 00A4h, 00B4h)..................................... 162
4.3.28 Output queue CLP threshold value registers (0086h, 0096h, 00A6h, 00B6h).......................... 163
4.3.29 Multi-cast queue maximum threshold value registers (00C0h, 00C4h, 00C8h, 00CCh)........... 164
4.3.30
UC (Used Cell) counter maximum threshold value register
(00D0h, 00D4h, 00D8h, 00DCh, 00E0h, 00E8h)
........................................................................ 165
4.3.31 UC (Used Cell) Counter EPD threshold value registers (00E2h, 00EAh)................................. 166
4.3.32 Port configuration register......................................................................................................... 167
4.3.33 Class priority control register..................................................................................................... 169
4.3.34 Cycle count register (01FCh).................................................................................................... 170
4.3.35 Header translation configuration register.................................................................................. 171
CHAPTER 5 JTAG BOUNDARY SCAN............................................................................................. 173
5.1 Features................................................................................................................................................ 173
5.2 Internal Configuration of Boundary Scan Circuit.............................................................................. 174
5.2.1 Instruction register....................................................................................................................... 174
5.2.2 TAP (Test Access Port) controller............................................................................................... 174
5.2.3 Bypass register ........................................................................................................................... 174
5.2.4 Boundary scan register............................................................................................................... 174
5.3 Pin Function ......................................................................................................................................... 175
5.3.1 JCK (JTAG Clock) pin................................................................................................................. 175
5.3.2 JMS (JTAG Mode Select) pin...................................................................................................... 175
5.3.3 JDI (JTAG Data Input) pin........................................................................................................... 175
5.3.4 JDO (JTAG Data Output) pin ...................................................................................................... 175
5.3.5 JRST_B (JTAG Reset) pin.......................................................................................................... 175
5.4 Operation Description.......................................................................................................................... 176
5.4.1 TAP controller ............................................................................................................................. 176
5.4.2 TAP controller state..................................................................................................................... 176

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5.5 TAP Controller Operation.................................................................................................................... 181
5.6 Initializing TAP Controller.................................................................................................................... 184
5.7 Instruction Register.............................................................................................................................. 184
5.7.1 BYPASS instruction..................................................................................................................... 185
5.7.2 EXTEST instruction..................................................................................................................... 185
5.8 Boundary Scan Data Bit Definition..................................................................................................... 185
CHAPTER 6 LIMITATIONS................................................................................................................... 187
6.1 Limitations ............................................................................................................................................ 187
6.2 Description of Limitations................................................................................................................... 188
CHAPTER 7 FAQ (Frequently Asked Questions)............................................................................. 195