NEC mPD98410 User manual

Document No. S12523EJ2V0UMJ1 (2nd edition)
Date Published October 2000 N CP(K)
Printed in Japan
1998©
User’s Manual
µ
µµ
µ
PD98410
(NEASCOT-X10™)
1.2G ATM SWITCH LSI

2
[MEMO]

3
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimatelydegradethedeviceoperation. Stepsmustbetakentostopgenerationofstaticelectricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulatorsthateasilybuildstaticelectricity. Semiconductordevicesmustbestoredandtransported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wriststrap. Semiconductordevicesmustnotbetouchedwith barehands. Similar precautionsneed
to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
totheinputpins, it is possible that aninternalinputlevelmaybegenerated due to noise, etc., hence
causingmalfunction. CMOSdevicesbehave differentlythanBipolarorNMOS devices. Inputlevels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.

4
NEASCOT-X10 is a trademark of NEC Corporation.
The export of this product from Japan is prohibited without governmental license. To export or re-export this product from
a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
M8E 00.4
The information in this document is current as of October, 1998. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
•
•
•
•
•
•

5
PREFACE
Readers This manual is intended for user engineers who wish to understand the functions of
the
µ PD98410 and design application systems using it.
Purpose This manual explains the hardware functions of the
µ PD98410 in the following
organization.
Organization This manual consists of the following chapters.
• General
• Pin functions
• Functional outline
• Internal registers
• JTAG boundary scan
• Limitations
• FAQ (Frequency Asked Questions)
How to Read This Manual It is assumed that the readers of this manual have a general knowledge of electricity,
logic circuits, and microcomputers.
To understand the overall functions of the µ PD98410
→Read this manual in the order of Table of Contents.
If you have any questions about the operation of the µ PD98410
→Read CHAPTER 7 FAQ (Frequently Asked Questions).
Conventions Data significance : Left: high-order digit, right: low-order digit
Active low : ×××_B (_B following pin or signal name)
Memory map address : Top: high-order, bottom: low-order
Note : Explanation of part of text marked Note
Caution : Important information
Remark : Supplementary information
Numeric notation : Binary ... ×××× or ×××B
Decimal ... ××××
Hexadecimal ... ××××H
Related documentation Some of the related documents are preliminary editions but are not so specified
below.
• Pamphlet : S12131E
• Data sheet : S12624E
• Application Note: S13107E

6
[MEMO]

7
CONTENTS
CHAPTER 1 GENERAL........................................................................................................................ 15
1.1 Features................................................................................................................................................ 15
1.2 Ordering Information ........................................................................................................................... 15
1.3 Example of System Configuration (Application)............................................................................... 16
1.4 Block Diagram...................................................................................................................................... 17
1.5 Pin Configuration................................................................................................................................. 18
CHAPTER 2 PIN FUNCTIONS............................................................................................................. 19
2.1 Pin Configuration (Bottom View)........................................................................................................ 19
2.2 Pin Layout............................................................................................................................................. 21
2.3 Pin Functions ....................................................................................................................................... 27
2.3.1 Power supply............................................................................................................................... 27
2.3.2 UTOPIA interface........................................................................................................................ 28
2.4 Memory Interface Signals.................................................................................................................... 32
2.4.1 Microprocessor interface signals................................................................................................. 34
2.4.2 JTAG........................................................................................................................................... 36
2.4.3 Others ......................................................................................................................................... 36
2.5 Recommended Connections of Unused Pins.................................................................................... 37
2.6 Pin Status at Reset............................................................................................................................... 38
CHAPTER 3 FUNCTIONAL OUTLINE ................................................................................................39
3.1 UTOPIA Interfaces................................................................................................................................ 39
3.1.1 Input port interface...................................................................................................................... 40
3.1.2 Output port interface ................................................................................................................... 41
3.2 Polling................................................................................................................................................... 42
3.2.1 Outline of polling ......................................................................................................................... 42
3.2.2 Polling during cell output............................................................................................................. 44
3.2.3 Polling during cell input............................................................................................................... 50
3.3 Header Translation............................................................................................................................... 56
3.3.1 HTT (Header Translation Table) memory map ........................................................................... 56
3.3.2 General ....................................................................................................................................... 57
3.3.3 Format of HTT............................................................................................................................. 60
3.3.4 Accessing HTT............................................................................................................................ 63
3.3.5 Flow of header translation........................................................................................................... 68
3.3.6 Accessing HTT with RM cell ....................................................................................................... 72
3.4 Queue Control ...................................................................................................................................... 75
3.4.1 Single cast................................................................................................................................... 75
3.4.2 Multi-cast..................................................................................................................................... 76
3.4.3 Congestion control...................................................................................................................... 77
3.4.4 Cell discard by class................................................................................................................... 81
3.4.5 EPD (Early Packet Discard) control............................................................................................ 82
3.4.6 PPD (Partial Packet Discard) control.......................................................................................... 84
3.4.7 Minimum queue length................................................................................................................ 85

8
3.5 ABR Congestion Control ..................................................................................................................... 88
3.5.1 EFCI (Explicit Forward Congestion Indicator)............................................................................. 88
3.5.2 RM cell CI/NI marking (Resource Management Cell CI/NI Congestion Indication Marking)....... 88
3.5.3 RM cell merge (Resource Management Cell Merge).................................................................. 89
3.6 WFQ (Weighted Fairness Queue)........................................................................................................ 90
3.6.1 General........................................................................................................................................ 90
3.6.2 Counters and flags used ............................................................................................................. 90
3.7 Peak Rate Shaping Function............................................................................................................... 93
3.7.1 General........................................................................................................................................ 93
3.7.2 Details ......................................................................................................................................... 95
3.8 Successive Transmission ................................................................................................................... 99
3.9 Interrupt Request.................................................................................................................................. 103
3.9.1 Parity error................................................................................................................................... 103
3.9.2 Input port overrun........................................................................................................................ 103
3.9.3 Queue pointer error..................................................................................................................... 103
3.9.4 Cast count error........................................................................................................................... 104
3.9.5 Cell buffer memory shortage....................................................................................................... 104
3.9.6 Control memory shortage............................................................................................................ 104
3.9.7 HEC/CRC error............................................................................................................................ 104
3.9.8 Header translation error .............................................................................................................. 105
3.9.9 Exceeding buffer threshold value................................................................................................ 105
3.9.10 Count over detection................................................................................................................. 105
3.10 Monitoring............................................................................................................................................. 106
3.10.1 Monitor register ......................................................................................................................... 106
3.10.2 Cell discard count due to exceeded threshold value................................................................. 106
3.10.3 Cell discard count due to header translation error.................................................................... 106
3.10.4 Cell discard count due to HEC error or CRC error.................................................................... 107
3.10.5 Cell discard count due to control/cell buffer memory shortage ................................................. 107
3.10.6 Counting number of received cells............................................................................................ 108
3.11 Microprocessor Interface..................................................................................................................... 109
3.11.1 I/O mapping and memory mapping........................................................................................... 110
3.11.2 32-bit multiplexed synchronous bus (HSEL = Low)................................................................... 113
3.11.3 16-bit separated asynchronous bus (HSEL = High).................................................................. 115
3.12 External Memory Interface................................................................................................................... 118
3.12.1 HTT & control memory interface................................................................................................ 118
3.12.2 Cell buffer interface................................................................................................................... 119
CHAPTER 4 INTERNAL REGISTERS................................................................................................. 123
4.1 Register List.......................................................................................................................................... 123
4.2 Register Map......................................................................................................................................... 125
4.3 Register Functions............................................................................................................................... 133
4.3.1 Command register (0000h)........................................................................................................... 133
4.3.2 Memory bank register (0004h) .................................................................................................... 134
4.3.3 Memory mode register (0006h)................................................................................................... 134
4.3.4 Interrupt mask register (0008h)................................................................................................... 136
4.3.5 Status register (000Ch)............................................................................................................... 137
4.3.6 Threshold value exceeding discard indication mask register (0010h)......................................... 139
4.3.7 Threshold value exceeding discard indication register (0014h).................................................. 139

9
4.3.8 Header translation error discard indication register (0018h)....................................................... 142
4.3.9 HEC/CRC error discard indication register (001Ah).................................................................... 144
4.3.10 Input port overrun error discard indication register (001Ch) ..................................................... 145
4.3.11 Threshold value exceeding discard cell count enable register (0020h).................................... 146
4.3.12 Header translation error discard cell count enable register (0024h)......................................... 147
4.3.13 HEC/CRC error discard cell count enable register (0026h) ...................................................... 148
4.3.14 Control/cell buffer memory shortage discard cell count enable register (0028h)...................... 149
4.3.15 Receive cell count enable register (002Ah).............................................................................. 150
4.3.16 Receive cell count register (002Ch).......................................................................................... 151
4.3.17 Threshold value exceeding discard cell count register (0030h)................................................ 152
4.3.18 Header translation error discard cell count register (0034h)..................................................... 153
4.3.19 HEC/CRC error discard cell count register (0038h).................................................................. 154
4.3.20 Control/cell buffer memory shortage discard cell count register (003Ch)................................. 155
4.3.21 Output queue minimum threshold value registers (0040h, 0044h, 0048h, 004Ch)................... 156
4.3.22 Multi-cast queue minimum threshold value registers (0050h, 0054h, 0058h, 005Ch).............. 157
4.3.23 TC (Total Cell) counter minimum threshold registers (0060h, 0064h, 0068h, 006Ch).............. 158
4.3.24 Total number of cells minimum threshold value register (007Eh)............................................. 159
4.3.25 Output queue maximum threshold value registers
(0080h, 0082h, 0090h, 0092h, 00A0h, 00B0h)......................................................................... 160
4.3.26 Output queue EPD threshold value registers (00A2h, 00B2h).................................................. 161
4.3.27 Output queue EFCI threshold value registers (0094h, 00A4h, 00B4h)..................................... 162
4.3.28 Output queue CLP threshold value registers (0086h, 0096h, 00A6h, 00B6h).......................... 163
4.3.29 Multi-cast queue maximum threshold value registers (00C0h, 00C4h, 00C8h, 00CCh)........... 164
4.3.30
UC (Used Cell) counter maximum threshold value register
(00D0h, 00D4h, 00D8h, 00DCh, 00E0h, 00E8h)
........................................................................ 165
4.3.31 UC (Used Cell) Counter EPD threshold value registers (00E2h, 00EAh)................................. 166
4.3.32 Port configuration register......................................................................................................... 167
4.3.33 Class priority control register..................................................................................................... 169
4.3.34 Cycle count register (01FCh).................................................................................................... 170
4.3.35 Header translation configuration register.................................................................................. 171
CHAPTER 5 JTAG BOUNDARY SCAN............................................................................................. 173
5.1 Features................................................................................................................................................ 173
5.2 Internal Configuration of Boundary Scan Circuit.............................................................................. 174
5.2.1 Instruction register....................................................................................................................... 174
5.2.2 TAP (Test Access Port) controller............................................................................................... 174
5.2.3 Bypass register ........................................................................................................................... 174
5.2.4 Boundary scan register............................................................................................................... 174
5.3 Pin Function ......................................................................................................................................... 175
5.3.1 JCK (JTAG Clock) pin................................................................................................................. 175
5.3.2 JMS (JTAG Mode Select) pin...................................................................................................... 175
5.3.3 JDI (JTAG Data Input) pin........................................................................................................... 175
5.3.4 JDO (JTAG Data Output) pin ...................................................................................................... 175
5.3.5 JRST_B (JTAG Reset) pin.......................................................................................................... 175
5.4 Operation Description.......................................................................................................................... 176
5.4.1 TAP controller ............................................................................................................................. 176
5.4.2 TAP controller state..................................................................................................................... 176

10
5.5 TAP Controller Operation.................................................................................................................... 181
5.6 Initializing TAP Controller.................................................................................................................... 184
5.7 Instruction Register.............................................................................................................................. 184
5.7.1 BYPASS instruction..................................................................................................................... 185
5.7.2 EXTEST instruction..................................................................................................................... 185
5.8 Boundary Scan Data Bit Definition..................................................................................................... 185
CHAPTER 6 LIMITATIONS................................................................................................................... 187
6.1 Limitations ............................................................................................................................................ 187
6.2 Description of Limitations................................................................................................................... 188
CHAPTER 7 FAQ (Frequently Asked Questions)............................................................................. 195

11
LIST OF FIGURES (1/2)
Figure No. Title Page
3-1 Example of Connecting UTOPIA Receive Interface...............................................................................40
3-2 Example of Connecting UTOPIA Transmit Interface..............................................................................41
3-3 Functional Blocks of µ PD98410 ............................................................................................................. 42
3-4 Clock Relation ........................................................................................................................................ 44
3-5 Single PHY Mode and Multi-PHY Mode................................................................................................. 44
3-6 Relationship between Polling Control and Basic Operation Cycle (in multi-PHY mode)........................ 45
3-7 Polling Operation during Cell Output...................................................................................................... 46
3-8 Polling Operation during Cell Output...................................................................................................... 47
3-9 Relationship between Polling Control and Basic Operation Cycle (single PHY mode).......................... 48
3-10 Control of Successive Output................................................................................................................. 49
3-11 Basic Operation of Polling during Cell Input........................................................................................... 50
3-12 Relationship between Polling Control and Basic Operation Cycle (during cell input)............................. 50
3-13 Basic Cell Input Timing 1........................................................................................................................ 51
3-14 Basic Cell Input Timing 2........................................................................................................................ 52
3-15 Drop in Transfer Rate during Successive Input...................................................................................... 52
3-16 Control of Successive Input.................................................................................................................... 53
3-17 HTT & Control Memory Map................................................................................................................... 56
3-18 Example of Single Cast .......................................................................................................................... 57
3-19 HTT (Header Translation Table)............................................................................................................. 57
3-20 Flow of Header Translation Information in Single-Cast Mode................................................................ 58
3-21 Example of Multi-Cast............................................................................................................................. 59
3-22 Flow of Header Translation Information in Multi-Cast Mode...................................................................59
3-23 HTT Area-A Format................................................................................................................................ 60
3-24 HTT Area-B Format................................................................................................................................ 62
3-25 VP Connection and VC Connection........................................................................................................ 63
3-26 Difference in Access to HTT between VPC and VCC (single cast)........................................................ 65
3-27 Calculating HTT Address........................................................................................................................ 66
3-28 Setting Format of OVPC......................................................................................................................... 67
3-29 Flow of Header Translation in VCC and Single Cast Modes.................................................................. 68
3-30 Flow of Header Translation in VCC and Multi-Cast Modes.................................................................... 69
3-31 Flow of Header Translation in VPC and Single Cast Modes.................................................................. 70
3-32 Flow of Header Translation in VPC and Multi-Cast Modes .................................................................... 71
3-33 Queuing of Cell Address (Single Cast)................................................................................................... 75
3-34 Queuing of Cell Address (Multi-Cast)..................................................................................................... 76
3-35 Queues and Counters by Service Class................................................................................................. 78
3-36 When EPD Control Is Enabled ............................................................................................................... 82
3-37 Status Transition When EOP Control Is Enabled................................................................................... 83
3-38 Status Transition of EPD Control............................................................................................................ 83
3-39 Status Transition of PPD Control............................................................................................................ 85
3-40 RM Cell Configuration (ATM Forum TM Ver. 4.0).................................................................................. 88
3-41 Output Queue and Counter .................................................................................................................... 90
3-42 Relationship between Internal Basic Cycle and Output Enable Timing of Each UTOPIA Interface....... 93
3-43 Example of Connection between µ PD98410 and Terminal.................................................................... 94
3-44 Polling Timing (a).................................................................................................................................... 100

12
LIST OF FIGURES (2/2)
Figure No. Title Page
3-45 Polling Timing (b)................................................................................................................................... 101
3-46 Polling Timing (c)................................................................................................................................... 102
3-47 I/O Register Mapping............................................................................................................................. 111
3-48 HTT & Control Memory and Cell Buffer Memory Mapping..................................................................... 112
3-49 Access Timing of 32-Bit Multiplexed Synchronous Bus......................................................................... 114
3-50 Access Timing of 16-Bit Separated Asynchronous Bus......................................................................... 116
3-51 Memory Map of 16-Bit Separated Asynchronous Bus........................................................................... 117
3-52 Example of Connecting HTT & Control Memory (minimum configuration) ............................................ 118
3-53 Example of Connecting HTT & Control Memory (maximum configuration) ........................................... 119
3-54 Cell Buffer Storage Format.................................................................................................................... 120
3-55 Example of Connecting Cell Buffer Memory.......................................................................................... 121
5-1 Block Diagram of Boundary Scan Circuit............................................................................................... 174
5-2 State Transition of TAP Controller......................................................................................................... 176
5-3 Operation Timing in Controller State...................................................................................................... 177
5-4 Operation of Test Logic (instruction scan)............................................................................................. 182
5-5 Operation of Test Logic (data scan)....................................................................................................... 183
7-1 Header Translation Flow (overall).......................................................................................................... 203
7-2 Header Translation Flow (reception side).............................................................................................. 204
7-3 Header Translation Flow (transmission side)......................................................................................... 205
7-4 Example of Setting HT Registers........................................................................................................... 206
7-5 Example of HTT Memory Mapping ........................................................................................................ 207

13
LIST OF TABLES
Table. No. Title Page
2-1 Receive Interface Signals....................................................................................................................... 28
2-2 Transmit Interface Signal........................................................................................................................ 30
2-3 HTT & Control Memory Interface Signals............................................................................................... 32
2-4 Cell Buffer Memory Interface Signals..................................................................................................... 33
2-5 Microprocessor Interface........................................................................................................................ 34
2-6 32-Bit Multiplexed Synchronous Interface.............................................................................................. 34
2-7 16-Bit Separated Asynchronous Interface.............................................................................................. 35
2-8 JTAG Interface Signals........................................................................................................................... 36
2-9 Other Interface Signals........................................................................................................................... 36
2-10 Recommended Connections of Unused Pins......................................................................................... 37
2-11 Pin Status at Reset................................................................................................................................. 38
3-1 Maximum Transfer Rate and UTOPIA Clock Rate ................................................................................. 39
3-2 Cell Discard Threshold Value Related to Total Number of Cells............................................................ 81
3-3 Cell Discard Threshold Value of Output Queue Length..........................................................................81
3-4 Cell Discard Threshold Values Related to Multi-Cast Queue Length..................................................... 82
3-5 Minimum Queue Length Related to Total Number of Cells (Used Cell Counter).................................... 85
3-6 Minimum Queue Length Related to Total Number of Cells of Each Class
(Total Cell Counter for each class)......................................................................................................... 85
3-7 Minimum Queue Length Related to Output Queue Length..................................................................... 86
3-8 Minimum Queue Length Related to Multi-Cast Queue........................................................................... 86
3-9 Classification and Names of Threshold Values...................................................................................... 87
3-10 EFCI Threshold Value Related to Output Queue ................................................................................... 88
3-11 CI Threshold Values Related to Output Queue Length..........................................................................89
3-12 PHY Device Connected and Mode Setting of µ PD98410....................................................................... 99
3-13 Microprocessor Interface Pin.................................................................................................................. 109
3-14 Selecting Subject to Access................................................................................................................... 110
3-15 Access Bit Width for Each Access Type................................................................................................. 110
5-1 Operation in Each Controller State......................................................................................................... 181

14
[MEMO]

15
CHAPTER 1 GENERAL
The µ PD98410 (NEASCOT-X10) is an LSI integrating ATM switch functions on a single chip. It has four UTOPIA
Level2 interfaces and can switch 24 ×24 circuits by connecting multiple PHY devices. This LSI employs a shared
buffer non-blocking type switch and realizes a switch capacity of 1.2G bps by using an externally connected SRAM
for buffering cells.
1.1 Features
• Conforms to ATM FORUM UNI Version 3.1 & 4.0
• Realizes all switch functions with a single chip
• Non-blocking type with switch capacity of 1.2G bps
• Can switch 24 logical ports via four UTOPIA Level2 (8 bits/40 MHz) interfaces
• Multi-speed (155M bps, 52M bps, 25M bps, etc.)
• Supports 16K/32K/64K VP/VC and 1K/2K/4K multi-cast VP/VC
• Shared buffer architecture using standard SRAM
• Cell buffer capacity: 12.8K/25.6K/51.2K cells
• Supports four QOS classes (CBR, VBR, ABR, UBR)
• ABR traffic control (binary mode)
• Supports EPD (Early Packet Discard) and PPD (Partial Packet Discard)
• +3.3-V single power source (directly connectable with +5-V TTL level signals)
• Test function: Supports JTAG (IEEE 1149.1)
1.2 Ordering Information
Part Number Package
µ PD98410S2-K6 580-pin plastic BGA (45 ×45 mm)

CHAPTER 1 GENERAL
16
1.3 Example of System Configuration (Application)
The µ PD98410 can be used to realize an ATM layer cell switching function by connecting it to a microprocessor,
SRAM for use as a cell buffer, and a header translation table (HTT)/SRAM for storing control information as shown
below.
Logical inport Logical outport
PHY #0 #0 PHY
#1 PHY
#2 PHY
#22 PHY
#23 PHY
PHY #1
PHY #2
PHY #22
PHY #23
8-bit
40 MHz
8-bit
33 MHz
32-bit
+parity 88-bit
8-bit
33 MHz
UTOPIA level 2
8-bit
40 MHz
UTOPIA level 2
UTOPIA level 2 UTOPIA level 2
Micro
processer
HTT &
control
memory Cell buffer (Memory )
HTT: Header Translation Table
Physical
inport
#0
Physical
outport
#0
#1 #1
#2 #2
#3 #3
PD98410
NEASCOT/X10
µ

CHAPTER 1 GENERAL
17
1.4 Block Diagram
UTOPIA
receive
port 0
UTOPIA
receive
port 1
UTOPIA
receive
port 2
UTOPIA
receive
port 3
UTOPIA
transmit
port 0
UTOPIA
transmit
port 1
UTOPIA
transmit
port 2
UTOPIA
transmit
port 3
Input port interface
Output interface
Microprocessor
interface
Output
arbiter
Output
header
selector
Input
header
selector
Microprocessor HTT & Control Memory TEST
HTT &
Control memory
interface
Test interface
Queue
controller
Input payload separator Output payload selector
Cell Buffer Memory
Cell buffer interface

CHAPTER 1 GENERAL
18
1.5 Pin Configuration
JDI
JDO
JCKJTAG
UTOPIA
Interface 3
UTOPIA
Interface 1
UTOPIA
Interface 2
UTOPIA
Interface 0
JMS
JRST_B
RXDATA3 [7:0]
TXDATA3 [7:0]
UCLK3
RXENB3_B
TXENB3_B
RXSOC3
TXSOC3
RXCLAV3
TXCLAV3
RXADDR3 [3:0]
RXDATA1 [7:0]
UCLK1
RXENB1_B
RXSOC1
RXCLAV1
RXADDR1 [3:0]
TXADDR3 [3:0]
TXDATA1 [7:0]
TXENB1_B
TXSOC1
TXCLAV1
TXADDR1 [3:0]
TXDATA2 [7:0]
TXENB2_B
TXSOC2
TXCLAV2
TXADDR2 [3:0]
TXDATA0 [7:0]
TXENB0_B
TXSOC0
TXCLAV0
TXADDR0 [3:0]
UCLK2
RXDATA2 [7:0]
RXENB2_B
RXSOC2
RXCLAV2
RXADDR2 [3:0]
UCLK0
RXDATA0 [7:0]
RXENB0_B
RXSOC0
RXCLAV0
RXADDR0 [3:0]
RDY_B/RDY
INT
HCLK
HSEL
CBCS_B [1:0] CBWE_B CBOE_B CBA [17:0] CBD [87:0]
RESET_B
SWCLK
HTD [31:0]
HTP [3:0]
HTOE_B
HTWE_B
HTCS_B [1:0]
HTA [17:0]
AD [15:0] /D [15:0]
AD [31:16] /A [15:0]
UWE_B/RD_B
R/W_B/WR_B
MCS_B
IOCS_B
Cell Buffer
Interface
Control
HTT &
Control Memory
Interface Microprocessor Interface
8
8
8
8
4
4
4
4
8
8
8
8
4
4
4
4
2
32 18 16 1642
18
88
PD98410 µ

19
CHAPTER 2 PIN FUNCTIONS
2.1 Pin Configuration (Bottom View)
580-pin BGA package
67
60
50
70
200
430
530
310
420
190
180
300
410
510
170
290
400
160
280
500 490 480
580 370
250
120
570
470
360
240
380
390
20
150 140
260
130
10 1
270
40
34 30
520
320
80
540
210
440
330
90
550
100
230
560 350
460
110
220
440
340
Index mark
Note
Note The index mark is shown in Top View.

CHAPTER 2 PIN FUNCTIONS
20
Pin name
(1) Power (4) CPU Interface
VDD : Supply Voltage HSEL : Host Bus Mode Select
GND : Ground IOCS_B : I/O Chip Select
MCS_B : Memory Chip Select
(2) UTOPIA RDY_B, RDY: I/O Ready, Memory Ready
RXADDR*3 - RXADDR*0: Receive Address INT : Interrupt Request
RXDATA*7 - RXDATA*0 : Receive Data Bus HCLK : Host Clock
RXSOC3 - RXSOC0 : Receive Start of Cell AD31 - AD0 : Address and Data
RXENB3_B - RXENB0_B: Receive Enable Data Transfers R/W_B : Read/Write
RXCLAV3 - RXCLAV0 : Receive Cell Buffer Available UWE_B : Upper Word Enable
UCLK3 - UCLK0 : UTOPIA Clock A15 - A0 : Address
TXADDR*3 - TXADDR*0 : Transmit Address D15 - D0 : Data
TXDATA*7 - TXDATA*0 : Transmit Data Bus WR_B : Write Strobe
TXSOC3 - TXSOC0 : Transmit Start of Cell RD_B : Read Strobe
TXENB3_B - TXENB0_B: Transmit Enable Data
TXCLAV3 - TXCLAV0 : Transmit Cell Buffer Available (5) JTAG
JDI : JTAG Data Input
(3) Memory Interface JDO : JTAG Data Output
HTA17 - HTA0 : HTT Memory Address JCK : JTAG Data Clock
HTD31 - HTD0 : HTT Memory Data Bus JMS : JTAG Mode Select
HTP3 - HTP0 : HTT Memory Data Bus Parity JRST_B : JTAG Reset
HTCS1_B, HTCS0_B : HTT Memory Chip Select
HTWE_B : HTT Memory Write Enable (6) Other
HTOE_B : HTT Memory Output Enable SWCLK : System Clock
CBA17 - CBA0 : Cell Buffer Memory Address RESET_B : Hardware Reset
CBD87 - CBD0 : Cell Buffer Memory Data Bus IC : Internal Connected
CBCS1_B, CBCS0_B: Cell Buffer Memory Chip Select CG : Connect Ground
CBWE_B : Cell Buffer Memory Write Enable PU : Pull-up
CBOE_B : Cell Buffer Memory Output Enable
* = 0 to 3