Nuvoton NuMicro NUC442 Series Product manual

NuMicro

NUC442/NUC472 Series Technical Reference Manual
May 23, 2014 Page 1of 1386 Rev.1.05
NUMICRO™ NUC442/NUC472 SERIES TECHNICAL REFERENCE MANUAL
ARM Cortex®-M4
32-bit Microcontroller
NuMicro™ NUC442/NUC472 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com

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NUC442/NUC472 Series Technical Reference Manual
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NUMICRO™ NUC442/NUC472 SERIES TECHNICAL REFERENCE MANUAL
TABLE OF CONTENTS
1GENERAL DESCRIPTION............................................................ 19
NuMicroNUC442/NUC472 General Description .....................................191.1
2FEATURES .............................................................................. 20
NuMicroNUC442 Features – Connectivity Series ...................................202.1
NuMicroNUC472 Features - Advanced Series.......................................282.2
3ABBREVIATIONS....................................................................... 36
4PARTS INFORMATION LIST AND PIN CONFIGURATION..................... 38
Selection Guide ..............................................................................384.1
4.1.1 NuMicroNUC442 Connectivity Series Selection Guide....................................38
4.1.2 NuMicroNUC472 Advanced Series Selection Guide.......................................38
Pin Configuration.............................................................................414.2
4.2.1 NuMicroNUC442 Pin Diagrams ...............................................................41
4.2.2 NuMicroNUC472 Pin Diagrams ...............................................................45
Pin Description ...............................................................................494.3
4.3.1 NuMicroNUC442 Package LQFP 64-pin Description ......................................49
4.3.2 NuMicroNUC442 Package LQFP 100-pin Description.....................................61
4.3.3 NuMicroNUC442 Package LQFP 128-pin Description.....................................81
4.3.4 NuMicroNUC442 Package LQFP 144-pin Description...................................105
4.3.5 NuMicroNUC472 Package LQFP 100-pin Description...................................131
4.3.6 NuMicroNUC472 Package LQFP 128-pin Description...................................152
4.3.7 NuMicroNUC472 Package LQFP 144-pin Description...................................177
4.3.8 NuMicroNUC472 Package LQFP 176-pin Description...................................204
4.3.9 Summary GPIO Multi-function Pin Description ..............................................234
4.3.10 Summary Function Pin Description .........................................................240
5BLOCK DIAGRAM.....................................................................264
NuMicroNUC442 Series Block Diagram ............................................2645.1
NuMicroNUC472 Series Block Diagram ............................................2655.2
6FUNCTIONAL DESCRIPTION.......................................................266
ARM®Cortex®-M4 Core...................................................................2666.1
System Manager...........................................................................2696.2
6.2.1 Overview ...........................................................................................269
6.2.2 System Reset......................................................................................269

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6.2.3 System Power Distribution ......................................................................270
6.2.4 System Memory Map.............................................................................271
6.2.5 System Control Registers .......................................................................274
6.2.6 System Timer (SysTick) .........................................................................322
6.2.7 Nested Vectored Interrupt Controller (NVIC).................................................326
6.2.8 System Control Register Map and Description ..............................................345
Clock Controller ............................................................................3546.3
6.3.1 Overview ...........................................................................................354
6.3.2 System Clock and SysTick Clock ..............................................................358
6.3.3 Clock Monitor......................................................................................358
6.3.4 Peripherals Clock .................................................................................360
6.3.5 Power-down Mode Clock........................................................................360
6.3.6 Frequency Divider Output .......................................................................360
6.3.7 Register Map ......................................................................................362
6.3.8 Register Description..............................................................................363
Analog Comparator Controller (ACMP) ................................................3946.4
6.4.1 Overview ...........................................................................................394
6.4.2 Features............................................................................................394
6.4.3 Block Diagram.....................................................................................395
6.4.4 Functional Description ...........................................................................396
6.4.5 Comparator Reference Voltage (CRV)........................................................397
6.4.6 Register Map ......................................................................................398
6.4.7 Register Description..............................................................................399
Analog-to-Digital Converter (ADC)......................................................4066.5
6.5.1 Overview ...........................................................................................406
6.5.2 Features............................................................................................406
6.5.3 Block Diagram.....................................................................................407
6.5.4 Functional Description ...........................................................................407
6.5.5 Register Map ......................................................................................414
6.5.6 Register Description..............................................................................415
12-bit Analog-to-Digital Converter (Enhanced ADC).................................4266.6
6.6.1 Overview ...........................................................................................426
6.6.2 Features............................................................................................426
6.6.3 Block Diagram.....................................................................................428
6.6.4 Operation Procedure.............................................................................429

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6.6.5 Register Map ......................................................................................441
6.6.6 Register Description..............................................................................444
Controller Area Network (CAN)..........................................................4756.7
6.7.1 Overview ...........................................................................................475
6.7.2 Features............................................................................................475
6.7.3 Block Diagram.....................................................................................476
6.7.4 Functional Description ...........................................................................477
6.7.5 Test Mode..........................................................................................478
6.7.6 CAN Communications ...........................................................................480
6.7.7 Register Description..............................................................................499
6.7.8 Register Map ......................................................................................499
6.7.9 CAN Interface Reset State ......................................................................500
CRC Controller.............................................................................5386.8
6.8.1 Overview ...........................................................................................538
6.8.2 Features............................................................................................538
6.8.3 Block Diagram.....................................................................................539
6.8.4 Basic Configuration...............................................................................539
6.8.5 Functional Description ...........................................................................540
6.8.6 Register Map ......................................................................................540
6.8.7 Register Description..............................................................................541
Cryptographic Accelerator................................................................5466.9
6.9.1 Overview ...........................................................................................546
6.9.2 Features............................................................................................546
6.9.3 Block Diagram.....................................................................................547
6.9.4 Functional Description ...........................................................................548
6.9.5 Register Map ......................................................................................559
6.9.6 Register Description..............................................................................564
PDMA Controller (PDMA) ................................................................6096.10
6.10.1 Overview ........................................................................................609
6.10.2 Features .........................................................................................609
6.10.3 Block Diagram ..................................................................................609
6.10.4 Functional Description.........................................................................609
6.10.5 Register Map....................................................................................615
6.10.6 Register Description ...........................................................................620
External Bus Interface (EBI) .............................................................6576.11

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6.11.1 Overview ........................................................................................657
6.11.2 Features .........................................................................................657
6.11.3 Block Diagram ..................................................................................658
6.11.4 Functional Description.........................................................................658
6.11.5 Register Map....................................................................................666
6.11.6 Register Description ...........................................................................667
Ethernet MAC Controller (EMAC) (NUC472 Only) ...................................6806.12
6.12.1 Overview ........................................................................................680
6.12.2 Features .........................................................................................680
6.12.3 Block Diagram ..................................................................................681
6.12.4 Functional Description.........................................................................682
6.12.5 DMA Descriptors Data Structure ............................................................685
6.12.6 Register and Memory Map ...................................................................698
6.12.7 Register Description ...........................................................................701
Flash Memory Controller (FMC).........................................................7536.13
6.13.1 Overview ........................................................................................753
6.13.2 Features .........................................................................................753
6.13.3 Block Diagram ..................................................................................754
6.13.4 Flash Memory Organization..................................................................754
6.13.5 Boot Selection..................................................................................756
6.13.6 In Application Programming..................................................................757
6.13.7 Data Flash.......................................................................................758
6.13.8 User Configuration.............................................................................760
6.13.9 In System Program (ISP) .....................................................................765
6.13.10 ISP Procedure ...............................................................................765
6.13.11 Flash Control Register Map ...............................................................769
6.13.12 Flash Control Register Description.......................................................770
General Purpose I/O (GPIO).............................................................7896.14
6.14.1 Overview ........................................................................................789
6.14.2 Features .........................................................................................789
6.14.3 Functional Description.........................................................................790
6.14.4 Register Map....................................................................................792
6.14.5 Register Description ...........................................................................801
I2C Serial Interface Controller (Master/Slave).........................................8206.15

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6.15.1 Overview ........................................................................................821
6.15.2 Features .........................................................................................822
6.15.3 Functional Description.........................................................................823
6.15.4 Operation Modes...............................................................................825
6.15.5 Protocol Registers .............................................................................833
6.15.6 Register Map....................................................................................838
6.15.7 Register Description ...........................................................................839
I2S Controller (I2S) .........................................................................8496.16
6.16.1 Overview ........................................................................................849
6.16.2 Features .........................................................................................849
6.16.3 Block Diagram ..................................................................................850
6.16.4 Timing Diagram Description..................................................................851
6.16.5 Functional Description.........................................................................854
6.16.6 Register Map....................................................................................855
6.16.7 Register Description ...........................................................................856
Image Capture Interface (ICAP).........................................................8686.17
6.17.1 Overview ........................................................................................868
6.17.2 Block Diagram ..................................................................................868
6.17.3 Features .........................................................................................868
6.17.4 Functional Description.........................................................................869
6.17.5 Register Map....................................................................................872
6.17.6 Register Description ...........................................................................873
Enhanced Input Capture Timer..........................................................9036.18
6.18.1 Overview ........................................................................................903
6.18.2 Features .........................................................................................903
6.18.3 Input Capture Timer/Counter Architecture .................................................903
6.18.4 Input Noise Filter ...............................................................................904
6.18.5 Operation of Input Capture Timer/Counter.................................................904
6.18.6 Input Capture Timer/Counter Interrupt Architecture......................................907
6.18.7 Register Map....................................................................................908
6.18.8 Register Description ...........................................................................909
OP Amplifier ................................................................................9196.19
6.19.1 Overview ........................................................................................919
6.19.2 Features .........................................................................................919
6.19.3 Block Diagram ..................................................................................920

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6.19.4 Interrupt Sources...............................................................................920
6.19.5 Register Map....................................................................................921
6.19.6 Register Description ...........................................................................922
PS/2 Device Controller (PS2D)..........................................................9256.20
6.20.1 Overview ........................................................................................925
6.20.2 Features .........................................................................................925
6.20.3 Block Diagram ..................................................................................926
6.20.4 Functional Description.........................................................................927
6.20.5 Register Map....................................................................................931
6.20.6 Register Description ...........................................................................932
PWM Generator and Capture Timer (PWM) ..........................................9396.21
6.21.1 Overview ........................................................................................939
6.21.2 Features .........................................................................................939
6.21.3 Block Diagram ..................................................................................940
6.21.4 Functional Description.........................................................................945
6.21.5 Register Map....................................................................................958
6.21.6 Register Description ...........................................................................961
Enhanced PWM Generator (EPWM) ...................................................9986.22
6.22.1 Overview ........................................................................................998
6.22.2 Features .........................................................................................998
6.22.3 PWM Operation ................................................................................999
6.22.4 PWM Brake ................................................................................... 1006
6.22.5 PWM Port Output Driving Control ......................................................... 1009
6.22.6 PWM modes .................................................................................. 1009
6.22.7 Polarity Control............................................................................... 1011
6.22.8 PWM Mask Output Function ............................................................... 1012
6.22.9 Asymmetric PWM Output................................................................... 1014
6.22.10 Interrupt Architecture of Enhanced PWM ............................................. 1016
6.22.11 Register Map............................................................................... 1018
6.22.12 Register Description ...................................................................... 1019
Quadrature Encoder Interface (QEI)..................................................10396.23
6.23.1 Overview ...................................................................................... 1039
6.23.2 Features ....................................................................................... 1039
6.23.3 QEI Architecture.............................................................................. 1039
6.23.4 Input Noise Filter ............................................................................. 1040

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6.23.5 Operation of Quadrature Encoder Interface ............................................. 1041
6.23.6 Compare Function ........................................................................... 1045
6.23.7 Reload Counter by Pin IDX................................................................. 1045
6.23.8 Capture QEI Counter........................................................................ 1046
6.23.9 QEI Interrupt Architecture................................................................... 1047
6.23.10 Register Map............................................................................... 1049
6.23.11 Register Description ...................................................................... 1050
Real Time Clock (RTC) .................................................................10606.24
6.24.1 Overview ...................................................................................... 1060
6.24.2 Features ....................................................................................... 1060
6.24.3 Block Diagram ................................................................................ 1061
6.24.4 Functional Description....................................................................... 1062
6.24.5 Register Map.................................................................................. 1065
6.24.6 Register Description ......................................................................... 1067
Smart Card Host Interface (SC).......................................................10906.25
6.25.1 Overview ...................................................................................... 1090
6.25.2 Features ....................................................................................... 1090
6.25.3 Block Diagram ................................................................................ 1090
6.25.4 Functional description....................................................................... 1091
6.25.5 Register Map.................................................................................. 1099
6.25.6 Register Description ......................................................................... 1100
Secure Digital Host Controller .........................................................11266.26
6.26.1 Overview ...................................................................................... 1126
6.26.2 Features ....................................................................................... 1126
6.26.3 Block Diagram and Card Pad Assignment............................................... 1127
6.26.4 SD Host DMA Controller.................................................................... 1127
6.26.5 SD Host Functional Description ........................................................... 1128
6.26.6 Register Map.................................................................................. 1130
6.26.7 Register Description ......................................................................... 1131
Serial Peripheral Interface (SPI).......................................................11516.27
6.27.1 Overview ...................................................................................... 1151
6.27.2 Features ....................................................................................... 1151
6.27.3 Block Diagram ................................................................................ 1152
6.27.4 Functional Description....................................................................... 1153
6.27.5 Timing Diagram .............................................................................. 1164

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6.27.6 Programming Flows ......................................................................... 1166
6.27.7 Register Map.................................................................................. 1169
6.27.8 Register Description ......................................................................... 1170
Timer Controller (TIMER)...............................................................11846.28
6.28.1 Overview ...................................................................................... 1184
6.28.2 Features ....................................................................................... 1184
6.28.3 Block Diagram ................................................................................ 1185
6.28.4 Basic Configuration.......................................................................... 1186
6.28.5 Functional Description....................................................................... 1186
6.28.6 Register Map.................................................................................. 1189
6.28.7 Register Description ......................................................................... 1191
Watchdog Timer (WDT).................................................................12016.29
6.29.1 Overview ...................................................................................... 1201
6.29.2 Features ....................................................................................... 1201
6.29.3 Block Diagram ................................................................................ 1201
6.29.4 Basic Configuration.......................................................................... 1202
6.29.5 Functional Description....................................................................... 1202
6.29.6 Register Map.................................................................................. 1205
6.29.7 Register Description ......................................................................... 1206
Window Watchdog Timer (WWDT) ...................................................12096.30
6.30.1 Overview ...................................................................................... 1209
6.30.2 Features ....................................................................................... 1209
6.30.3 Block Diagram ................................................................................ 1209
6.30.4 Basic Configuration.......................................................................... 1210
6.30.5 Functional Description....................................................................... 1210
6.30.6 Register Map.................................................................................. 1212
6.30.7 Register Description ......................................................................... 1213
UART Interface Controller (UART)....................................................12186.31
6.31.1 Overview ...................................................................................... 1218
6.31.2 Features ....................................................................................... 1218
6.31.3 Block Diagram ................................................................................ 1220
6.31.4 IrDA Mode..................................................................................... 1222
6.31.5 LIN (Local Interconnection Network) Mode.............................................. 1224
6.31.6 RS-485 Function Mode ..................................................................... 1233
6.31.7 Register Map.................................................................................. 1236

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6.31.8 Register Description ......................................................................... 1237
USB 2.0 Device Controller .............................................................12666.32
6.32.1 Overview ...................................................................................... 1266
6.32.2 Features ....................................................................................... 1266
6.32.3 Block Diagram ................................................................................ 1267
6.32.4 Functional Description....................................................................... 1267
6.32.5 Registers Map ................................................................................ 1270
6.32.6 Register Description ......................................................................... 1275
USB 1.1 Host Controller (USBH)......................................................13276.33
6.33.1 Overview ...................................................................................... 1327
6.33.2 Features ....................................................................................... 1327
6.33.3 Block Diagram ................................................................................ 1328
6.33.4 Basic Configuration.......................................................................... 1328
6.33.5 Functional Description....................................................................... 1329
6.33.6 Register Map.................................................................................. 1331
6.33.7 Register Description ......................................................................... 1333
USB OTG Controller.....................................................................13656.34
6.34.1 Overview ...................................................................................... 1365
6.34.2 Features ....................................................................................... 1365
6.34.3Block Diagram ................................................................................ 1366
6.34.4 Functional Description....................................................................... 1366
6.34.5 Register and Memory Map ................................................................. 1370
6.34.6 Register Description ......................................................................... 1371
7PACKAGE DIMENSIONS ..........................................................1380
LQFP 64L (10x10x1.4 mm footprint 2.0 mm) .......................................13807.1
LQFP 100L (14x14x1.4 mm footprint 2.0 mm)......................................13817.2
LQFP 128L (14x14x1.4 mm footprint 2.0 mm)......................................13827.3
LQFP 144L (20x20x1.4 mm footprint 2.0 mm)......................................13837.4
LQFP 176L (24x24x1.4 mm footprint 2.0 mm)......................................13847.5
8REVISION HISTORY................................................................1385