Nuvoton NuMicro NUC442 Series Product manual

NuMicro

NUC442/NUC472 Series Technical Reference Manual
May 23, 2014 Page 1of 1386 Rev.1.05
NUMICRO™ NUC442/NUC472 SERIES TECHNICAL REFERENCE MANUAL
ARM Cortex®-M4
32-bit Microcontroller
NuMicro™ NUC442/NUC472 Series
Technical Reference Manual
The information described in this document is the exclusive intellectual property of
Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.
Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based
system design. Nuvoton assumes no responsibility for errors or omissions.
All data and specifications are subject to change without notice.
For additional information or questions, please contact: Nuvoton Technology Corporation.
www.nuvoton.com

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NUMICRO™ NUC442/NUC472 SERIES TECHNICAL REFERENCE MANUAL
TABLE OF CONTENTS
1GENERAL DESCRIPTION............................................................ 19
NuMicroNUC442/NUC472 General Description .....................................191.1
2FEATURES .............................................................................. 20
NuMicroNUC442 Features – Connectivity Series ...................................202.1
NuMicroNUC472 Features - Advanced Series.......................................282.2
3ABBREVIATIONS....................................................................... 36
4PARTS INFORMATION LIST AND PIN CONFIGURATION..................... 38
Selection Guide ..............................................................................384.1
4.1.1 NuMicroNUC442 Connectivity Series Selection Guide....................................38
4.1.2 NuMicroNUC472 Advanced Series Selection Guide.......................................38
Pin Configuration.............................................................................414.2
4.2.1 NuMicroNUC442 Pin Diagrams ...............................................................41
4.2.2 NuMicroNUC472 Pin Diagrams ...............................................................45
Pin Description ...............................................................................494.3
4.3.1 NuMicroNUC442 Package LQFP 64-pin Description ......................................49
4.3.2 NuMicroNUC442 Package LQFP 100-pin Description.....................................61
4.3.3 NuMicroNUC442 Package LQFP 128-pin Description.....................................81
4.3.4 NuMicroNUC442 Package LQFP 144-pin Description...................................105
4.3.5 NuMicroNUC472 Package LQFP 100-pin Description...................................131
4.3.6 NuMicroNUC472 Package LQFP 128-pin Description...................................152
4.3.7 NuMicroNUC472 Package LQFP 144-pin Description...................................177
4.3.8 NuMicroNUC472 Package LQFP 176-pin Description...................................204
4.3.9 Summary GPIO Multi-function Pin Description ..............................................234
4.3.10 Summary Function Pin Description .........................................................240
5BLOCK DIAGRAM.....................................................................264
NuMicroNUC442 Series Block Diagram ............................................2645.1
NuMicroNUC472 Series Block Diagram ............................................2655.2
6FUNCTIONAL DESCRIPTION.......................................................266
ARM®Cortex®-M4 Core...................................................................2666.1
System Manager...........................................................................2696.2
6.2.1 Overview ...........................................................................................269
6.2.2 System Reset......................................................................................269

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6.2.3 System Power Distribution ......................................................................270
6.2.4 System Memory Map.............................................................................271
6.2.5 System Control Registers .......................................................................274
6.2.6 System Timer (SysTick) .........................................................................322
6.2.7 Nested Vectored Interrupt Controller (NVIC).................................................326
6.2.8 System Control Register Map and Description ..............................................345
Clock Controller ............................................................................3546.3
6.3.1 Overview ...........................................................................................354
6.3.2 System Clock and SysTick Clock ..............................................................358
6.3.3 Clock Monitor......................................................................................358
6.3.4 Peripherals Clock .................................................................................360
6.3.5 Power-down Mode Clock........................................................................360
6.3.6 Frequency Divider Output .......................................................................360
6.3.7 Register Map ......................................................................................362
6.3.8 Register Description..............................................................................363
Analog Comparator Controller (ACMP) ................................................3946.4
6.4.1 Overview ...........................................................................................394
6.4.2 Features............................................................................................394
6.4.3 Block Diagram.....................................................................................395
6.4.4 Functional Description ...........................................................................396
6.4.5 Comparator Reference Voltage (CRV)........................................................397
6.4.6 Register Map ......................................................................................398
6.4.7 Register Description..............................................................................399
Analog-to-Digital Converter (ADC)......................................................4066.5
6.5.1 Overview ...........................................................................................406
6.5.2 Features............................................................................................406
6.5.3 Block Diagram.....................................................................................407
6.5.4 Functional Description ...........................................................................407
6.5.5 Register Map ......................................................................................414
6.5.6 Register Description..............................................................................415
12-bit Analog-to-Digital Converter (Enhanced ADC).................................4266.6
6.6.1 Overview ...........................................................................................426
6.6.2 Features............................................................................................426
6.6.3 Block Diagram.....................................................................................428
6.6.4 Operation Procedure.............................................................................429

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6.6.5 Register Map ......................................................................................441
6.6.6 Register Description..............................................................................444
Controller Area Network (CAN)..........................................................4756.7
6.7.1 Overview ...........................................................................................475
6.7.2 Features............................................................................................475
6.7.3 Block Diagram.....................................................................................476
6.7.4 Functional Description ...........................................................................477
6.7.5 Test Mode..........................................................................................478
6.7.6 CAN Communications ...........................................................................480
6.7.7 Register Description..............................................................................499
6.7.8 Register Map ......................................................................................499
6.7.9 CAN Interface Reset State ......................................................................500
CRC Controller.............................................................................5386.8
6.8.1 Overview ...........................................................................................538
6.8.2 Features............................................................................................538
6.8.3 Block Diagram.....................................................................................539
6.8.4 Basic Configuration...............................................................................539
6.8.5 Functional Description ...........................................................................540
6.8.6 Register Map ......................................................................................540
6.8.7 Register Description..............................................................................541
Cryptographic Accelerator................................................................5466.9
6.9.1 Overview ...........................................................................................546
6.9.2 Features............................................................................................546
6.9.3 Block Diagram.....................................................................................547
6.9.4 Functional Description ...........................................................................548
6.9.5 Register Map ......................................................................................559
6.9.6 Register Description..............................................................................564
PDMA Controller (PDMA) ................................................................6096.10
6.10.1 Overview ........................................................................................609
6.10.2 Features .........................................................................................609
6.10.3 Block Diagram ..................................................................................609
6.10.4 Functional Description.........................................................................609
6.10.5 Register Map....................................................................................615
6.10.6 Register Description ...........................................................................620
External Bus Interface (EBI) .............................................................6576.11

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6.11.1 Overview ........................................................................................657
6.11.2 Features .........................................................................................657
6.11.3 Block Diagram ..................................................................................658
6.11.4 Functional Description.........................................................................658
6.11.5 Register Map....................................................................................666
6.11.6 Register Description ...........................................................................667
Ethernet MAC Controller (EMAC) (NUC472 Only) ...................................6806.12
6.12.1 Overview ........................................................................................680
6.12.2 Features .........................................................................................680
6.12.3 Block Diagram ..................................................................................681
6.12.4 Functional Description.........................................................................682
6.12.5 DMA Descriptors Data Structure ............................................................685
6.12.6 Register and Memory Map ...................................................................698
6.12.7 Register Description ...........................................................................701
Flash Memory Controller (FMC).........................................................7536.13
6.13.1 Overview ........................................................................................753
6.13.2 Features .........................................................................................753
6.13.3 Block Diagram ..................................................................................754
6.13.4 Flash Memory Organization..................................................................754
6.13.5 Boot Selection..................................................................................756
6.13.6 In Application Programming..................................................................757
6.13.7 Data Flash.......................................................................................758
6.13.8 User Configuration.............................................................................760
6.13.9 In System Program (ISP) .....................................................................765
6.13.10 ISP Procedure ...............................................................................765
6.13.11 Flash Control Register Map ...............................................................769
6.13.12 Flash Control Register Description.......................................................770
General Purpose I/O (GPIO).............................................................7896.14
6.14.1 Overview ........................................................................................789
6.14.2 Features .........................................................................................789
6.14.3 Functional Description.........................................................................790
6.14.4 Register Map....................................................................................792
6.14.5 Register Description ...........................................................................801
I2C Serial Interface Controller (Master/Slave).........................................8206.15

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6.15.1 Overview ........................................................................................821
6.15.2 Features .........................................................................................822
6.15.3 Functional Description.........................................................................823
6.15.4 Operation Modes...............................................................................825
6.15.5 Protocol Registers .............................................................................833
6.15.6 Register Map....................................................................................838
6.15.7 Register Description ...........................................................................839
I2S Controller (I2S) .........................................................................8496.16
6.16.1 Overview ........................................................................................849
6.16.2 Features .........................................................................................849
6.16.3 Block Diagram ..................................................................................850
6.16.4 Timing Diagram Description..................................................................851
6.16.5 Functional Description.........................................................................854
6.16.6 Register Map....................................................................................855
6.16.7 Register Description ...........................................................................856
Image Capture Interface (ICAP).........................................................8686.17
6.17.1 Overview ........................................................................................868
6.17.2 Block Diagram ..................................................................................868
6.17.3 Features .........................................................................................868
6.17.4 Functional Description.........................................................................869
6.17.5 Register Map....................................................................................872
6.17.6 Register Description ...........................................................................873
Enhanced Input Capture Timer..........................................................9036.18
6.18.1 Overview ........................................................................................903
6.18.2 Features .........................................................................................903
6.18.3 Input Capture Timer/Counter Architecture .................................................903
6.18.4 Input Noise Filter ...............................................................................904
6.18.5 Operation of Input Capture Timer/Counter.................................................904
6.18.6 Input Capture Timer/Counter Interrupt Architecture......................................907
6.18.7 Register Map....................................................................................908
6.18.8 Register Description ...........................................................................909
OP Amplifier ................................................................................9196.19
6.19.1 Overview ........................................................................................919
6.19.2 Features .........................................................................................919
6.19.3 Block Diagram ..................................................................................920

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6.19.4 Interrupt Sources...............................................................................920
6.19.5 Register Map....................................................................................921
6.19.6 Register Description ...........................................................................922
PS/2 Device Controller (PS2D)..........................................................9256.20
6.20.1 Overview ........................................................................................925
6.20.2 Features .........................................................................................925
6.20.3 Block Diagram ..................................................................................926
6.20.4 Functional Description.........................................................................927
6.20.5 Register Map....................................................................................931
6.20.6 Register Description ...........................................................................932
PWM Generator and Capture Timer (PWM) ..........................................9396.21
6.21.1 Overview ........................................................................................939
6.21.2 Features .........................................................................................939
6.21.3 Block Diagram ..................................................................................940
6.21.4 Functional Description.........................................................................945
6.21.5 Register Map....................................................................................958
6.21.6 Register Description ...........................................................................961
Enhanced PWM Generator (EPWM) ...................................................9986.22
6.22.1 Overview ........................................................................................998
6.22.2 Features .........................................................................................998
6.22.3 PWM Operation ................................................................................999
6.22.4 PWM Brake ................................................................................... 1006
6.22.5 PWM Port Output Driving Control ......................................................... 1009
6.22.6 PWM modes .................................................................................. 1009
6.22.7 Polarity Control............................................................................... 1011
6.22.8 PWM Mask Output Function ............................................................... 1012
6.22.9 Asymmetric PWM Output................................................................... 1014
6.22.10 Interrupt Architecture of Enhanced PWM ............................................. 1016
6.22.11 Register Map............................................................................... 1018
6.22.12 Register Description ...................................................................... 1019
Quadrature Encoder Interface (QEI)..................................................10396.23
6.23.1 Overview ...................................................................................... 1039
6.23.2 Features ....................................................................................... 1039
6.23.3 QEI Architecture.............................................................................. 1039
6.23.4 Input Noise Filter ............................................................................. 1040

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6.23.5 Operation of Quadrature Encoder Interface ............................................. 1041
6.23.6 Compare Function ........................................................................... 1045
6.23.7 Reload Counter by Pin IDX................................................................. 1045
6.23.8 Capture QEI Counter........................................................................ 1046
6.23.9 QEI Interrupt Architecture................................................................... 1047
6.23.10 Register Map............................................................................... 1049
6.23.11 Register Description ...................................................................... 1050
Real Time Clock (RTC) .................................................................10606.24
6.24.1 Overview ...................................................................................... 1060
6.24.2 Features ....................................................................................... 1060
6.24.3 Block Diagram ................................................................................ 1061
6.24.4 Functional Description....................................................................... 1062
6.24.5 Register Map.................................................................................. 1065
6.24.6 Register Description ......................................................................... 1067
Smart Card Host Interface (SC).......................................................10906.25
6.25.1 Overview ...................................................................................... 1090
6.25.2 Features ....................................................................................... 1090
6.25.3 Block Diagram ................................................................................ 1090
6.25.4 Functional description....................................................................... 1091
6.25.5 Register Map.................................................................................. 1099
6.25.6 Register Description ......................................................................... 1100
Secure Digital Host Controller .........................................................11266.26
6.26.1 Overview ...................................................................................... 1126
6.26.2 Features ....................................................................................... 1126
6.26.3 Block Diagram and Card Pad Assignment............................................... 1127
6.26.4 SD Host DMA Controller.................................................................... 1127
6.26.5 SD Host Functional Description ........................................................... 1128
6.26.6 Register Map.................................................................................. 1130
6.26.7 Register Description ......................................................................... 1131
Serial Peripheral Interface (SPI).......................................................11516.27
6.27.1 Overview ...................................................................................... 1151
6.27.2 Features ....................................................................................... 1151
6.27.3 Block Diagram ................................................................................ 1152
6.27.4 Functional Description....................................................................... 1153
6.27.5 Timing Diagram .............................................................................. 1164

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6.27.6 Programming Flows ......................................................................... 1166
6.27.7 Register Map.................................................................................. 1169
6.27.8 Register Description ......................................................................... 1170
Timer Controller (TIMER)...............................................................11846.28
6.28.1 Overview ...................................................................................... 1184
6.28.2 Features ....................................................................................... 1184
6.28.3 Block Diagram ................................................................................ 1185
6.28.4 Basic Configuration.......................................................................... 1186
6.28.5 Functional Description....................................................................... 1186
6.28.6 Register Map.................................................................................. 1189
6.28.7 Register Description ......................................................................... 1191
Watchdog Timer (WDT).................................................................12016.29
6.29.1 Overview ...................................................................................... 1201
6.29.2 Features ....................................................................................... 1201
6.29.3 Block Diagram ................................................................................ 1201
6.29.4 Basic Configuration.......................................................................... 1202
6.29.5 Functional Description....................................................................... 1202
6.29.6 Register Map.................................................................................. 1205
6.29.7 Register Description ......................................................................... 1206
Window Watchdog Timer (WWDT) ...................................................12096.30
6.30.1 Overview ...................................................................................... 1209
6.30.2 Features ....................................................................................... 1209
6.30.3 Block Diagram ................................................................................ 1209
6.30.4 Basic Configuration.......................................................................... 1210
6.30.5 Functional Description....................................................................... 1210
6.30.6 Register Map.................................................................................. 1212
6.30.7 Register Description ......................................................................... 1213
UART Interface Controller (UART)....................................................12186.31
6.31.1 Overview ...................................................................................... 1218
6.31.2 Features ....................................................................................... 1218
6.31.3 Block Diagram ................................................................................ 1220
6.31.4 IrDA Mode..................................................................................... 1222
6.31.5 LIN (Local Interconnection Network) Mode.............................................. 1224
6.31.6 RS-485 Function Mode ..................................................................... 1233
6.31.7 Register Map.................................................................................. 1236

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6.31.8 Register Description ......................................................................... 1237
USB 2.0 Device Controller .............................................................12666.32
6.32.1 Overview ...................................................................................... 1266
6.32.2 Features ....................................................................................... 1266
6.32.3 Block Diagram ................................................................................ 1267
6.32.4 Functional Description....................................................................... 1267
6.32.5 Registers Map ................................................................................ 1270
6.32.6 Register Description ......................................................................... 1275
USB 1.1 Host Controller (USBH)......................................................13276.33
6.33.1 Overview ...................................................................................... 1327
6.33.2 Features ....................................................................................... 1327
6.33.3 Block Diagram ................................................................................ 1328
6.33.4 Basic Configuration.......................................................................... 1328
6.33.5 Functional Description....................................................................... 1329
6.33.6 Register Map.................................................................................. 1331
6.33.7 Register Description ......................................................................... 1333
USB OTG Controller.....................................................................13656.34
6.34.1 Overview ...................................................................................... 1365
6.34.2 Features ....................................................................................... 1365
6.34.3Block Diagram ................................................................................ 1366
6.34.4 Functional Description....................................................................... 1366
6.34.5 Register and Memory Map ................................................................. 1370
6.34.6 Register Description ......................................................................... 1371
7PACKAGE DIMENSIONS ..........................................................1380
LQFP 64L (10x10x1.4 mm footprint 2.0 mm) .......................................13807.1
LQFP 100L (14x14x1.4 mm footprint 2.0 mm)......................................13817.2
LQFP 128L (14x14x1.4 mm footprint 2.0 mm)......................................13827.3
LQFP 144L (20x20x1.4 mm footprint 2.0 mm)......................................13837.4
LQFP 176L (24x24x1.4 mm footprint 2.0 mm)......................................13847.5
8REVISION HISTORY................................................................1385

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List of Figure
Figure 4.1-1 NuMicroNUC442/NUC472 Series Selection Code................................................ 40
Figure 4.2-1 NuMicroNUC442Rxxxx LQFP 64-pin Diagram...................................................... 41
Figure 4.2-2 NuMicroNUC442Vxxxx LQFP 100-pin Diagram.................................................... 42
Figure 4.2-3 NuMicroNUC442Kxxxx LQFP 128-pin Diagram.................................................... 43
Figure 4.2-4 NuMicroNUC442Jxxxx LQFP 144-pin Diagram .................................................... 44
Figure 4.2-5 NuMicroNUC472Vxxxx LQFP 100-pin Diagram.................................................... 45
Figure 4.2-6 NuMicroNUC472Kxxxx LQFP 128-pin Diagram.................................................... 46
Figure 4.2-7 NuMicroNUC472Jxxxx LQFP 144-pin Diagram .................................................... 47
Figure 4.2-8 NuMicroNUC472Hxxxx LQFP 176-pin Diagram.................................................... 48
Figure 5.1-1 NuMicroNUC442 Series Block Diagram.............................................................. 264
Figure 5.2-1 NuMicroNUC472 Series Block Diagram.............................................................. 265
Figure 6.1-1 Cortex®-M4 Block Diagram...................................................................................... 266
Figure 6.2-1 NuMicroNUC442/NUC472 Power Distribution Diagram...................................... 270
Figure 6.3-1 Clock Generator Block Diagram.............................................................................. 355
Figure 6.3-2 System Clock Block Diagram .................................................................................. 358
Figure 6.3-3 System Clock Switch Procedure ............................................................................. 359
Figure 6.3-4 SysTick Clock Control Block Diagram..................................................................... 359
Figure 6.3-5 Clock Source of Frequency Divider......................................................................... 360
Figure 6.3-6 Block Diagram of Frequency Divider....................................................................... 361
Figure 6.4-1 Analog Comparator Block Diagram......................................................................... 395
Figure 6.4-2 Comparator Controller Interrupt Sources ................................................................ 396
Figure 6.4-3 Comparator Hysteresis Function............................................................................. 396
Figure 6.4-4 Comparator Reference Voltage Block Diagram ...................................................... 397
Figure 6.5-1 ADC Controller Block Diagram................................................................................ 407
Figure 6.5-2 ADC Clock Control................................................................................................... 408
Figure 6.5-3 Single Mode Conversion Timing Diagram............................................................... 409
Figure 6.5-4 Single-Cycle Scan on Enabled Channels Timing Diagram..................................... 410
Figure 6.5-5 Continuous Scan on Enabled Channels Timing Diagram ....................................... 411
Figure 6.5-6 A/D Conversion Result Monitor Block Diagram....................................................... 412
Figure 6.5-7 A/D Controller Interrupt............................................................................................ 412
Figure 6.5-8 Conversion Result Mapping Diagram of Single-end Input ...................................... 416
Figure 6.5-9 Conversion Result Mapping Diagram of Differential Input ...................................... 417
Figure 6.6-1 ADC0 Converter Block Diagram.............................................................................. 428
Figure 6.6-2 ADC1 Converter Block Diagram.............................................................................. 429

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Figure 6.6-3 ADC Clock Control................................................................................................... 429
Figure 6.6-4 Single Sampling Mode Conversion Timing Diagram............................................... 431
Figure 6.6-5 SAMPLE00~SAMPLE03 and SAMPLE10~SAMPLE13 Control Block Diagram..... 431
Figure 6.6-6 SAMPLE04~SAMPLE07 and SAMPLE14~SAMPLE17 Control Block Diagram..... 432
Figure 6.6-7 SAMPLE Module Conversion Priority Arbitrator Diagram....................................... 433
Figure 6.6-8 PWM-triggered ADC Start Conversion.................................................................... 434
Figure 6.6-9 SAMPLE module A/D EOC Signal for ADINT0 Interrupt......................................... 435
Figure 6.6-10 SAMPLE module A/D EOC Signal for ADINT1 Interrupt....................................... 436
Figure 6.6-11 SAMPLE module A/D EOC Signal for ADINT2 Interrupt....................................... 436
Figure 6.6-12 SAMPLE module A/D EOC Signal for ADINT3 Interrupt....................................... 437
Figure 6.6-13 Conversion Start Delay Timing Diagram............................................................... 438
Figure 6.6-14 A/D Extend Sampling Timing Diagram.................................................................. 439
Figure 6.6-15 A/D Conversion Result Monitor Logics Diagram................................................... 439
Figure 6.6-16 A/D Controller Interrupts........................................................................................ 440
Figure 6.7-1 CAN Peripheral Block Diagram ............................................................................... 476
Figure 6.7-2 CAN Core in Silent Mode ........................................................................................ 478
Figure 6.7-3 CAN Core in Loop Back Mode ................................................................................ 479
Figure 6.7-4 CAN Core in Loop Back Mode Combined with Silent Mode ................................... 479
Figure 6.7-5 Data transfer between IFn Registers and Message................................................ 482
Figure 6.7-6 Application Software Handling of a FIFO Buffer................................................. 487
Figure 6.7-7 Bit Timing ................................................................................................................ 489
Figure 6.7-8 Propagation Time Segment.................................................................................... 490
Figure 6.7-9 Synchronization on “late” and “early” Edges.......................................................... 492
Figure 6.7-10 Filtering of Short Dominant Spikes........................................................................ 493
Figure 6.7-11 Structure of the CAN Core’s CAN Protocol Controller........................................ 495
Figure 6.8-1 CRC Generator Block Diagram .............................................................................. 539
Figure 6.9-1 Cryptographic Accelerator Block Diagram............................................................... 547
Figure 6.9-2 PRNG Function Diagram......................................................................................... 549
Figure 6.9-3 Electronic Codebook Mode ..................................................................................... 550
Figure 6.9-4 Cipher Block Chaining Mode................................................................................... 551
Figure 6.9-5 Cipher Feedback Mode ........................................................................................... 552
Figure 6.9-6 Output Feedback Mode........................................................................................... 553
Figure 6.9-7 Counter Mode.......................................................................................................... 554
Figure 6.9-8 CBC-CS1 Encryption............................................................................................... 555
Figure 6.9-9 CBC-CS1 Decryption............................................................................................... 555
Figure 6.10-1 PDMA Controller Block Diagram ........................................................................... 609

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Figure 6.10-2 Embedded Description Table Data Structure........................................................ 611
Figure 6.10-3 Embedded Description Table Data Structure........................................................ 612
Figure 6.10-4 Embedded Description Table Data Structure........................................................ 613
Figure 6.11-1 EBI Block Diagram................................................................................................. 658
Figure 6.11-2 Connection of 16-bit EBI Data Width with 16-bit Device...................................... 659
Figure 6.11-3 Connection of 8-bit EBI Data Width with 8-bit Device........................................... 660
Figure 6.11-4 Connection of 16-bit EBI Data Width with 16-bit Device in Address/Data Separating
Mode ..................................................................................................................................... 660
Figure 6.11-5 Timing Control Waveform for 16-bit Data Width................................................... 662
Figure 6.11-6 Timing Control Waveform for 8-bit Data Width..................................................... 663
Figure 6.11-7 Timing Control Waveform for Insert Idle Cycle...................................................... 664
Figure 6.11-8 Timing Control Waveform for Address & Data Separate Mode (16-bit Data Width)
.............................................................................................................................................. 665
Figure 6.12-1 Ethernet MAC Controller Block Diagram............................................................... 681
Figure 6.12-2 Ethernet Frame Format ......................................................................................... 683
Figure 6.12-3 64-bit Reference Timing Counter .......................................................................... 684
Figure 6.12-4 RXDMA Descriptor Data Structure........................................................................ 685
Figure 6.12-5 TXDMA Descriptor Data Structure ........................................................................ 691
Figure 6.12-6 MII Management Frame Format............................................................................ 718
Figure 6.13-1 Flash Memory Organization .................................................................................. 755
Figure 6.13-2 NUC442/NUC472 Boot Selection.......................................................................... 757
Figure 6.13-3 Executable Range of Code with IAP Function Enabled........................................ 758
Figure 6.13-4 Flash Memory Structure ........................................................................................ 759
Figure 6.14-1 Push-Pull Output.................................................................................................... 790
Figure 6.14-2 Open-Drain Output ................................................................................................ 790
Figure 6.14-3 Quasi-bidirectional I/O Mode................................................................................. 791
Figure 6.15-1 I2C Bus Timing....................................................................................................... 821
Figure 6.15-2 I2C Protocol............................................................................................................ 823
Figure 6.15-3 Master Transmits Data to Slave............................................................................ 823
Figure 6.15-4 Master Reads Data from Slave ............................................................................. 824
Figure 6.15-5 START and STOP Condition................................................................................. 824
Figure 6.15-6 Bit Transfer on I2C Bus.......................................................................................... 825
Figure 6.15-7 Acknowledge on I2C Bus....................................................................................... 825
Figure 6.15-8 Control I2C Bus according to Current I2C Status................................................... 826
Figure 6.15-9 Master Transmitter Mode Control Flow................................................................. 827
Figure 6.15-10 Master Receiver Mode Control Flow ................................................................... 828
Figure 6.15-11 Slave Mode Control Flow .................................................................................... 829

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Figure 6.15-12 GC Mode ............................................................................................................. 831
Figure 6.15-13 EEPROM Random Read..................................................................................... 832
Figure 6.15-14 Protocol of EEPROM Random Read................................................................... 833
Figure 6.15-15 I2C Data Shifting Direction................................................................................... 834
Figure 6.15-16 I2C Time-out Count Block Diagram ..................................................................... 836
Figure 6.16-1 I2S Clock Control Diagram..................................................................................... 850
Figure 6.16-2 I2S Controller Block Diagram................................................................................. 850
Figure 6.16-3 I2S Bus Timing Diagram (PCM = 0, Format = 0)........................................ 851
Figure 6.16-4 MSB Justified Timing Diagram (PCM = 0, Format = 1)......................................... 851
Figure 6.16-5 PCM A Audio Timing Diagram (PCM = 1, Format = 0) ......................................... 851
Figure 6.16-6 PCM B Audio Timing Diagram (PCM = 1, Format = 1) ......................................... 852
Figure 6.16-7 FIFO Contents for Various I2S Modes................................................................... 853
Figure 6.16-8 Master mode Interface Block Diagram.................................................................. 854
Figure 6.16-9 Slave mode Interface Block Diagram.................................................................... 854
Figure 6.17-1 Image Capture Interface Block Diagram ............................................................... 868
Figure 6.17-2 Image Capture Flow Chart .................................................................................... 869
Figure 6.17-3 Image Start and Size of the Window after Cropping Block ................................... 870
Figure 6.17-4 MDSM is set to 0 and MDBS is set to 1 ................................................................ 870
Figure 6.17-5 MDSM is set to 1 and MDBS is set to 0 ................................................................ 871
Figure 6.18-1 Input Capture Timer/Counter Clock Source Control.............................................. 903
Figure 6.18-2 Input Capture Timer/Counter Architecture............................................................. 904
Figure 6.18-3 Noise Filter Sampling Clock Selection................................................................... 904
Figure 6.18-4 Input Capture Timer/Counter Functions Block ...................................................... 906
Figure 6.18-5 Input Capture Timer/Counter Interrupt Architecture Diagram ............................... 907
Figure 6.19-1 OP Amplifier Block Diagram.................................................................................. 920
Figure 6.20-1 PS/2 Device Block Diagram .................................................................................. 926
Figure 6.20-2 Data Format of Device-to-Host.............................................................................. 928
Figure 6.20-3 Data Format of Host-to-Device.............................................................................. 928
Figure 6.20-4 PS/2 Bit Data Format............................................................................................. 929
Figure 6.20-5 PS/2 Bus Timing.................................................................................................... 929
Figure 6.20-6 PS/2 Data Format.................................................................................................. 930
Figure 6.21-1 PWM Generator 0 Clock Source Control............................................................... 940
Figure 6.21-2 PWM Generator 0 Architecture Diagram............................................................... 941
Figure 6.21-3 PWM Generator 2 Clock Source Control............................................................... 942
Figure 6.21-4 PWM Generator 2 Architecture Diagram............................................................... 943
Figure 6.21-5 PWM Generator 4 Clock Source Control............................................................... 944

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Figure 6.21-6 PWM Generator 4 Architecture Diagram............................................................... 945
Figure 6.21-7 PWM waveform of Edge-aligned type................................................................... 946
Figure 6.21-8 Center-Aligned Mode Output Waveform ............................................................... 947
Figure 6.21-9 PWM Center Aligned Interrupt Generate Timing Waveform................................. 948
Figure 6.21-10 PWM Double Buffering Timing Waveform........................................................... 949
Figure 6.21-11 PWM Paired-output with Dead-zone Generation Operation ............................... 949
Figure 6.21-12 Illustration of Mask Control Waveform................................................................. 951
Figure 6.21-13 PWM Brake Function........................................................................................... 952
Figure 6.21-14 PWM Output Multiplex for Group Mode and Synchronous Mode ....................... 953
Figure 6.21-15 PWM Multiplex for Mask Control, Brake Control and Polarity Control ................ 954
Figure 6.21-16 Capture Operation Timing................................................................................... 955
Figure 6.21-17 PWM Interrupt Architecture Diagram................................................................... 956
Figure 6.22-1 PWM Block Diagram.............................................................................................. 999
Figure 6.22-2 PWM Clock Source Control................................................................................... 999
Figure 6.22-3 PWM Time-base Generator................................................................................. 1000
Figure 6.22-4 Edge-Aligned PWM ............................................................................................. 1002
Figure 6.22-5 PWM0 Edge Aligned Waveform Output.............................................................. 1002
Figure 6.22-6 Edge-Aligned Flow Diagram................................................................................ 1003
Figure 6.22-7 Center-Aligned Mode........................................................................................... 1004
Figure 6.22-8 Example PWM0 Center-Aligned Waveform Output ............................................ 1005
Figure 6.22-9 Center-aligned Flow Diagram (INTTYPE (EPWM_CTL[8]) = 0) ......................... 1006
Figure 6.22-10 PWM Brake Function......................................................................................... 1007
Figure 6.22-11 PWM Brake Condition (Edge-aligned Mode) .................................................... 1008
Figure 6.22-12 PWM Brake Condition (Centre-aligned Mode).................................................. 1008
Figure 6.22-13 PWM Output Driving Control ............................................................................. 1009
Figure 6.22-14 Dead-Time Insertion.......................................................................................... 1010
Figure 6.22-15 Initial State and Polarity Control with Rising Edge Dead Time Insertion........... 1011
Figure 6.22-16 Illustration of Mask Control................................................................................ 1013
Figure 6.22-17 Asymmetric PWM Architecture.......................................................................... 1015
Figure 6.22-18 Symmetric PWM Output in Centre Aligned Mode ............................................. 1015
Figure 6.22-19 Asymmetric PWM Output for ASPRLDM=00b .................................................. 1015
Figure 6.22-20 Asymmetric PWM Output for ASPRLDM=01b .................................................. 1016
Figure 6.22-21 Asymmetric PWM Output for ASPRLDM=10b .................................................. 1016
Figure 6.22-22 Enhanced PWM Interrupt Architecture.............................................................. 1017
Figure 6.23-1 QEI Clock Source Control ................................................................................... 1039
Figure 6.23-2 QEI Block Diagram.............................................................................................. 1040

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Figure 6.23-3 Noise Filter........................................................................................................... 1041
Figure 6.23-4 Noise Filter Sampling Clock Selection................................................................. 1041
Figure 6.23-5 QEA/QEB/IDX Timing Requirement through Noise Filter ................................... 1041
Figure 6.23-6 X4 Counting Mode............................................................................................... 1042
Figure 6.23-7 X2 Counting Mode............................................................................................... 1043
Figure 6.23-8 Compare Operation............................................................................................. 1045
Figure 6.23-9 QEI_CNT Reload/Reset Control.......................................................................... 1045
Figure 6.23-10 Trigger Control of Capturing QEI Counter......................................................... 1046
Figure 6.23-11 Capture and Latch QEI Counter........................................................................ 1047
Figure 6.23-12 Quadrature Encoder Interface Interrupt Architecture Diagram ......................... 1048
Figure 6.24-1 RTC Block Diagram............................................................................................. 1061
Figure 6.24-2 Tamper Detector and Spare Register.................................................................. 1061
Figure 6.25-1 SC Clock Control Diagram (4-bit Prescale Counter in Clock Controller) ............ 1091
Figure 6.25-2 SC Controller Block Diagram............................................................................... 1091
Figure 6.25-3 SC Data Character .............................................................................................. 1092
Figure 6.25-4 SC Activation Sequence...................................................................................... 1092
Figure 6.25-5 SC Warm Reset Sequence ................................................................................. 1093
Figure 6.25-6 SC Deactivation Sequence.................................................................................. 1094
Figure 6.25-7 Initial Character TS.............................................................................................. 1095
Figure 6.25-8 SC Error Signal.................................................................................................... 1095
Figure 6.26-1 SD Host Controller Block Diagram ...................................................................... 1127
Figure 6.27-1 SPI Block Diagram............................................................................................... 1152
Figure 6.27-2 SPI Master Mode Application Block Diagram...................................................... 1153
Figure 6.27-3 SPI Slave Mode Application Block Diagram........................................................ 1154
Figure 6.27-4 32-bit in One Transaction .................................................................................... 1155
Figure 6.27-5 Byte Reorder Function......................................................................................... 1156
Figure 6.27-6 Timing Waveform for Byte Suspend.................................................................... 1156
Figure 6.27-7 2-bit Mode System Architecture .......................................................................... 1157
Figure 6.27-8 2-bit Mode (Slave Mode) ..................................................................................... 1158
Figure 6.27-9 Bit Sequence of Dual Output Mode..................................................................... 1159
Figure 6.27-10 Bit Sequence of Dual Input Mode...................................................................... 1159
Figure 6.27-11 Bit Sequence of Quad Output Mode.................................................................. 1160
Figure 6.27-12 Bit Sequence of Quad Input Mode .................................................................... 1160
Figure 6.27-13 FIFO Mode Block Diagram................................................................................ 1161
Figure 6.27-14 SPI Timing in Master Mode ............................................................................... 1164
Figure 6.27-15 SPI Timing in Master Mode (Alternate Phase of SPICLK)................................ 1165

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Figure 6.27-16 SPI Timing in Slave Mode ................................................................................. 1165
Figure 6.27-17 SPI Timing in Slave Mode (Alternate Phase of SPICLK).................................. 1166
Figure 6.28-1 Timer Controller Block Diagram .......................................................................... 1185
Figure 6.28-2 Clock Source of Timer Controller ........................................................................ 1185
Figure 6.28-3 Continuous Counting Mode................................................................................. 1188
Figure 6.29-1 Watchdog Timer Clock Control............................................................................ 1201
Figure 6.29-2 Watchdog Timer Block Diagram.......................................................................... 1202
Figure 6.29-3 Timing of Interrupt and Reset Signal................................................................... 1204
Figure 6.30-1 Window Watchdog Timer Clock Control.............................................................. 1209
Figure 6.30-2 Window Watchdog Timer Block Diagram............................................................ 1209
Figure 6.30-3 Window Watchdog Timer Reset and Reload Behavior....................................... 1211
Figure 6.31-1 UART Clock Control Diagram.............................................................................. 1220
Figure 6.31-2 UART Block Diagram........................................................................................... 1221
Figure 6.31-3 Auto Flow Control Block Diagram........................................................................ 1222
Figure 6.31-4 IrDA Block Diagram............................................................................................. 1223
Figure 6.31-5 IrDA TX/RX Timing Diagram ............................................................................... 1224
Figure 6.31-6 LIN Frame Structure............................................................................................ 1225
Figure 6.31-7 Break Detection in LIN Mode............................................................................... 1227
Figure 6.31-8 Relationship between Break Detection and Frame Error Detection.................... 1228
Figure 6.31-9 LIN Sync Field Measurement .............................................................................. 1231
Figure 6.31-10 UART_BAUD Update Method ........................................................................... 1232
Figure 6.31-11 RS-485 Frame Structure ................................................................................... 1235
Figure 6.32-1 USB Device Controller Block Diagram ................................................................ 1267
Figure 6.33-1 USB 1.1 Host Controller Block Diagram.............................................................. 1328
Figure 6.34-1 USB OTG Controller Block Diagram ................................................................... 1366
Figure 6.34-2 HOST-Only Mode ................................................................................................ 1367
Figure 6.34-3 Device-Only Mode............................................................................................... 1367
Figure 6.34-4 ID-Dependent (ID Low)........................................................................................ 1368
Figure 6.34-5 ID-Dependent (ID High)....................................................................................... 1368
Figure 6.34-6 OTG Device......................................................................................................... 1369

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List of Tables
Table 1.1-1 Key Features Support Table....................................................................................... 19
Table 3.1-1 List of Abbreviations.................................................................................................... 37
Table 6.2-1 Address Space Assignments for On-Chip Controllers.............................................. 273
Table 6.2-2 Exception Model ....................................................................................................... 327
Table 6.2-3 Interrupt Number Table............................................................................................. 331
Table 6.2-4 Priority Grouping....................................................................................................... 349
Table 6.3-1 Power-down Mode Control Table ............................................................................. 365
Table 6.7-1 Initialization of a Transmit Object ............................................................................ 484
Table 6.7-2 Initialization of a Receive Object ............................................................................. 485
Table 6.7-3 CAN Bit Time Parameters........................................................................................ 490
Table 6.7-4 CAN Register Map for Each Bit Function................................................................ 503
Table 6.7-5 Error Code ................................................................................................................ 507
Table 6.7-6 Source of Interrupts .................................................................................................. 510
Table 6.7-7 IF1 and IF2 Message Interface Register................................................................. 513
Table 6.7-8 Structure of a Message Object in the Message Memory.......................................... 527
Table 6.9-1 Comparison of SHA Functions ................................................................................. 557
Table 6.10-1 Memory Map of Embedded Descriptor Table......................................................... 610
Table 6.10-2 Channel Priority Table ............................................................................................ 613
Table 6.11-1 Timing Control Parameter Settings......................................................................... 661
Table 6.12-1 Arbiter Arbitration Results....................................................................................... 682
Table 6.12-2 Different CAMCMR Setting and Type of Received Packet..................................... 703
Table 6.12-3 MII Management Function Configure Sequence.................................................... 718
Table 6.13-1 Memory Address Map............................................................................................. 754
Table 6.13-2 NUC442/NUC472 Boot Selection........................................................................... 756
Table 6.13-3 ISP Mode Command............................................................................................... 768
Table 6.15-1 I2C Status Code Description Table......................................................................... 836
Table 6.23-1 Direction of Count................................................................................................. 1044
Table 6.26-1 SD/SDHC Pad Assignment .................................................................................. 1127
Table 6.29-1 Watchdog Timer Interval Selection....................................................................... 1203
Table 6.30-1 Window Watchdog Prescaler Value Selection ..................................................... 1210
Table 6.30-2 CMPDAT Setting Limitation.................................................................................. 1211
Table 6.31-1 UART Interrupt Sources and Flag List in DMA Mode........................................... 1252
Table 6.31-2 UART Interrupt Sources and Flag List in Software Mode..................................... 1252
Table 6.31-3 Baud Rate Equation Table.................................................................................... 1255
Table 6.31-4 Baud Rate Equation Table.................................................................................... 1255

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1 GENERAL DESCRIPTION
NuMicro

NUC442/NUC472 General Description1.1 The NuMicroNUC442 Connectivity series with embedded Cortex®-M4F core with DSP
extensions and a Floating Point Unit runs up to 84 MHz with 256/512 Kbytes embedded flash
memories and 64K-byte embedded SRAM. It is also equipped with plenty of peripheral devices,
such as Timers, Watchdog Timers, RTC, PDMA, EBI, UART, Smart Card interface, SD HOST,
SPI, I2C, I2S, PWM Timer, GPIO, LIN, CAN, PS/2, 12-bit ADC, analog comparator, operational
amplifier, temperature sensor, Low Voltage Reset Controller and Brown-out Detector. The
NUC442 also provides USB 2.0 full-speed Device/Host/OTG, USB 2.0 HS device and security
functions such as tamper detection, symmetric cryptographic accelerator and secure Hash
function accelerator.
The NuMicroNUC472 Advanced series with embedded Cortex®-M4F core with DSP extensions
and a Floating Point Unit runs up to 84 MHz with 256/512 Kbytes embedded flash memories and
64K-byte embedded SRAM. It is also equipped with plenty of peripheral devices, such as Timers,
Watchdog Timers, RTC, PDMA, EBI, UART, Smart Card interface, SD HOST, SPI, I2C, I2S, PWM
Timer, GPIO, LIN, CAN, PS/2, 12-bit ADC, analog comparator, operational amplifier, temperature
sensor, Low Voltage Reset Controller and Brown-out Detector. The NUC472 also provides
Ethernet 10/100 MAC with MII and RMII interface, USB 2.0 full-speed Device/Host/OTG, USB 2.0
HS device and security functions such as tamper detection, symmetric cryptographic accelerator
and secure Hash function accelerator.
Product
Series Ethernet USB CAN SD Host UART SPI I2C Smart
Card
Interface Security ADC
NUC442 ●●●●●●●●●
NUC472 ●●●●●●●●●●
Table 1.1-1 Key Features Support Table
The NuMicroNUC442/NUC472 series is suitable for a wide range of applications such as:
Industrial Automation
PLCs
Inverters
Home Automation
Security Alarm System
Power Metering
Portable Data Collector
Portable RFID Reader
System Supervisors
USB Accessories
Smart Card Reader
Printer
POS
Motor Control

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2 FEATURES
NuMicro

NUC442 Features – Connectivity Series2.1
Core
– ARM®Cortex®-M4 core running up to 84 MHz
– Supports DSP extension
Supports hardware divider
– Supports IEEE 754 compliant Floating-point Unit (FPU)
– Supports Memory Protection Unit (MPU)
– One 24-bit system timer
– Supports low power sleep mode
Supports both WFI and WFE instructions
– Single-cycle 32-bit hardware multiplier
– Supports Nested Vectored Interrupt Controller (NVIC)
Supports programmable 256 level priorities for interrupts
– Supports programmable maskable interrupts
Build-in LDO for wide operating voltage ranged from 2.5 V to 5.5 V
Flash Memory
– 256/512 Kbytes Flash memory
– Configurable program code/data allocation
– ISP loader sizes 16 Kbytes
– Supports 2-wired ICP update through SWD/ICE interface
– Supports In-system program (ISP), In application program (IAP) update
– 2 Kbytes page erase for flash
– Supports fast parallel programming mode by external programmer
SRAM
– 64 Kbytes embedded SRAM
– 24 Kbytes SRAM with hardware parity check
– Supports byte-, half-word- and word-access parity check
– Supports exception (NMI) generated once a parity check error occurs
– Supports PDMA mode
PDMA (Peripheral DMA)
– Supports 16 independent configurable channels for automatic data transfer between
memories and peripherals
– Supports normal and Scatter-Gather Transfer modes
– Supports 2 types of priorities modes: fixed-priority and round-robin modes
– Supports byte-, half-word- and word-access
– Auto increment the source and destination address
– Supports 16-level FIFO
– Supports bus abort status flag
– Supports time out status flag
Clock Control
– Flexible selection for different applications
– Built-in 22.1184 MHz high speed RC oscillator for system operation (variation < 2% at
-40℃~ +105℃)
– Built-in 10 kHz low speed RC oscillator for Watchdog Timer and Wake-up operation
– Built-in 4~24 MHz high speed oscillator for external crystal input for precise timing
operation
– Built-in 32.768 kHz low speed oscillator for external crystal input for RTC function and
low power system operation