NXP Semiconductors i.MX6ULL User manual

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Content
1．NXP i.MX6ULL chip introduction...................................................................................................1
2. WT-SOM6ULX schematic and testing description...........................................................3
2.1 WT-SOM6ULX diagram and shematic .................................................................................................3
2.2 WT-SOM6ULX power management.....................................................................................................4
2.3 i.MX6ULL related power supply domain’s ripple test ....................................................................4
3．Based WT-SOM6ULX’s baseboard power system design..........................................5
3.1 Core boards power on sequence and typical supply circuit ....................................................5
3.2 About reset ....................................................................................................................................................6
3.3 ON/OFF and wakeup .................................................................................................................................7
4. Startup related circuit design ....................................................................................................................7
4.1 Startup mode and stardup device.........................................................................................................7
4.2 Other startup related hardware notice .......................................................................................... 10
5．TF/SD card circuit design ............................................................................................................. 10
6．LCD interface circuit........................................................................................................................... 11
7．Touch screen interface circuit...................................................................................................... 12
7.1 Resistive TP circuit.....................................................................................................................................13
7.2 Capacitive TP.............................................................................................................................................. 13
8. IIC interface................................................................................................................................................14
9. USB interface............................................................................................................................................. 15
10. Ethernet interface................................................................................................................................. 16
11. Serial port................................................................................................................................................... 19
12. Audio interface.......................................................................................................................................20
13. RTC circuit................................................................................................................................................. 21
14. PWM............................................................................................................................................................. 21
15. SPI ..................................................................................................................................................................21
16. CAN bus..................................................................................................................................................... 22
17. CSI camera interface........................................................................................................................... 23

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18. ADC interface.......................................................................................................................................... 23

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1．NXP i.MX6ULL chip introduction
i.MX6ULL is designed by NXP, high efficiency, cost effective application processor. With
advanced implementations of single core ARM Cortex-A7 running up to 900MHz. i.MX
6ULL application processor includes an integrated power management module that
reduce the complexity of the external power supply and simplifies power-up sequencing.
Applications include:
⚫Automotive telematics
⚫IoT gateway
⚫HMI human machine interface
⚫Home power management system
⚫Intelligent energy information concentrator
⚫Intelligent industrial control system
⚫Electronic POS equipment
⚫Portable medical equipment
⚫Printer and 2D scanner, etc.
i.MX6ULL block diagram

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i.MX6ULL Pin-to-Pin compatible chip and difference comparison
i.MX6ULL BGA289 package main chipset’s part number and parameter comparison list:
Parts
MCIMX6Y2CVM05AA
MCIMX6Y2CVM08AB
MCIMX6Y2DVM09AB
Marketing
Description
i.MX 32-bit MPU,
ARM Cortex-A7 core,
528MHz, 289BGA
i.MX 32-bit MPU,
ARM Cortex-A7 core,
800MHz, 289BGA
i.MX 32-bit MPU,
ARM Cortex-A7 core,
900MHz, 289BGA
Package Type
LFBGA289
LFBGA289
LFBGA289
Core Type
Arm Cortex-A7
Arm Cortex-A7
Arm Cortex-A7
Operating
Frequency
[Max] (MHz)
528
800
900
External
Memory
Supported
DDR3 SDRAM, DDR3L
SDRAM, LPDDR2
DRAM
DDR3 SDRAM, DDR3L
SDRAM, LPDDR2
DRAM
DDR3 SDRAM, DDR3L
SDRAM, LPDDR2
DRAM

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Video/Display
features
RGB
RGB
RGB
Ethernet
2
2
2
SPI
4
4
4
I2C
4
4
4
UART
8
8
8
SAI
3
3
3
USB
Controllers
2
2
2
CAN
2
2
2
Work
Temperature
(℃)
-40 ~ 105
-40 ~ 105
0 ~ 95
Camera
Interfaces
CSI
CSI
CSI
Audio Specific
Modules
SPDIF
WT-SOM6ULX supports i.MX6UltraLite and i.MX6ULL all BGA289 part numbers. Main
production model is i.MX6ULL series MCIMX6Y2CVM08AB, Other models produced by
order.
2. WT-SOM6ULX schematic and test instruction
2.1 WT-SOM6ULX core board block diagram and schematic
For most applications, WT-SOM6ULX designed the smallest system Power Management +
DDR3L + NAND/EMMC+ LAN8720(Ethernet Phy).
WT-SOM6ULX smallest system block diagram
Core board schematic “wt-som6ulx-sch-v1.pdf”, you can get from sales representative.

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2.2 WT-SOM6ULX core board’s power management
According to i.MX6ULL power supply timing requirement, core board layout 4 power supply
pins: VSNVS，VSYS_3V3，USB_OTG2_VBUS，USB_OTG1_VBUS.
VSNVS have to powered first, backup battery power can be used for button ON/OFF switch
control, low power consumption, maintenance internal RTC power supply after
shutdown, only consume 26uA.
VSYS_3V3 is the main power supply for the core board, full load current consumption
<200mA.
USB_OTG2_VBUS and USB_OTG1_VBUS powered after VSYS_3V3. When you don’t need to
use the USB function, you don’t need to supply power.
Power supply pin
Min
Max
Current
Power supply
ripple
requirement
VSYS_3V3
3.2V
3.4V
<200mA(full speed
operation)
<9mA (standby)
<30mVrms
VSNVS
2.8V
3.4V
<500uA
<30mVrms
USB_OTG2_VBUS
4.7V
5.2V
<50mA
<50mVrms
USB_OTG1_VBUS
4.7V
5.2V
<50mA
<50mVrms
2.3 i.MX6ULL related power domain ripple test
WT-SOM6ULX adopts single-sided layout, which performs a lot of power integrity
simulation and optimization in the power supply part, and draws test points in the
CPU-related power domain and performs power supply ripple test.
Test conditions: DDR stress test status,
Test method: oscilloscope, 10X probe, AC coupling, 20mV, 1mS, bandwidth 20M
Test point
Power network
Ripple amplitude
(peak to peak)
Voltage (V)
TP18
VDD_ARM_CAP
29mV
1.272
TP12
VSYS_3V3
24mV
3.3
TP11
VDD_ARM_SOC_IN
22mV
1.348
TP19
DRAM_1V35
30mV
1.351
TP17
VDD_SOC_CAP
20mV
1.273
TP14
VDD_SNVS_CAP
20mV
1.107
TP15
NVCC_PLL_OUT
19mV
1.118
TP13
VDD_SNVS_3V3
24mV
3.297
TP16
VDD_HIGH_CAP
22mV
2.521

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TP20
DRAM_VREF
20mV
0.677
3．Based on WT-SOM6ULX’s baseboard power system design
3.1 Core board power sequencing and typical power supply circuit
⚫SNVS should be powered first and can be powered by LDO or backup battery
separately. SNVS should be powered first and can be powered separately by LDO
or backup battery. SNVS can be used for button ON/OFF switch control, low
current consumption, maintenance of internal RTC power supply after shutdown,
only consumes 26uA.
⚫After the SNVS is powered on, the core board pin PMIC_ON_REQ output is used to
control the VSYS_3V3 power switch. When the CPU enters the shutdown state,
PMIC_ON_REQ will be pulled low to turn off the entire board except the other
SNVS part. The 3.3V power supply for the baseboard and core board should use
the same power supply output to avoid potential risks due to level differences or
inconsistent power-up timing.
⚫5V power supply (USB_OTG1_VBUS, USB_OTG2_VBUS, CAN, RS485, etc.) should be
powered after the 3.3V power supply’s stable.
⚫For all IO pins, ensure that there is no high level input before VSYS_3V3 is powered
on.
The above is the power-on timing requirements of the NXP i.MX6ULL chip to ensure
long-term stable operation of the whole circuit board. If the timing requirements are
violated, the power-on behavior of the chip may be affected, resulting in a small
probability of chip damage or startup failure.

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WT-SOM6ULX typical power supply scheme
Power/GND pin
Pin number
Description
VSNVS
96
Have to be powered on first, and have to be powered
on when switch power management is required.
VSYS_3V3
97
Main power supply. Power supply is enabled via
PMIC_ON_REQ.
It is recommended that the string power supply use a
magnetic bead (such as 120R 3A) and then place a
2x22uF ceramic capacitor near the pin to form an LC
filter. Use low ripple DC/DC power supply. Ripple
<30mVrms.
USB_OTG1_VBUS
77
The MicroUSB VBUS input can be connected, also can
be disconnected, but it must be powered after
VSYS_3V3 powered on.
USB_OTG2_VBUS
76
Disconnected if no need to use USB function.
It must be powered after VSYS_3V3 is powered on,
5V.
Add 10uF ceramic capacitors near the pin.
GND
5, 35, 42, 55,
73, 78, 81,
98，115，126
Totally 10 GND pins.
The GND pin must be fully connected to the GND
plane of the baseboard (multiple vias or copper) to
optimize the return path for high speed signals.
3.2 About reset
In PWR_EN network control VSYS_3V3 的DC/DC chip enable pin. The WT-SOM6ULX has a
power-on reset chip on board, and the overall reset of the core board is recommended to
use a power-off reset. Typical mode: the output of the MAX811 is used to control the
VSYS_3V3 supply enable, which can be manually reset by a reset button or watchdog rest.
Refer to the circuit below, where the PWR_EN network controls the VSYS_3V3’s DC/DC chip
enable pin.

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3.3 Switch and wake up
i.MX6ULL chip provides the switch of power management function. It is connected to the
touch button through the ONOFF pin. When the VSNVS is powered, press about six seconds
to pull low the ONOFF. The PMIC_ON_REQ will be pulled low through the above circuit.
Connecting PMIC_ON_REQ to the enable of the VSYS_3V3 DC/DC chip will cause VSYS_3V3
to power down. Therefore, the whole board will be powered off except VSNVS. In the off
state, short press the switch button to pull the ONOFF pin low for about 2 seconds,
PMIC_ON_REQ will output a high level, then the whole board is powered on.
Sleep and wake up
Executing commands under Linux can put the system into a sleep state. At this time,
PMIC_STBY_REQ is pulled high. The power management circuit on the core board reduces
the core voltage VDD_SOC_IN to about 1.0V, and the core board VSYS_3V3 consumes
<=9mA. In the standby status, through IO or other interrupt wake-up (requires software
setting), PMIC_STBY_REQ is pulled low, the system will resume normal operation within 1S,
and the core voltage will be adjusted to about 1.3V.
4. Start related circuit design
4.1 start mode and boot device
i.MX6ULx family, the startup mode is determined by the level sampling of the
BOOT_MODE[1:0] pins during a Power-on Reset.
BOOT_MODE[1:0]
Boot Type
00
Boot From Fuses
01
Serial Downloader
10
Internal Boot
11
Reserved
When BOOT_MODE[1:0] is 00, From i.MX6ULX chip internal FUSE sonfigurartion specified
device and parameters to start
WT-SOM6ULX core board supports both NAND FLASH and EMMC. For regular device
models, FUSE parameters are provided to avoid cumbersome pin configurations. Therefore,
it is recommended to use the “Boot From Fuses” mode in applications that are
mass-produced or not ready to replace storage devices.
When BOOT_MODE[1:0] is 01, you can download and burn system image files including

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u-boot, zImage, dtb, rootfs, etc. through the Mfgtools programming tool (installed on
Windows system) provided by NXP official website.
When BOOT_MODE[1:0] is 10, the i.MX6ULx chip samples the level of LCD_DATA[23:0]
during power-on reset to determine the startup device and parameters. The specific
description is as follow:
The relationship between the level of LCD_DATA[23:0] during power-on and the internal
boot eFuse register is as follows:
The startup device and device parameters determined by the eFuse register configuration
are as follows: