NXP Semiconductors i.MX6ULL User manual

1
Content
1．NXP i.MX6ULL chip introduction...................................................................................................1
2. WT-SOM6ULX schematic and testing description...........................................................3
2.1 WT-SOM6ULX diagram and shematic .................................................................................................3
2.2 WT-SOM6ULX power management.....................................................................................................4
2.3 i.MX6ULL related power supply domain’s ripple test ....................................................................4
3．Based WT-SOM6ULX’s baseboard power system design..........................................5
3.1 Core boards power on sequence and typical supply circuit ....................................................5
3.2 About reset ....................................................................................................................................................6
3.3 ON/OFF and wakeup .................................................................................................................................7
4. Startup related circuit design ....................................................................................................................7
4.1 Startup mode and stardup device.........................................................................................................7
4.2 Other startup related hardware notice .......................................................................................... 10
5．TF/SD card circuit design ............................................................................................................. 10
6．LCD interface circuit........................................................................................................................... 11
7．Touch screen interface circuit...................................................................................................... 12
7.1 Resistive TP circuit.....................................................................................................................................13
7.2 Capacitive TP.............................................................................................................................................. 13
8. IIC interface................................................................................................................................................14
9. USB interface............................................................................................................................................. 15
10. Ethernet interface................................................................................................................................. 16
11. Serial port................................................................................................................................................... 19
12. Audio interface.......................................................................................................................................20
13. RTC circuit................................................................................................................................................. 21
14. PWM............................................................................................................................................................. 21
15. SPI ..................................................................................................................................................................21
16. CAN bus..................................................................................................................................................... 22
17. CSI camera interface........................................................................................................................... 23

2
18. ADC interface.......................................................................................................................................... 23

1
1．NXP i.MX6ULL chip introduction
i.MX6ULL is designed by NXP, high efficiency, cost effective application processor. With
advanced implementations of single core ARM Cortex-A7 running up to 900MHz. i.MX
6ULL application processor includes an integrated power management module that
reduce the complexity of the external power supply and simplifies power-up sequencing.
Applications include:
⚫Automotive telematics
⚫IoT gateway
⚫HMI human machine interface
⚫Home power management system
⚫Intelligent energy information concentrator
⚫Intelligent industrial control system
⚫Electronic POS equipment
⚫Portable medical equipment
⚫Printer and 2D scanner, etc.
i.MX6ULL block diagram

2
i.MX6ULL Pin-to-Pin compatible chip and difference comparison
i.MX6ULL BGA289 package main chipset’s part number and parameter comparison list:
Parts
MCIMX6Y2CVM05AA
MCIMX6Y2CVM08AB
MCIMX6Y2DVM09AB
Marketing
Description
i.MX 32-bit MPU,
ARM Cortex-A7 core,
528MHz, 289BGA
i.MX 32-bit MPU,
ARM Cortex-A7 core,
800MHz, 289BGA
i.MX 32-bit MPU,
ARM Cortex-A7 core,
900MHz, 289BGA
Package Type
LFBGA289
LFBGA289
LFBGA289
Core Type
Arm Cortex-A7
Arm Cortex-A7
Arm Cortex-A7
Operating
Frequency
[Max] (MHz)
528
800
900
External
Memory
Supported
DDR3 SDRAM, DDR3L
SDRAM, LPDDR2
DRAM
DDR3 SDRAM, DDR3L
SDRAM, LPDDR2
DRAM
DDR3 SDRAM, DDR3L
SDRAM, LPDDR2
DRAM

3
Video/Display
features
RGB
RGB
RGB
Ethernet
2
2
2
SPI
4
4
4
I2C
4
4
4
UART
8
8
8
SAI
3
3
3
USB
Controllers
2
2
2
CAN
2
2
2
Work
Temperature
(℃)
-40 ~ 105
-40 ~ 105
0 ~ 95
Camera
Interfaces
CSI
CSI
CSI
Audio Specific
Modules
SPDIF
WT-SOM6ULX supports i.MX6UltraLite and i.MX6ULL all BGA289 part numbers. Main
production model is i.MX6ULL series MCIMX6Y2CVM08AB, Other models produced by
order.
2. WT-SOM6ULX schematic and test instruction
2.1 WT-SOM6ULX core board block diagram and schematic
For most applications, WT-SOM6ULX designed the smallest system Power Management +
DDR3L + NAND/EMMC+ LAN8720(Ethernet Phy).
WT-SOM6ULX smallest system block diagram
Core board schematic “wt-som6ulx-sch-v1.pdf”, you can get from sales representative.

4
2.2 WT-SOM6ULX core board’s power management
According to i.MX6ULL power supply timing requirement, core board layout 4 power supply
pins: VSNVS，VSYS_3V3，USB_OTG2_VBUS，USB_OTG1_VBUS.
VSNVS have to powered first, backup battery power can be used for button ON/OFF switch
control, low power consumption, maintenance internal RTC power supply after
shutdown, only consume 26uA.
VSYS_3V3 is the main power supply for the core board, full load current consumption
<200mA.
USB_OTG2_VBUS and USB_OTG1_VBUS powered after VSYS_3V3. When you don’t need to
use the USB function, you don’t need to supply power.
Power supply pin
Min
Max
Current
Power supply
ripple
requirement
VSYS_3V3
3.2V
3.4V
<200mA(full speed
operation)
<9mA (standby)
<30mVrms
VSNVS
2.8V
3.4V
<500uA
<30mVrms
USB_OTG2_VBUS
4.7V
5.2V
<50mA
<50mVrms
USB_OTG1_VBUS
4.7V
5.2V
<50mA
<50mVrms
2.3 i.MX6ULL related power domain ripple test
WT-SOM6ULX adopts single-sided layout, which performs a lot of power integrity
simulation and optimization in the power supply part, and draws test points in the
CPU-related power domain and performs power supply ripple test.
Test conditions: DDR stress test status,
Test method: oscilloscope, 10X probe, AC coupling, 20mV, 1mS, bandwidth 20M
Test point
Power network
Ripple amplitude
(peak to peak)
Voltage (V)
TP18
VDD_ARM_CAP
29mV
1.272
TP12
VSYS_3V3
24mV
3.3
TP11
VDD_ARM_SOC_IN
22mV
1.348
TP19
DRAM_1V35
30mV
1.351
TP17
VDD_SOC_CAP
20mV
1.273
TP14
VDD_SNVS_CAP
20mV
1.107
TP15
NVCC_PLL_OUT
19mV
1.118
TP13
VDD_SNVS_3V3
24mV
3.297
TP16
VDD_HIGH_CAP
22mV
2.521

5
TP20
DRAM_VREF
20mV
0.677
3．Based on WT-SOM6ULX’s baseboard power system design
3.1 Core board power sequencing and typical power supply circuit
⚫SNVS should be powered first and can be powered by LDO or backup battery
separately. SNVS should be powered first and can be powered separately by LDO
or backup battery. SNVS can be used for button ON/OFF switch control, low
current consumption, maintenance of internal RTC power supply after shutdown,
only consumes 26uA.
⚫After the SNVS is powered on, the core board pin PMIC_ON_REQ output is used to
control the VSYS_3V3 power switch. When the CPU enters the shutdown state,
PMIC_ON_REQ will be pulled low to turn off the entire board except the other
SNVS part. The 3.3V power supply for the baseboard and core board should use
the same power supply output to avoid potential risks due to level differences or
inconsistent power-up timing.
⚫5V power supply (USB_OTG1_VBUS, USB_OTG2_VBUS, CAN, RS485, etc.) should be
powered after the 3.3V power supply’s stable.
⚫For all IO pins, ensure that there is no high level input before VSYS_3V3 is powered
on.
The above is the power-on timing requirements of the NXP i.MX6ULL chip to ensure
long-term stable operation of the whole circuit board. If the timing requirements are
violated, the power-on behavior of the chip may be affected, resulting in a small
probability of chip damage or startup failure.

6
WT-SOM6ULX typical power supply scheme
Power/GND pin
Pin number
Description
VSNVS
96
Have to be powered on first, and have to be powered
on when switch power management is required.
VSYS_3V3
97
Main power supply. Power supply is enabled via
PMIC_ON_REQ.
It is recommended that the string power supply use a
magnetic bead (such as 120R 3A) and then place a
2x22uF ceramic capacitor near the pin to form an LC
filter. Use low ripple DC/DC power supply. Ripple
<30mVrms.
USB_OTG1_VBUS
77
The MicroUSB VBUS input can be connected, also can
be disconnected, but it must be powered after
VSYS_3V3 powered on.
USB_OTG2_VBUS
76
Disconnected if no need to use USB function.
It must be powered after VSYS_3V3 is powered on,
5V.
Add 10uF ceramic capacitors near the pin.
GND
5, 35, 42, 55,
73, 78, 81,
98，115，126
Totally 10 GND pins.
The GND pin must be fully connected to the GND
plane of the baseboard (multiple vias or copper) to
optimize the return path for high speed signals.
3.2 About reset
In PWR_EN network control VSYS_3V3 的DC/DC chip enable pin. The WT-SOM6ULX has a
power-on reset chip on board, and the overall reset of the core board is recommended to
use a power-off reset. Typical mode: the output of the MAX811 is used to control the
VSYS_3V3 supply enable, which can be manually reset by a reset button or watchdog rest.
Refer to the circuit below, where the PWR_EN network controls the VSYS_3V3’s DC/DC chip
enable pin.

7
3.3 Switch and wake up
i.MX6ULL chip provides the switch of power management function. It is connected to the
touch button through the ONOFF pin. When the VSNVS is powered, press about six seconds
to pull low the ONOFF. The PMIC_ON_REQ will be pulled low through the above circuit.
Connecting PMIC_ON_REQ to the enable of the VSYS_3V3 DC/DC chip will cause VSYS_3V3
to power down. Therefore, the whole board will be powered off except VSNVS. In the off
state, short press the switch button to pull the ONOFF pin low for about 2 seconds,
PMIC_ON_REQ will output a high level, then the whole board is powered on.
Sleep and wake up
Executing commands under Linux can put the system into a sleep state. At this time,
PMIC_STBY_REQ is pulled high. The power management circuit on the core board reduces
the core voltage VDD_SOC_IN to about 1.0V, and the core board VSYS_3V3 consumes
<=9mA. In the standby status, through IO or other interrupt wake-up (requires software
setting), PMIC_STBY_REQ is pulled low, the system will resume normal operation within 1S,
and the core voltage will be adjusted to about 1.3V.
4. Start related circuit design
4.1 start mode and boot device
i.MX6ULx family, the startup mode is determined by the level sampling of the
BOOT_MODE[1:0] pins during a Power-on Reset.
BOOT_MODE[1:0]
Boot Type
00
Boot From Fuses
01
Serial Downloader
10
Internal Boot
11
Reserved
When BOOT_MODE[1:0] is 00, From i.MX6ULX chip internal FUSE sonfigurartion specified
device and parameters to start
WT-SOM6ULX core board supports both NAND FLASH and EMMC. For regular device
models, FUSE parameters are provided to avoid cumbersome pin configurations. Therefore,
it is recommended to use the “Boot From Fuses” mode in applications that are
mass-produced or not ready to replace storage devices.
When BOOT_MODE[1:0] is 01, you can download and burn system image files including

8
u-boot, zImage, dtb, rootfs, etc. through the Mfgtools programming tool (installed on
Windows system) provided by NXP official website.
When BOOT_MODE[1:0] is 10, the i.MX6ULx chip samples the level of LCD_DATA[23:0]
during power-on reset to determine the startup device and parameters. The specific
description is as follow:
The relationship between the level of LCD_DATA[23:0] during power-on and the internal
boot eFuse register is as follows:
The startup device and device parameters determined by the eFuse register configuration
are as follows:

9
Note: When the boot device specified by FUSE does not have a boot program available
(such as DCD command), i.MX6ULL will first jump to the MMC/SD1 device boot mode, try to
boot from the SD/TF card, if no boot program is available, then finally enter "Serial
Downloader" mode.
Therefore, after i.MX6ULL has internally programmed FUSE, you can still enter SD/TF card
boot or "Serial Downloader" mode by setting BOOT_MODE[1:0] to 10, "Internal Boot" mode.
In order to simplify the complexity of the LCD configuration and to avoid the LCD screen
driver lead uncertainty into the LCD_DATA[23:0] level sampling, it is recommended to use
the default boot mode from "Boot from fuse".

10
4.2 Other hardware considerations related to startup
1) u-boot and Linux currently use UART1 as the debug serial port to print system
messages. It should be layout from the baseboard and can be connected to the
UART-USB bridge chip or connected to the PC via the RS232 interface convert chip.
2) Lead the SD1 interface to the SD card/TF card holder as much as possible. When the
core board NAND FLASH/EMMC does not start the program, the system can be booted
through SD1. Note that the UART1_RTS pin is used as the SD card detection pin by
default. If the card is not detected, a 10K pull-down resistor can be added to the
UART1_RTS pin.
3) Layout USB_OTG1_DN/USB_OTG1_DP to the MicroUSB holder as much as possible, and
download the system software through NXP's Mfgtools tool.
5．TF/SD card circuit design
i.MX6ULL supports two high speed MMC/SD interfaces. Characters as follows:
•Conforms to the SD Host Controller Standard Specification version 3.0
•Compatible with the MMC System Specification version 4.2/4.3/4.4/4.41/4.5
•Compatible with the SD Memory Card Specification version 3.0 and supports the
Extended Capacity SD Memory Card
•Compatible with the SDIO Card Specification version 3.0
•Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD
Combo, MMC, MMC plus, and MMC RS cards
•Card bus clock frequency up to 208 MHz
•Supports 1-bit / 4-bit SD and SDIO modes, 1-bit / 4-bit / 8-bit MMC modes
The MMC/SD1 pin is fixed. When the default boot device fails to boot, it will attempt to boot
from the SD1 connected SD/TF card.
The MMC/SD2 pin can be configured. When the core board adopts EMMC, the MMC/SD2 is
used, and the pin is multiplexed with the NAND pin. When the core board adopts NAND
FLASH, MMC/SD2 can be extended by multiplexing CSI or LCD pins, or connected to EMMC,
or connected to SD/TF card, or connected to SDIO interface module (such as WIFI module).
The i.MX6ULL MMC/SD clock is up to 208MHz. In the design, the SDIO bus series matching
resistor (usually 22R, placed close to the core board pin) must be used for the same length
processing. The characteristic impedance is controlled at about 50 ohms.
The schematic diagram of the SD1 connection TF card holder reference is as follows:

11
MMC/SD1 connect SD card schematic diagram
MMC/SD2 pin assignment:
MMC/SD2 pin
Multiplex NAND pin
group (core board
solder EMMC)
Multiplex CSI pin
group (core board
solder NAND)
Multiplex LCD pin
group(core board
solder NAND)
SD2_CLK
NAND_RE_B
CSI_VSYNC
LCD_DATA19
SD2_CMD
NAND_WE_B
CSI_HSYNC
LCD_DATA18
SD2_DATA0
NAND_DATA00
CSI_DATA00
LCD_DATA20
SD2_DATA1
NAND_DATA01
CSI_DATA01
LCD_DATA21
SD2_DATA2
NAND_DATA02
CSI_DATA02
LCD_DATA22
SD2_DATA3
NAND_DATA03
CSI_DATA03
LCD_DATA23
SD2_DATA4
NAND_DATA04
CSI_DATA04
LCD_DATA14
SD2_DATA5
NAND_DATA05
CSI_DATA05
LCD_DATA15
SD2_DATA6
NAND_DATA06
CSI_DATA06
LCD_DATA16
SD2_DATA7
NAND_DATA07
CSI_DATA07
LCD_DATA17
6．LCD interface circuit
i.MX6ULL LCD interface characteristics:
⚫LCDIF supports one parallel 24-bit LCD display with up to WXGA (1366 x 768)
⚫resolution at 60 Hz
⚫8/16/18/24/32 bit LCD data bus support available depending on I/O mux options.
⚫Support PXP 2D graphics acceleration
TFT LDC display is connected to RGB24 (RGB888) or RGB18 (RGB666). Pin definition as
follows:

12
LCD pin
Core board pin
number
RGB24 (RGB888)
RGB18 (RGB666)
LCD_DATA23
6
R7 red data MSB
-
LCD_DATA22
7
R6
-
LCD_DATA21
8
R5
-
LCD_DATA20
9
R4
-
LCD_DATA19
10
R3
-
LCD_DATA18
11
R2
-
LCD_DATA17
12
R1
R5 red data MSB
LCD_DATA16
13
R0 red data LSB
R4
LCD_DATA15
14
G7 green data MSB
R3
LCD_DATA14
15
G6
R2
LCD_DATA13
16
G5
R1
LCD_DATA12
17
G4
R0 red data LSB
LCD_DATA11
18
G3
G5green data MSB
LCD_DATA10
19
G2
G4
LCD_DATA9
20
G1
G3
LCD_DATA8
21
G0 green dataLSB
G2
LCD_DATA7
22
B7 blue dataMSB
G1
LCD_DATA6
23
B6
G0 green data LSB
LCD_DATA5
24
B5
B5 blue data MSB
LCD_DATA4
25
B4
B4
LCD_DATA3
26
B3
B3
LCD_DATA2
27
B2
B2
LCD_DATA1
28
B1
B1
LCD_DATA0
29
B0 blue data LSB
B0 blue data LSB
LCD_VSYNC
31
LCD vertical synchronization
LCD_HSYNC
32
LCD horizontal synchronization
LCD_PCLK
33
LCD pixel clock
LCD_DE
34
LCD data enable
LCD signal line design considerations:
⚫All signal lines in series with matched resistors (typically 22R) and placed close to
the core board pins.
⚫It is recommended to use a trace with a characteristic impedance of 50 ohms.
⚫The length of the line is equal, and the relative length error is <=400mil
7．Touch screen interface circuit
i.MX6ULL built in ADC controller, support 4-wire resistive touch screen. At the same time, the
capacitive touch screen is supported through the I2C/USB interface.

13
7.1 resistance TP circuit
Resistance TP pin definition:
Core board pin definition
Core board pin number
Resistance TP definition
GPIO1_IO04
91
X+
GPIO1_IO03
92
X-
GPIO1_IO02
93
Y+
GPIO1_IO01
94
Y-
Resistance TP use and connection mode reference:
Resistance TP structure diagram
i.MX6ULL connect 4-wire resistance TP schematic
7.2 capacitance TP
A common capacitor TP circuit diagram based on I2C interface is as follows:

14
Capacitor TP interface circuit
Among them, the RST (reset pin) and INT (interrupt pin) of the capacitor TP can be
configured as any pin with GPIO function.
8. IIC interface
i.MX6ULL provides up to 4 I2C interfaces. It can be flexibly allocated through pin
multiplexing.
I2C1 signal reusable list
I2C1 signal
Core board pin name
Core board pin number
I2C1_SCL
CSI_PIXCLK
44
GPIO1_IO02
93
UART4_TX_DATA
112
I2C1_SDA
CSI_MCLK
43
GPIO1_IO03
92
UART4_RX_DATA
111
I2C2 signal reusable list
I2C2 signal
Core board pin name
Core board pin number
I2C2_SCL
CSI_HSYNC
46
GPIO1_IO00
95
UART5_TX_DATA
113
I2C2_SDA
CSI_VSYNC
45
GPIO1_IO01
94
UART5_RX_DATA
114

15
I2C3 signal reusable list
I2C3 signal
Core board pin name
Core board pin number
I2C3_SCL
ENET2_RXD0
119
LCD_DATA1
28
UART1_TX_DATA
102
I2C3_SDA
ENET2_RXD1
118
LCD_DATA0
29
UART1_RX_DATA
101
I2C4 signal reusable list
I2C4 signal
Core board pin name
Core board pin number
I2C4_SCL
ENET2_TXEN
121
LCD_DATA3
26
UART2_TX_DATA
106
I2C4_SDA
ENET2_TXD0
123
LCD_DATA2
27
UART2_RX_DATA
105
9. USB interface
i.MX6ULL have 2 way USB 2.0 controller. Each USB OTG controller core can operate in High
Speed operation (480 Mbps), Full Speed operation (12 Mbps) and Low Speed operation (1.5
Mbps).
2 way USB related pin
USB signal name
Function description
Reusable pin
Pin number
USB_OTG2_VBUS
USB power supply pin
(5V input)
-
76
USB_OTG2_DP
USB Differential signal
-
72
USB_OTG2_DN
USB Differential signal
-
71
USB_OTG2_ID
USB ID signal
ENET2_TX_CLK
120
GPIO1_IO05
90
SD1_DATA3
38
USB_OTG2_OC
USB power overcurrent
signal (input)
ENET2_TXEN
121
GPIO1_IO03
92
SD1_DATA2
39
USB_OTG2_PWR
USB power output
control signal
ENET2_TXD1
122
GPIO1_IO02
93
SD1_DATA1
40
USB_OTG1_VBUS
VBUS power input（5V）
-
77
USB_OTG1_DP
USB differential signal
-
74

16
USB_OTG1_DN
USB differential signal
-
75
USB_OTG1_ID
OTG ID signal
GPIO1_IO00
95
SD1_DATA0
41
UART3_TX_DATA
110
USB_OTG1_OC
USB power overcurrent
signal (input)
ENET2_RXD1
118
GPIO1_IO01
94
SD1_CLK
36
USB_OTG1_PWR
USB power output
control signal
ENET2_RXD0
119
GPIO1_IO04
91
SD1_CMD
37
USB interface circuit design notice
About USB power supply, USB_OTG2_VBUS and USB_OTG1_VBUS may not be powered if
the USB function is not used. If the USB function is used, the USB_OTG2_VBUS must be
powered by 5V, and the power-on sequence is after VSYS_3V3. USB_OTG1_VBUS can be
used as an OTG VBUS input, it have to ensure to allow USB_OTG1_VBUS input power after
VSYS_3V3.
The system defaults OTG1 as a USB Device to facilitate the Mfgtools tool to download and
program system programs.
When more than 2 USB Hosts are required, they are generally extended by a USB Hub chip
(such as USB2514).
10. Ethernet interface
i.MX6ULL implements a dual-speed 10/100-Mbit/s Ethernet MAC compliant with the
IEEE802.3-2002 standard. The MAC layer provides compatibility with half- or full duplex
10/100-Mbit/s Ethernet LANs.
A LAN8720A Ethernet physical chip has been installed on the WT-SOM6ULX core board. It is
connected to the ENET1 RMII interface and extends the ETH1 receive and transmit
differential pair signal and LED indicator through the core board pins. The LAN8720A is a
low-power 10/100Mbps adaptive Ethernet physical chip from MICROCHIP that supports HP
Auto-MDIX features.
The WT-SOM6ULX core board extends the corresponding pins of the ENET2 RMII interface,
as well as the MDIO/MDC pins. A LAN8720A can be extended on the baseboard to
implement dual network port configuration.
ENET1 extended pin description
Pin name
Pin
number
Pin description
ETH1_TXN
1
ENET1 transmit-/ data A-
ETH1_TXP
2
ENET1 transmit+/ data A+
ETH1_RXN
3
ENET1 receive-/ data B-
ETH1_RXP
4
ENET1 receive+/ data B+

17
ETH1X_LED1
128
Lan8720A Link activity LED Active High
ETH1X_LED2
127
LAN8720A Speed LED(100M or 10Mbps) Active Low
ENET1 connect RJ45 reference schematic as below:
ENET1 connect RJ45 schematic
When there is a dual network port requirement, the ENET2 can be extended by connecting
the LAN8720A through the ENET2 RMII interface.
ENET2 RMII interface signal definition and related pin list:
ENET2 RMII
interface
Core board pin
number
Description
ENET2_CRS_DV
116
RMII RX Enable
ENET2_RXER
117
RMII PHY error detect
ENET2_RXD1
118
RMII Data1 receive from PHY
ENET2_RXD0
119
RMII Data0 receive from PHY
ENET2_TX_CLK
120
RMII 50MHZ Clock from MAC to PHY
ENET2_TXEN
121
RMII TX Enable
ENET2_TXD1
122
RMII Data1 transmit to PHY
ENET2_TXD0
123
RMII Data0 transmit to PHY
ENET_MDC
124
SMI Clock 2.5MHz
ENET_MDIO
125
SMI MDIO, already pulled up with 1.5K on

18
WT-SOM6ULX module
Precautions:
1．The SMI serial bus ENET_MDC, ENET_MDIO is not configurable for other functions unless
the core board LAN8720A is not installed. ENET_MDIO has been pulled up from 1.5K
ohms to 3.3V on the core board.
2．ENET1 and ENET2 share the same set of SMI serial bus (ENET_MDC, ENET_MDIO), so the
two PHY chips must be configured with different PHY addresses. The LAN8720A PHY
address installed on the WT-SOM6ULX module default is configured to 0x00. Therefore,
if ENET2 is extended on the baseboard, the PHY address can’t be 0x00. If the LAN8720A
is used to extend ENET2, the PHY address must be configured to 0x1, and the LAN8720A
PHYAD0 configuration pin (pin 10) must be pulled up from 10K ohms to 3.3V.
3．ENET2 RMII interface should be connected in series with matching resistors (generally
about 22R), the series match resistor must be close to the signal output pin. RMII routing
should be treated as equal length.
ENET2 extended schematic (LAN8720A)