NXP Semiconductors i.MX 8M Plus User manual

i.MX 8M Plus Hardware Developer’s Guide
NXP Semiconductors Document identifier: IMX8MPHDG
User's Guide Rev. 0, 03/2021

Chapter 1
Overview
This document aims to help hardware engineers design and test the i.MX 8M Plus series processors. It provides examples on
board layout and design checklists to ensure first-pass success, and solutions to avoid board bring-up problems.
Engineers should understand board layouts and board hardware terminology.
This guide is released with relevant device-specific hardware documentation, such as datasheets, reference manuals, and
application notes. All these documents are available on www.nxp.com/imx8mplusevk.
1.1 Device supported
This document supports the i.MX 8M Plus (15 x 15 mm package).
1.2 Essential references
This guide is supplementary to the i.MX 8M Plus series chip reference manuals and data sheets. For reflow profile and thermal
limits during soldering, see General Soldering Temperature Process Guidelines (document AN3300). These documents are
available on www.nxp.com/i.MX8MPLUS.
1.3 Supplementary references
1.3.1 General information
The following documents introduces the Arm® processor architecture and computer architecture.
• For information about the Arm Cortex-A53 processor, see www.arm.com/products/processors/cortex-a/cortex-a53-
processor.php
• For information about the Arm Cortex-M7 processor, see https://www.arm.com/products/processors/cortex-m/cortex-m7-
processor.php
• Computer Architecture - A Quantitative Approach (Fourth Edition) - John L. Hennessy and David A. Patterson
• Computer Organization and Design - The Hardware/Software Interface (Second Edition) - David A. Patterson and John L.
Hennessy
The following documentation introduces the high-speed board design:
• Right the First Time- A Practical Handbook on High Speed PCB and System Design - Volumes I & II - Lee W. Ritchey
(Speeding Edge) - ISBN 0-9741936- 0-72
• Signal and Power Integrity Simplified (2nd Edition) - Eric Bogatin (Prentice Hall)- ISBN 0-13-703502-0
• High Speed Digital Design- A Handbook of Black Magic - Howard W. Johnson & Martin Graham (Prentice Hall) - ISBN
0-13-395724-1
• High Speed Signal Propagation- Advanced Black Magic - Howard W. Johnson & Martin Graham - (Prentice Hall) - ISBN
0-13-084408-X
• High Speed Digital System Design- A handbook of Interconnect Theory and Practice - Hall, Hall and McCall (Wiley
Interscience 2000) - ISBN 0-36090-2
• Signal Integrity Issues and Printed Circuit Design - Doug Brooks (Prentice Hall) ISBN 0-13-141884-X
• PCB Design for Real-World EMI Control - Bruce R. Archambeault (Kluwer Academic Publishers Group) - ISBN
1-4020-7130-2
• Digital Design for Interference Specifications - A Practical Handbook for EMI Suppression -David L. Terrell & R. Kenneth
Keenan (Newnes Publishing) - ISBN 0-7506-7282-X
NXP Semiconductors
i.MX 8M Plus Hardware Developer’s Guide, Rev. 0, 03/2021
User's Guide 2 / 50

• Electromagnetic Compatibility Engineering - Henry Ott (1st Edition - John Wiley and Sons) - ISBN 0-471-85068-3
• Introduction to Electromagnetic Compatibility - Clayton R. Paul (John Wiley and Sons) - ISBN 978-0-470-18930-6
• Grounding & Shielding Techniques - Ralph Morrison (5th Edition - John Wiley & Sons) - ISBN 0-471-24518-6
• EMC for Product Engineers - Tim Williams (Newnes Publishing) - ISBN 0-7506- 2466-3
1.4 Related documentation
Additional literature will be published in the future.
For the list of current documents, see i.MX8MPLUS and AN4579.
1.5 Conventions
Table 1 lists the notational conventions used in this document.
Table 1. Conventions used in the document
Conventions Description
Courier Used to indicate commands, command parameters, code examples, and file and directory names.
Italics Used to indicates command or function parameters.
Bold Function names are written in bold.
cleared/set When a bit takes the value zero, it means to be cleared; when it takes a value of one, it means to be set.
mnemonics Instruction mnemonics are shown in lowercase bold. Book titles in text are set in italics.
sig_name Internal signals are written in all lowercase.
nnnn nnnnh Denotes hexadecimal number
0b Denotes binary number
rA, rB Instruction syntax used to identify a source GPR
rD Instruction syntax used to identify a destination GPR
REG[FIELD] Abbreviations for registers are shown in uppercase. Specific bits, fields, or ranges appear in brackets. For
example, MSR[LE] refers to the little-endian mode enable bit in the machine state register.
x An italicized x indicates an alphanumeric variable.
n, m An italicized n indicates a numeric variable.
In this document, notation for all logical, bit-wise, arithmetic, comparison, and assignment operations follow C
Language conventions.
1.6 Acronyms and abbreviations
Table 2 defines the acronyms and abbreviations used in this document.
NXP Semiconductors
Overview
i.MX 8M Plus Hardware Developer’s Guide, Rev. 0, 03/2021
User's Guide 3 / 50

Table 2. Definitions and acronyms
Acronym Definition
ARM Advanced RISC Machines processor architecture
BGA Ball Grid Array package
BOM Bill of Materials
BSDL Boundary Scan Description Language
CAN Flexible Controller Area Network peripheral
CCM Clock Controller Module
CSI MIPI Camera Serial Interface
DDR Dual Data Rate DRAM
DDR4 DDR4 DRAM
DDRC DDR Controller
DFP Downstream Facing Port (USB Type-C)
DRP Dual Role Port (USB Type-C)
ECSPI Enhanced Configurable SPI peripheral
EIM External Interface Module
ENET 10/100/1000 Mbps Ethernet MAC peripheral
EPIT Enhanced Periodic Interrupt Timer peripheral
ESR Equivalent Series Resistance
GND Ground
GPC General Power Controller
GPIO General Purpose Input/Output
I2C Inter-integrated Circuit interface
IBIS Input output Buffer Information Specification
IOMUX i.MX 8M Plus chip-level I/O multiplexing
JTAG Joint Test Action Group
KPP Keypad Port Peripheral
Table continues on the next page...
NXP Semiconductors
Overview
i.MX 8M Plus Hardware Developer’s Guide, Rev. 0, 03/2021
User's Guide 4 / 50

Table 2. Definitions and acronyms (continued)
Acronym Definition
LDB LVDS Display Bridge
LDO Low Drop-Out regulator
LPCG Low Power Clock Gating
LPDDR4 Low Power DDR4 DRAM
LVDS Low-Voltage Differential Signaling
ODT On-Die Termination
OTP One-Time Programmable
PCB Printed Circuit Board
PCIe PCI Express
PCISig Peripheral Component Interconnect Special Interest Group
PDN Power Distribution Network
PMIC Power Management Integrated Circuit
POR Power-On Reset
PTH Plated Through Hole PCB (that is, no microvias)
RGMII Reduced Gigabit Media Independent Interface (Ethernet)
RMII Reduced Media Independent Interface (Ethernet)
ROM Read-Only Memory
NXP Semiconductors
Overview
i.MX 8M Plus Hardware Developer’s Guide, Rev. 0, 03/2021
User's Guide 5 / 50

Chapter 2
i.MX 8M Plus design checklist
This document provides a design checklist for the i.MX 8M Plus (15 x 15 mm package) processor. The design checklist tables
recommend optimal design and provide explanations to help users understand better. All supplemental tables referenced by the
checklist appear in sections following the design checklist tables.
2.1 Design checklist table
Table 3. LPDDR4 recommendations (i.MX 8M Plus)
Check box Recommendations Explanation/Supplemental recommendations
1. Connect the DRAM_ZN ball on the processor (ball
R1) to a 240 Ω, 1% resistor to GND.
This is a reference used during DRAM output
buffer driver calibration.
2. The ZQ0 and ZQ1 balls on the LPDDR4 device
should be connected through 240Ω, 1% resistors to the
LPDDR4 VDD2 rail.
—
3. Place a 10 kΩ, 5% resistor to ground on the DRAM
reset signal.
This will ensure adherence to the JEDEC
specification until the control is configured and
starts driving the DDR.
4. The ODT_CA balls on the LPDDR4 device should be
connected directly to the LPDDR4 VDD2 rail.
LPDDR4 ODT on the i.MX 8M Plus is command-
based, making processor ODT_CA output
balls unnecessary.
5. The architecture for each chip inside the DRAM
package must be x 16.
The processor does not support byte mode
specified in JESD209-4B.
6. The processor ball MTEST (ball P2), should be left
unconnected.
These are observability ports for manufacturing
and are not used otherwise.
7. The VREF pin on the processor (ball R2) can be left
unconnected.
The VREF signal for LPDDR4 is generated
internally by the processor.
8. It is strongly suggested to use LPDDR4 if lower
power consumption is required since DLL-off mode is
not supported.
The LPDDR4 can operate at low frequency
without DLL-off mode.
Table 4. DDR4 recommendations (i.MX 8M Plus)
Check box Recommendations Explanation/Supplemental recommendations
1. Connect the ZQ(DRAM_ZN) ball on the processor
(ball R1) to individual 240 Ω, 1% resistors to GND.
This is a reference used during DRAM output
buffer driver calibration.
2. The ZQ ball on each DDR4 device should be
connected through individual 240 Ω, 1% resistors to
GND.
—
Table continues on the next page...
NXP Semiconductors
i.MX 8M Plus Hardware Developer’s Guide, Rev. 0, 03/2021
User's Guide 6 / 50

Table 4. DDR4 recommendations (i.MX 8M Plus) (continued)
Check box Recommendations Explanation/Supplemental recommendations
3. Place a 10 kΩ, 5% resistor to ground on the DRAM
reset signal.
This will ensure adherence to the JEDEC
specification until the control is configured and
starts driving the DDR.
4. The processor ball MTEST (ball P2), should be left
unconnected.
These are observability ports for manufacturing
and are not used otherwise.
5. If boundary scan mode of the DDR4 DRAM device
is to be used to test connectivity with the i.MX 8M
Plus, TEN pin of the DRAM device should be routed
to a test point and pulled to GND through a resistor.
Otherwise it can be directly connected to GND. See
Testing DDR4 connectivity using boundary scan for
details about the limitations of the DRAM_RESET_N
signal in the boundary scan mode.
TEN=HIGH makes the DDR4 DRAM device enter
boundary scan mode(connectivity test mode). For
normal operation, TEN must be LOW.
6. DLL-off mode is not supported, which means DDR4
cannot run in low frequency, such as 100 MTS.
The power consumption for low power mode
in DDR4 system will be higher compared with
LPDDR4 system.
Refer to i.MX 8M Plus data sheet for supported DDR chip selects and bus width configurations.
NOTE
Table 5. I2C recommendations
Check box Recommendations Explanation/Supplemental recommendations
1. Verify the target I2C interface clock rates
The I2C bus can only be operated as fast as the
slowest peripheral on the bus. If faster operation
is required, move the slow devices to another
I2C port.
2. Verify that there are no I2C address conflicts on any
of the I2C buses utilized
There are multiple I2C ports available on
chip, so if a conflict exists, move one of the
conflicting devices to a different I2C bus. If it
is impossible, use a I2C bus switch (NXP part
number PCA9646).
3. Do not place more than one set of pull-up resistors
on the I2C lines.
This could result in excessive loading and
potential incorrect operation. Choose the pull-
up value commensurate with the bus speed
being used.
4. Ensure that the VCC rail powering the i.MX 8M Plus
I2C interface balls matches the supply voltage used for
the pull-up resistors and the slave I2C devices.
Prevent device damage or incorrect operation due
to voltage mismatch.
NXP Semiconductors
i.MX 8M Plus design checklist
i.MX 8M Plus Hardware Developer’s Guide, Rev. 0, 03/2021
User's Guide 7 / 50

Table 6. JTAG recommendations
Check box Recommendations Explanation/Supplemental recommendations
1. Do not use external pullup or pulldown resistors on
JTAG_TDO.
JTAG_TDO is configured with an on-chip
keeper circuit and the floating condition is
actively eliminated.
2. Follow the recommendations for external pull-up and
pull-down resistors given in Table 15.
—
3. For normal operation, JTAG_MOD (ball G20) should
be pulled down using a 10KOhm resistor. To enter
boundary-scan mode, this pin should be pulled up
to NVCC_JTAG using a 2.2KOhm resistor. Please
reference “COMPLIANCE_PATTERNS” in the chip
BSDL file.
—
Table 7. Reset and ON/OFF recommendations
Check box Recommendations Explanation/Supplemental recommendations
1. The POR_B input must be asserted at powered
up and remain asserted until the last power rail for
devices required for system boot are at their working
voltage. This functionality is controlled by the PMIC
(PCA9450CHN) on EVK.
POR_B is driven by the PMIC. If a reset button is
used, it should be connected to the PMIC_RST_B
pin of the PMIC instead of directly connected
to POR_B pin of the CPU. When POR_B is
asserted (low) on the i.MX 8M Plus, the output
PMIC_ON_REQ remains asserted (high).
2. For portable applications, the ONOFF pin may be
connected to an ON/OFF SPST push-button switch to
ground. An external pull-up resistor is required on this
pin.
A brief connection to GND in OFF mode
causes the internal power management state
machine to change state to ON. In ON mode,
a brief connection to GND generates an interrupt
(intended to initiate a software-controllable power-
down). The connection to GND for approximate 5
seconds or more causes a forced OFF.
3. Connect GPIO1_IO02( WDOG_B, ball B6) to
external PMIC or reset IC to repower the system
except SNVS is strongly recommended.
i.MX8M Plus cannot be reset by internal reset
source in idle mode, repower is preferred. Some
peripherals like SD3.0, QSPI also need repower
during system reset.
4. GPIO1_IO02( WDOG_B, ball B6) is used as Cold
Reset. If using a PMIC other than PCA9450, an
external pull-up resistor (100 Kohm) might be required
to support boundary-scan mode.
In boundary-scan mode, WDOG_B is floating.
Without the external 100 Kohm pull up, WDOG_B
might repeatedly reset the system when entering
boundary-scan mode. The PCA9450 disables
WDOG_B reset by default, so will not be impacted.
NXP Semiconductors
i.MX 8M Plus design checklist
i.MX 8M Plus Hardware Developer’s Guide, Rev. 0, 03/2021
User's Guide 8 / 50

Table 8. PCIe recommendations
Check box Recommendations Explanation/Supplemental recommendations
1. Use an appropriate external PCIe reference clock
generator.
The NXP EVK board design uses an IDT
9FGV0241 device. However, NXP does not
recommend one supplier over another, and does
not suggest that this is the only clock generator
supplier. The device used should support all the
specs (jitter, accuracy, etc.).
2. The differential transmitters from the processor must
be AC coupled. It is recommended to use a 0.1 μF cap
on both the PCIE_TXP and PCIE_TXN outputs.
PCIe specification compliance requires AC
coupling at each transmitter. The receiver must be
DC coupled.
3. The PCIEx_RESREF ball (ball F16) should be
connected to the ground through a 8.2 K Ω, 1%
resistor.
—
Table 9. USB recommendations
Check box Recommendations Explanation/Supplemental recommendations
1. Connect a 200 Ω, 1% resistor to the ground on the
USBx_TXRTUNE ball (ball F10 and F12).
—
2. Route all USB differential signals with 90 Ω
differential impedance. —
3. ESD protection should be implemented at the
connector pins. Choose a low capacitance device
recommended for high-speed interfaces.
This will prevent potential damages to board
components from ESD.
4. USB1_DNU, USB2_DNU are not functional,
recommend to use common GPIO if USB identification
is needed.
—
5. If USB connector is MicroAB or MicroB,
USBx_VBUS must not connect directly to the 5 V
VBUS voltage of connector; Instead, this pin must be
isloated with an external 30 K 1% resistor.
—
6. PCB trace length of the USB3.0 TX/RX signals
should not exceed 6 inches in order for the eye
diagram to meet compliance test requirement.
—
Table 10. FlexSPI recommendations
Check box Recommendations Explanation/Supplemental recommendations
1. Read strobe(DQS) pad should be floated or with
a 10-18pF cap load to compensate SIO/SCK
pins load for high speed running, if the memory
device does not provide DQS.
There are three modes for the internal sample
clock for FlexSPI read data:
Dummy read strobe generated by
FlexSPI controller and looped back
Table continues on the next page...
NXP Semiconductors
i.MX 8M Plus design checklist
i.MX 8M Plus Hardware Developer’s Guide, Rev. 0, 03/2021
User's Guide 9 / 50

Table 10. FlexSPI recommendations
Check box Recommendations Explanation/Supplemental recommendations
internally(FlexSPIn_MCR0[RXCLKSRC] = 0x0),
can only reach 66Mhz operation frequency;
Dummy read strobe generated by FlexSPI
controller and looped back through the DQS
pad(FlexSPIn_MCR0[RXCLKSRC] = 0x1), can
reach 133Mhz operation frequency. In this mode,
this pin can be floated or put some cap loads on
board level to compensate SIO/SCK pins load;
Read strobe provided by memory device and input
from DQS pad(FlexSPIn_MCR0[RXCLKSRC] =
0x3), can reach 133Mhz operation frequency.
Table 11. Oscillator/Crystal recommendations
Check box Recommendations Explanation/Supplemental recommendations
1. Connect a 24 MHz crystal and a 510K Ω resistor
between 24M_XTALI and 24M_XTALO (balls G25 and
G26).
This crystal should have ESR not greater than 60
Ω, and be rated for a drive level of at least 100
µW. Follow the manufacturer’s recommendation
for loading capacitance. Use short traces between
the crystal and the processor, with a ground
plane under the crystal, load capacitors, and
associated traces.
2. Connect a 32.768 KHz crystal and a 4.7M Ω
feedback resistor (must install) between RTC_XTALI
and RTC_XTALO (balls J25 and J26). Alternatively, an
external 32.768 KHz clock can be fed into RTC_XTALI
to provide the RTC clock for the i.MX 8M Plus. See
item #3.
This crystal should have ESR not greater than 70
kΩ, and be rated for a drive level of at least 0.5
µW. Follow the manufacturer’s recommendation
for loading capacitance. Use short traces between
the crystal and the processor, with a ground
plane under the crystal, load capacitors, and
associated traces.
3. If using external 32.768 KHz clock rather than
a crystal to provide the RTC clock, it should be
connected to RTC_XTALI pin. The RTC_XTALO pin
should be connected to NVCC_SNVS_1P8 through a
100Kohm resistor.
The voltage level of this driving clock should
not exceed the voltage of the NVCC_SNVS_1P8
rail, or damage/malfunction may occur. The
RTC signal should not be driven if the
NVCC_SNVS_1P8 supply is OFF. For RTC
VIL and VIH voltage levels, see the latest
i.MX 8M Plus data sheet available at
www.nxp.com/i.MX8MPLUS.
Table 12. i.MX 8M Plus power/decoupling recommendations
Check box Recommendations Explanation/Supplemental recommendations
1. Comply with the power-up sequence guidelines
as described in the data sheet to guarantee reliable
operations of the device.
Any deviation from these sequences may result in
the following situations:
Table continues on the next page...
NXP Semiconductors
i.MX 8M Plus design checklist
i.MX 8M Plus Hardware Developer’s Guide, Rev. 0, 03/2021
User's Guide 10 / 50

Table 12. i.MX 8M Plus power/decoupling recommendations (continued)
Check box Recommendations Explanation/Supplemental recommendations
• Excessive current during power-up phase
• Prevention of the device from booting
• Irreversible damage to the processor (worst
case)
2. Maximum ripple voltage requirements
Common requirement for ripple noise peak-to-
peak value should be less than 5% of the supply
voltage nominal value.
3. If using PCA9450CHN PMIC to provide power, make
sure all the regulators have output L/C components
properly connected, even if unused.
Leaving any regulator output open will lead to
malfunction of the whole PMIC.
4. Check PMIC switcher output currents and the
switcher inductor current ratings are sufficient for the
Maximum supply currents ratings per rail as specified
within the data sheet.
When using an non-NXP PMIC, or scaling down a
power rail, insure the PMIC and inductor will meet
the maximum current demands of the system.
Note: Currents will be higher at hotter SoC
temperatures than at room temperature.
5. Suggest using 3.3 V for NVCC_ECSPI_HDMI rather
than 1.8 V.
It is easier to find 3.3 V to 5 V dedicated
HDMI DDC level shifter on the market, like NXP
PCA9507. No much choice for 1.8 V to 5 V
dedicated HDMI DDC level shifter.
Table 13. Decoupling capacitors recommendations (i.MX 8M Plus)
Checkbox Supply 0.22 µF 1 µF 4.7 µF 10 µF Notes
VDD_SOC,
VDD_ARM_PLL_0P8,
VDD_DRAM_PLL_0P8,
VDD_HDMI_0P8,
VDD_SAI_PLL_0P8
VDD_ANA1_0P8,
VDD_MIPI_0P8,
VDD_PCI_0P8,
VDD_USB_0P8
— 16 — 4
These 9 power rails are combined
on EVK
NVCC_DRAM — 7 — 2 —
VDD_ARM — 8 — 2 —
VDD_SNVS_0P8_CAP — 1 — — —
NVCC_SNVS_1P8 — 1 — — —
Table continues on the next page...
NXP Semiconductors
i.MX 8M Plus design checklist
i.MX 8M Plus Hardware Developer’s Guide, Rev. 0, 03/2021
User's Guide 11 / 50

Table 13. Decoupling capacitors recommendations (i.MX 8M Plus) (continued)
Checkbox Supply 0.22 µF 1 µF 4.7 µF 10 µF Notes
VDD_24M_XTAL_1P8,
VDD_EARC_1P8,
VDD_ANA1_1P8,
VDD_ANA2_1P8,
VDD_ARM_PLL_1P8,
VDD_AVPLL_1P8,
VDD_DRAM_PLL_1P8,
VDD_ANA0_1P8,
VDD_HDMI_1P8,
VDD_LVDS_1P8,
VDD_MIPI_1P8,
VDD_PCI_1P8,
VDD_SAI_PLL_1P8,
VDD_USB_1P8
— 9 — 1
These 14 power rails are combined
on EVK
NVCC_JTAG,
NVCC_NAND,
NVCC_SAI1_SAI5,
NVCC_SAI2_SAI3_SPDIF,
NVCC_GPIO,
NVCC_I2C_UART,
NVCC_ECSPI_HDMI,
NVCC_ENET,
NVCC_SD1,
NVCC_CLK,
PVCC_1P8
— 9 — 1
These 11 power rails are combined
on EVK
NVCC_SD2 1 — — — —
VDD_USB_3P3 1 — — — —
VDD_MIPI_1P2_CAP — — 1 — —
Capacitor part number used on EVK:
• 0.22 μF --- LMK063BJ224MP-F
• 1 μF --- 02016D105MAT2A
• 4.7 μF --- C1005X5R0J475M050BC
Table continues on the next page...
NXP Semiconductors
i.MX 8M Plus design checklist
i.MX 8M Plus Hardware Developer’s Guide, Rev. 0, 03/2021
User's Guide 12 / 50

Table 13. Decoupling capacitors recommendations (i.MX 8M Plus) (continued)
Checkbox Supply 0.22 µF 1 µF 4.7 µF 10 µF Notes
• 10 μF --- CL05A106MQ5NUNC
Table 14. PCB design recommendations
Check box Recommendations Explanation/Supplemental recommendations
1. High-speed signal traces have reference plane in
adjacent layer and are impedance-controlled.
Controlled impedance is the key factor to have
good signal integrity. Note that the reference
plane can only be GND or the signal’s own I/O
power. Do not use other nets as reference.
2. High-speed signal traces never cross gap or slot in
reference plane.
Crossing gap in reference plane will cause
reflection and increase crosstalk.
3. Place at least one GND stitching via within 50 mils of
signal via when switching reference planes.
GND stitching via can help keep impedance
continuous and reduce via crosstalk.
4. Appropriate delay matching is done for parallel bus. Signals within a bus should have delay time
matched to maintain timing margin.
5. The true and complementary signal of a differential
pair must have delay matched to within 1ps.
The true and complementary signal within
a differential pair should have delay time
tightly matched.
6. DDR interface passed SI simulation. Alternatively,
directly copy the EVK DDR layout design.
Generally, SI simulation should be performed for
DDR interface that runs at 4000 MT/s to ensure
stable working. If this is not feasible, just copy
the EVK DDR layout design as well as the board
stack-up and materials.
7. Place test point on key signals to ease debugging.
When placing test point on high-speed signal traces,
make sure its diameter is no more than 20mil and the
test point be directly placed on the trace with no stub.
Test points can bring excessive capacitance
and should be carefully handled on high-speed
signal traces.
8. Decoupling capacitors are placed as close to IC
power pins as possible.
This is to reduce the inductance from
decoupling capacitor to IC power pin, to improve
decoupling effectiveness.
2.2 JTAG signal termination
Table 15 is a JTAG termination chart showing what terminations should be placed on PCB designs.
Table 15. Recommended JTAG board terminations
JTAG signal I/O type External termination Comments
JTAG_TCK Input None Internal pulled up to NVCC_JTAG, no external
termination required
Table continues on the next page...
NXP Semiconductors
i.MX 8M Plus design checklist
i.MX 8M Plus Hardware Developer’s Guide, Rev. 0, 03/2021
User's Guide 13 / 50

Table 15. Recommended JTAG board terminations (continued)
JTAG signal I/O type External termination Comments
JTAG_TMS Input None Internal pulled up to NVCC_JTAG, no external
termination required
JTAG_TDI Input None Internal pulled up to NVCC_JTAG, no external
termination required
JTAG_TDO 3-state output None —
2.3 Signal termination for Boundary-scan
Table 16 is a signal termination chart showing what terminations should be placed on board designs to support Boundary-scan.
Table 16. Recommended board terminations for Boundary-scan
Signal I/O type External termination Comments
BOOT_MODE0 Input Pull Up
BOOT_MODE0, BOOT_MODE1,
BOOT_MODE2, BOOT_MODE3,
JTAG_MOD, POR_B must be at 111111 to
enter Boundary-scan mode.
BOOT_MODE1 Input Pull Up
BOOT_MODE2 Input Pull Up
BOOT_MODE3 Input Pull Up
JTAG_MOD Input Pull Up
POR_B Input Pull Up
GPIO1_IO02
(WDOG_B)
Input Pull Up If using a PMIC other than PCA9450, external
pull-up resistor (100 Kohm) is needed to
support boundary-scan mode.
2.4 General recommendations
More than one software operating environment can run on the i.MX 8M Plus platforms concurrently. Peripherals on these SoCs
are accessible to all software operating environments. Conflict occurs when more than one software operating environment
reads or writes the state of the same peripheral. Therefore, software operating environments must be isolated from each other
when accessing shared resources. For instance, if two operating environments read and write the same region of DRAM without
coordinating their access, results are unpredictable. The same behavior is applicable for peripheral registers, especially for the
IP modules which offer multiple logical channels. For example, GPIO, I2C, SPI, SAI, and DMA.
Therefore, any sharing of an IP module between Cortex-M and Cortex-A domains must be coordinated with the system software
architecture because software operating environments must be isolated from each other when accessing shared resources in
order to avoid safety/reliability issues.
Consider an example. Individual GPIO pins are aggregated into groups, each group is controlled by a single GPIO module.
Each GPIO module is a distinct peripheral that must be protected from conflicting access by different software operating
environments. For example, GPIO1 module be assigned as a shared peripheral for Linux on the Arm Cortex-A and RTOS on
the Cortex-M. Cortex-A and Cortex-M should obtain a semaphore lock before access to any pin of GPIO1 module is allowed.
If Cortex-A and Cortex-M attempt to access to GPIO1 module at the same time, which can result in lack of isolation leading to
safety/reliability issues.
NXP Semiconductors
i.MX 8M Plus design checklist
i.MX 8M Plus Hardware Developer’s Guide, Rev. 0, 03/2021
User's Guide 14 / 50

Another important note, resource allocation should assure any peripheral that has external signals pinned out and its IO resource
can be synchronously controlled by Cortex-A or Cortex-M in the corresponding software operating environment.
Not allocating correctly can result in lack of isolation leading to safety/reliability issues that can only be overcome with complex
software such as virtual drivers which indirectly, can affect the HW isolation of Software Domains and the peripheral performance.
In this case, customer needs to implement customized software solutions like: RPMSG Client/server-style cooperative device
drivers or Peripheral Exclusive Access using a Mutex solution implemented using SEMA42. Implementation on the i.MX 8M Plus
is up to the customer’s Software Architecture.
Under those circumstances, the Peripheral Modules have to be allocated to Software Systems per module basis and not a per
signal basis from board design phase.
NXP Semiconductors
i.MX 8M Plus design checklist
i.MX 8M Plus Hardware Developer’s Guide, Rev. 0, 03/2021
User's Guide 15 / 50

Chapter 3
i.MX 8M Plus layout/routing recommendations
3.1 Introduction
This chapter describes how to assist design engineers with the layout of an i.MX 8M Plus-based system.
3.2 Basic design recommendations
When using the Allegro design tool, the schematic symbol & PCB footprint created by NXP is recommended. When not using the
Allegro tool, use the Allegro footprint export feature (supported by many tools). If the export is not possible, create the footprint
per the package dimensions outlined in the product data sheet.
Native Allegro layout and gerber files are available on www.nxp.com/imx8mplusevk.
3.2.1 Placing decoupling capacitors
Place small decoupling and larger bulk capacitors on the bottom side of the PCB.
The 0201 or 0402 decoupling and 0603 or larger bulk capacitors should be mounted as close as possible to the power vias. The
distance should be less than 50 mils. Additional bulk capacitors can be placed near the edge of the BGA via array. Placing the
decoupling capacitors close to the power balls is critical to minimize inductance and ensure high-speed transient current required
by the processor. See the i.MX 8M Plus EVK layouts for the recommended decoupling capacitor placement.
The following list describes how to choose correct decoupling scheme:
• Place the largest capacitance in the smallest package that budget and manufacturing can support.
• For high-speed bypassing, select the required capacitance with the smallest package (for example, 1.0 μF, or even 2.2 μF
in a 0201 package size).
• Minimize trace length (inductance) to small caps.
• Series inductance cancels out capacitance.
• Tie caps to GND plane directly with a via.
• Place capacitors close to the power ball of the associated package from the schematic.
• A preferred BGA power decoupling design is available on the EVK board design available on www.nxp.com/
imx8mplusevk. Customers should use the NXP design strategy for power and decoupling.
3.3 Stack-up and manufacturing recommendations
3.3.1 Stack-up recommendation (i.MX 8M Plus)
Due to the number of balls on the i.MX 8M Plus processor in the 15 mm x 15 mm package, a minimum 6-layer PCB stack-up is
recommended. For the 6 layers on the PCB, at least 1 layer need to be dedicated to power on routing to meet the IR drop target
of 2% for the i.MX 8M Plus CPU power rails.
The constraints for the trace width will depend on such factors as the board stack-up and associated dielectric and copper
thickness, required impedance, and required current (for power traces). The stack-up also determines the constraints for routing
and spacing. Consider the following requirements when designing the stack-up and selecting board material:
• Board stack-up is critical for high-speed signal quality.
• Preplanning impedance of critical traces is required.
• High-speed signals must have reference planes on adjacent layers.
NXP Semiconductors
i.MX 8M Plus Hardware Developer’s Guide, Rev. 0, 03/2021
User's Guide 16 / 50

• PCB material: the material used on EVK is TU768.
3.3.2 Manufacturing recommendation (i.MX 8M Plus)
Since the i.MX 8M Plus processor uses 0.5mm-pitch BGA package, the PCB technology must meet below requirement to fully
fanout all the signals of the processor using PTH(plated through holes).
• Minimum trace width: 3.2mil
• Minimum trace to trace/pad spacing: 3.2mil
• Minimum via size: 8mil-diameter hole, 16mil-diameter pad
• Minimum via pad to pad spacing: 4mil
Figure 1 shows the reference routing of the i.MX 8M Plus, PTH is OK for the fanout, HDI is not needed.
Figure 1. i.MX 8M Plus fanout routing on EVK
3.3.3 EVK PCB stack-up (i.MX 8M Plus)
Table 17 and Table 18 show stack-up of the EVK. CPU board uses 6-layer stack-up and the BB board uses 8-layer stack-up.
Table 17. 8MPLUSLPD4-CPU Board stack up information
Layer Description Copper (Oz.) Generic Er Dielectric thickness (mil)
1 Signal 0.33+Plating 1.15 mil
Dielectric 1067 RC74% 3.49 2.5 mil
2 GND 1
Table continues on the next page...
NXP Semiconductors
i.MX 8M Plus layout/routing recommendations
i.MX 8M Plus Hardware Developer’s Guide, Rev. 0, 03/2021
User's Guide 17 / 50

Table 17. 8MPLUSLPD4-CPU Board stack up information (continued)
Layer Description Copper (Oz.) Generic Er Dielectric thickness (mil)
Dielectric Core 0.075MM 1/1 3.97 2.95 mil
3 Signal 1
Dielectric
7628 RC49%
2116 RC54%
2116 RC54%
7628 RC49%
4.15
4.01
4.01
4.15
26.4 mil
4 Power 1
Dielectric Core 0.075MM 1/1 3.97 2.95 mil
5 GND 1
Dielectric 1067 RC74% 3.49 2.5 mil
6 Signal 0.33+Plating 1.15 mil
Finished: 47.244(4.724/-4.724) mil 1.2(+0.12/-0.12) MM
Designed: 45.5 mil 1.156 MM
Material: TU768
Table 18. 8MPLUS-BB Board stack up information
Layer Description Copper (Oz.) Generic Er Dielectric thickness (mil)
1 Signal 0.5+Plating 1.31 mil
Dielectric 1080 RC64% 3.75 2.96 mil
2 GND 1
Dielectric Core 0.1MM 1/1 4.13 3.94 mil
3 Signal 1
Dielectric
7628 RC47%
2116 RC58%
4.2
3.91
12.88 mil
4 Power 1
Dielectric Core 0.3MM 1/1 4.47 11.81 mil
5 Power 1
Table continues on the next page...
NXP Semiconductors
i.MX 8M Plus layout/routing recommendations
i.MX 8M Plus Hardware Developer’s Guide, Rev. 0, 03/2021
User's Guide 18 / 50

Table 18. 8MPLUS-BB Board stack up information (continued)
Layer Description Copper (Oz.) Generic Er Dielectric thickness (mil)
Dielectric
2116 RC58%
7628 RC47%
3.91
4.2
12.7 mil
6 Signal 1
Dielectric Core 0.1MM 1/1 4.13 3.94 mil
7 GND 1
Dielectric 1080 RC64% 3.75 2.96 mil
8 Signal 0.5+Plating 1.31 mil
Finished: 62.992(+6.299/-6.299) mil 1.6(+0.16/-0.16) MM
Designed: 61.01 mil 1.55 MM
Material: TU768
3.4 DDR design recommendations
3.4.1 DDR connection information
The i.MX 8M Plus processor can be used with LPDDR4 or DDR4 memory. Since these memory types have different I/O signals,
there are 38 generically-named functional balls, depending on the type of memory used. See Table 19 for the connectivity of
these generic balls for LPDDR4 and DDR4. The schematic symbol created by NXP already replaced these generic names with
DDR function.
Table 19. LPDDR4/DDR4 connectivity
Ball name Ball # LPDDR4 function DDR4 function
DRAM_AC00 J6 CKE0_A CKE0
DRAM_AC01 G5 CKE1_A CKE1
DRAM_AC02 N6 CS0_A CS0_n
DRAM_AC03 J4 CS1_A C0
DRAM_AC04 M1 CK_t_A BG0
DRAM_AC05 M2 CK_c_A BG1
DRAM_AC06 G4 - ACT_n
DRAM_AC07 J5 - A9
DRAM_AC08 L6 CA0_A A12
Table continues on the next page...
NXP Semiconductors
i.MX 8M Plus layout/routing recommendations
i.MX 8M Plus Hardware Developer’s Guide, Rev. 0, 03/2021
User's Guide 19 / 50

Table 19. LPDDR4/DDR4 connectivity (continued)
Ball name Ball # LPDDR4 function DDR4 function
DRAM_AC09 L4 CA1_A A11
DRAM_AC10 E4 CA2_A A7
DRAM_AC11 D4 CA3_A A8
DRAM_AC12 N4 CA4_A A6
DRAM_AC13 N5 CA5_A A5
DRAM_AC14 L5 - A4
DRAM_AC15 R5 - A3
DRAM_AC16 N1 - CK_t_A
DRAM_AC17 N2 - CK_c_A
DRAM_AC19 P2 MTEST MTEST
DRAM_AC20 AA4 CKE0_B CK_t_B
DRAM_AC21 AA5 CKE1_B CK_c_B
DRAM_AC22 AA6 CS1_B -
DRAM_AC23 U4 CS0_B -
DRAM_AC24 V2 CK_t_B A2
DRAM_AC25 V1 CK_c_B A1
DRAM_AC26 P1 - BA1
DRAM_AC27 R4 - PARITY
DRAM_AC28 W4 CA0_B A13
DRAM_AC29 W5 CA1_B BA0
DRAM_AC30 AE4 CA2_B A10 / AP
DRAM_AC31 AF4 CA3_B A0
DRAM_AC32 U5 CA4_B C2
DRAM_AC33 U6 CA5_B CAS_n / A15
DRAM_AC34 U1 - WE_n / A14
Table continues on the next page...
NXP Semiconductors
i.MX 8M Plus layout/routing recommendations
i.MX 8M Plus Hardware Developer’s Guide, Rev. 0, 03/2021
User's Guide 20 / 50