NXP Semiconductors UM11596 User manual

UM11596
PTN3944 linear equalizer application board user manual
Rev. 1 — 14 July 2021 User manual
Document information
Information Content
Keywords PTN3944, PCIe, linear redriver
Abstract UM11596 demonstrates application board capability, interfacing an PCIe
device with a host computer on a x16 slot. The application board is intended
for use as an evaluation board, customer demonstration tool, and a reference
design.

NXP Semiconductors UM11596
PTN3944 linear equalizer application board user manual
Rev Date Description
1 20210714 Initial release
Revision history
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User manual Rev. 1 — 14 July 2021
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NXP Semiconductors UM11596
PTN3944 linear equalizer application board user manual
Important notice
NXP provides the enclosed product(s) under the following conditions:
This evaluation kit is intended for use of ENGINEERING DEVELOPMENT OR
EVALUATION PURPOSES ONLY. It is provided as a sample IC pre-soldered to a
printed circuit board to make it easier to access inputs, outputs, and supply terminals.
This evaluation board may be used with any development system or other source of
I/O signals by simply connecting it to the host MCU or computer board via off-the-
shelf cables. This evaluation board is not a Reference Design and is not intended to
represent a final design recommendation for any particular application. Final device in
an application will be heavily dependent on proper printed circuit board layout and heat
sinking design as well as attention to supply filtering, transient suppression, and I/O
signal quality.
The goods provided may not be complete in terms of required design, marketing, and
or manufacturing related protective considerations, including product safety measures
typically found in the end product incorporating the goods. Due to the open construction
of the product, it is the user's responsibility to take any and all appropriate precautions
with regard to electrostatic discharge. In order to minimize risks associated with the
customers applications, adequate design and operating safeguards must be provided
by the customer to minimize inherent or procedural hazards. For any safety concerns,
contact NXP sales and technical support services.
UM11596 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2021. All rights reserved.
User manual Rev. 1 — 14 July 2021
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NXP Semiconductors UM11596
PTN3944 linear equalizer application board user manual
1 Introduction
The PTN3944 is a high-performance, multi-channel, linear equalizer optimized for PCIe
4.0, UPI, and similar high-speed interfaces. Using multiple components of the PTN3944
supports redriving PCIe signals on x1, x2, x4, x8, or x16 devices installed in a PCIe slot.
This document details how to properly connect the evaluation board in a system in order
to interface a chipset and a PCIe device. The document also illustrates; the Graphical
User Interface (GUI) to configure the equalizer settings of transmitters and receivers;
LPCUSBSIO module operation; and configuration with the PTN3944 application board.
2 PTN3944 PCIe Add-In-Card
The PTN3944 PCIe Add-In-Card (AIC) is designed for use in an available PCIe x16 slot
on a PC or server computer. In addition, using the CEM connector on the top, a PCIe
device can be attached. On the front side of the AIC, there are four PTN3944 that redrive
PCIe signals from motherboard side (from CPU/chipset) to the PCIe device. On the
back side of the AIC, another 4 PTN3944 redrive PCIe signals from a PCIe device to the
motherboard side (to CPU/chipset). The PTN3944 equalizer, output swing level, or flat
gain settings can be configured through either an I2C bus, or using the onboard pull-up/
down DIP switches.
The AIC power is supplied from either gold finger 3.3 V, or from an external 5.0 V power
supply. Each redriver consumes up to 250 mA of current at 1.8 V. With all 8 components
of the PTN3944 active at the same time, the AIC consumes up to 2 A of current at 1.8 V.
NXP recommends using an external 5.0 V, 1 A power supply instead of using power
from the PCIe gold finger. An onboard DC-to-DC power converter converts 5.0 V input to
1.8 V.
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User manual Rev. 1 — 14 July 2021
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NXP Semiconductors UM11596
PTN3944 linear equalizer application board user manual
2.1 Block diagram
aaa-042292
TX_OUT[0:3]
RX_OUT[0:3]
U1 x4x4
x4x4
x4x4
TX_IN[0:3]
RX_IN[0:3]
TX_OUT[4:7]
U2
U5
RX_OUT[4:7] x4x4 RX_IN[4:7]
U6
TX_IN[4:7]
x4x4 TX_OUT[8:11]
U3
RX_OUT[8:11] x4x4 RX_IN[8:11]
U7
TX_IN[8:11]
x4x4 TX_OUT[12:15] U4
RX_OUT[12:15] x4x4 RX_IN[12:15]
U11
PCA9540
U10
REG1117-3.3
I2C
J5
U8
TX_IN[12:15]
J13
J17
U9
TPS62827
5 V
1.8 V
J12J11
5 V 3.3 V
3.3 V
3.3 V
J16
Figure 1. Block diagram
2.2 PCB photographs
Figure 2. PTN3944 PCIe add-in-card front side
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User manual Rev. 1 — 14 July 2021
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NXP Semiconductors UM11596
PTN3944 linear equalizer application board user manual
Figure 3. PTN3944 PCIe add-in-card back side
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User manual Rev. 1 — 14 July 2021
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NXP Semiconductors UM11596
PTN3944 linear equalizer application board user manual
2.3 PTN3944 PCIe Add-In-Card schematics
2.3.1 Front side redrivers
aaa-042295
C1
0.22 µF
1
2
C2
0.22 µF
C9
0.22 µF C10
0.22 µF
C11
0.22 µF C12
0.22 µF
C13
0.22 µF C14
0.22 µF
C15
0.22 µF C16
0.22 µF
C3
0.22 µF
6
33
32
28
27
25
24
20
19
18
17
22
23
30
36
7
C4
0.22 µF
C5
0.22 µF
9
10
C6
0.22 µF
C7
0.22 µF
14
15
C8
0.22 µF 34
35
NC1
NC2
13
16
29
3
11
21
VDD
VCCA
VCCB
VCCC
VCCD
12
5
4
T1_TEST1
TX_IN3N
TX_IN3P
TX_IN2N
TX_IN2P
TX_IN1N
TX_IN1P
TX_IN0N
TX_IN0P
IN3N
IN3P
IN2N
IN2P
IN1N
IN1P
IN0N
IN0P
T1_OUT3N
GND
I2C Address
010-0011 (0x23)
GND
VDD1V8
FG1_T1
FG2_T1
SCL1
SDA1
FG1_T1
FG2_T1
SCL1
SDA1
SCL
SDA
T1_OUT3P
T1_OUT2N
TX_IN0P
TX_IN0N
TX_IN1P
TX_IN1N
TX_IN2P
TX_IN2N
TX_IN3P
TX_IN3N
TX_OUT0P
TX_OUT0N
TX_OUT1P
TX_OUT1N
TX_OUT2P
TX_OUT2N
TX_OUT3P
TX_OUT3N
T1_OUT2P
T1_OUT1N
T1_OUT1P
T1_OUT0N
TX_OUT0P
OUT3N
OUT3P
ADDR3
ADDR4
ADDR2
ADDR1
FG2
FG1
OUT2N
OUT2P
OUT1N
OUT1P
OUT0N
OUT0P
CTL1_T1
CTL2_T1
CTL3_T1
T1_TEST1
PTNVCC1
CTL1_T1
CTL2_T1
CTL3_T1
TEST1
LCTL1
LCTL2
LCTL3
8
26
GND6 GND5 GND4
GND3 GND2 GND1
TEST2
GND
GND
PESD3V3R1BSFD1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
39 38 37 31404142
U1
PTN3944
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
Figure 4. Front side U1 redrivers schematic
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NXP Semiconductors UM11596
PTN3944 linear equalizer application board user manual
aaa-042296
C22
0.22 µF
1
2
C23
0.22 µF
C30
0.22 µF C31
0.22 µF
C32
0.22 µF C33
0.22 µF
C34
0.22 µF C35
0.22 µF
C36
0.22 µF
R3
56 kΩ
C37
0.22 µF
C24
0.22 µF
6
33
32
28
27
25
24
20
19
18
17
22
23
30
36
7
C25
0.22 µF
C26
0.22 µF
9
10
C27
0.22 µF
C28
0.22 µF
14
15
C29
0.22 µF 34
35
NC1
NC2
13
16
29
3
11
21
VDD
VCCA
VCCB
VCCC
VCCD
12
5
4
T2_TEST1
TX_IN7N
TX_IN7P
TX_IN6N
TX_IN6P
TX_IN5N
TX_IN5P
TX_IN4N
TX_IN4P
IN3N
IN3P
IN2N
IN2P
IN1N
IN1P
IN0N
IN0P
TX_OUT7N
GND
I2C Address
010-0010 (0x22)
GND
VDD1V8
FG1_T2
FG2_T2
SCL1
SDA1
FG1_T2
FG2_T2
SCL1
SDA1
SCL
SDA
TX_OUT7P
TX_OUT6N
TX_IN4P
TX_IN4N
TX_IN5P
TX_IN5N
TX_IN6P
TX_IN6N
TX_IN7P
TX_IN7N
TX_OUT4P
TX_OUT4N
TX_OUT5P
TX_OUT5N
TX_OUT6P
TX_OUT6N
TX_OUT7P
TX_OUT7N
TX_OUT6P
TX_OUT5N
TX_OUT5P
TX_OUT4N
TX_OUT4P
OUT3N
OUT3P
ADDR3
ADDR4
ADDR2
ADDR1
FG2
FG1
OUT2N
OUT2P
OUT1N
OUT1P
OUT0N
OUT0P
CTL1_T2
CTL2_T2
CTL3_T2
T2_TEST1
PTNVCC1
CTL1_T2
CTL2_T2
CTL3_T2
TEST1
LCTL1
LCTL2
LCTL3
8
26
GND6 GND5 GND4
GND3 GND2 GND1
TEST2
GND
GND
PESD3V3R1BSFD17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
39 38 37 31404142
U2
PTN3944
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
Figure 5. Front side U2 redrivers schematic
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NXP Semiconductors UM11596
PTN3944 linear equalizer application board user manual
aaa-042297
C43
0.22 µF
1
2
C44
0.22 µF
C51
0.22 µF C52
0.22 µF
C53
0.22 µF C54
0.22 µF
C55
0.22 µF C56
0.22 µF
C57
0.22 µF
R7
200 kΩ
C58
0.22 µF
C45
0.22 µF
6
33
32
28
27
25
24
20
19
18
17
22
23
30
36
7
C46
0.22 µF
C47
0.22 µF
9
10
C48
0.22 µF
C49
0.22 µF
14
15
C50
0.22 µF 34
35
NC1
NC2
13
16
29
3
11
21
VDD
VCCA
VCCB
VCCC
VCCD
12
5
4
T3_TEST1
TX_IN11N
TX_IN11P
TX_IN10N
TX_IN10P
TX_IN9N
TX_IN9P
TX_IN8N
TX_IN8P
IN3N
IN3P
IN2N
IN2P
IN1N
IN1P
IN0N
IN0P
TX_OUT11N
GND
I2C Address
010-0001 (0x21)
GND
VDD1V8
FG1_T3
FG2_T3
SCL1
SDA1
FG1_T3
FG2_T3
SCL1
SDA1
SCL
SDA
TX_OUT11P
TX_OUT10N
TX_IN8P
TX_IN8N
TX_IN9P
TX_IN9N
TX_IN10P
TX_IN10N
TX_IN11P
TX_IN11N
TX_OUT8P
TX_OUT8N
TX_OUT9P
TX_OUT9N
TX_OUT10P
TX_OUT10N
TX_OUT11P
TX_OUT11N
TX_OUT10P
TX_OUT9N
TX_OUT9P
TX_OUT8N
TX_OUT8P
OUT3N
OUT3P
ADDR3
ADDR4
ADDR2
ADDR1
FG2
FG1
OUT2N
OUT2P
OUT1N
OUT1P
OUT0N
OUT0P
CTL1_T3
CTL2_T3
CTL3_T3
T3_TEST1
PTNVCC1
CTL1_T3
CTL2_T3
CTL3_T3
TEST1
LCTL1
LCTL2
LCTL3
8
26
GND6 GND5 GND4 GND3 GND2 GND1
TEST2
GND
GND
PESD3V3R1BSFD33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
39 38 37 31404142
U3
PTN3944
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
Figure 6. Front side U3 redrivers schematic
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NXP Semiconductors UM11596
PTN3944 linear equalizer application board user manual
aaa-042298
C64
0.22 µF
1
2
C65
0.22 µF
C72
0.22 µF C73
0.22 µF
C74
0.22 µF C75
0.22 µF
C76
0.22 µF C77
0.22 µF
C78
0.22 µF C79
0.22 µF
C66
0.22 µF
6
33
32
28
27
25
24
20
19
18
17
22
23
30
36
7
C67
0.22 µF
C68
0.22 µF
9
10
C69
0.22 µF
C70
0.22 µF
14
15
C71
0.22 µF 34
35
NC1
NC2
13
16
29
3
11
21
VDD
VCCA
VCCB
VCCC
VCCD
12
5
4
T4_TEST1
TX_IN15N
TX_IN15P
TX_IN14N
TX_IN14P
TX_IN13N
TX_IN13P
TX_IN12N
TX_IN12P
IN3N
IN3P
IN2N
IN2P
IN1N
IN1P
IN0N
IN0P
TX_OUT15N
GND
I2C Address
010-0000 (0x20)
GND
FG1_T4
FG2_T4
SCL1
SDA1
FG1_T4
FG2_T4
SCL1
SDA1
SCL
SDA
TX_OUT15P
TX_OUT14N
TX_IN12P
TX_IN12N
TX_IN13P
TX_IN13N
TX_IN14P
TX_IN14N
TX_IN15P
TX_IN15N
TX_OUT12P
TX_OUT12N
TX_OUT13P
TX_OUT13N
TX_OUT14P
TX_OUT14N
TX_OUT15P
TX_OUT15N
TX_OUT14P
TX_OUT13N
TX_OUT13P
TX_OUT12N
TX_OUT12P
OUT3N
OUT3P
ADDR3
ADDR4
ADDR2
ADDR1
FG2
FG1
OUT2N
OUT2P
OUT1N
OUT1P
OUT0N
OUT0P
CTL1_T4
CTL2_T4
CTL3_T4
T4_TEST1
PTNVCC1
CTL1_T4
CTL2_T4
CTL3_T4
TEST1
LCTL1
LCTL2
LCTL3
8
26
GND6 GND5 GND4
GND3 GND2 GND1
TEST2
GND
GND
PESD3V3R1BSFD49
D50
D51
D52
D53
D54
D55
D56
D57
D58
D59
D60
D61
D62
D63
D64
39 38 37 31404142
GND
U4
PTN3944
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
Figure 7. Front side U4 redrivers schematic
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NXP Semiconductors UM11596
PTN3944 linear equalizer application board user manual
aaa-042299
GND
PTNVCC1VDD1V8
FB1
3 A
25 MΩ C17
0.1 µF
C18
0.1 µF
C19
0.1 µF
C20
0.1 µF
C21
0.1 µF
Figure 8. Schematic - front side
There are four PTN3944 on the front side of the AIC. Each PTN3944 component is
responsible for 4 lanes of transmitters from the motherboard side to PCIe device side.
Each PTN3944 is assigned a unique I2C address. See Table 1.
Designator I2C Address Corresponding PCIe TX Lanes
U1 0x23 CH[0] – PCIe TX[0]
CH[1] – PCIe TX[1]
CH[2] – PCIe TX[2]
CH[3] – PCIe TX[3]
U2 0x22 CH[0] – PCIe TX[4]
CH[1] – PCIe TX[5]
CH[2] – PCIe TX[6]
CH[3] – PCIe TX[7]
U3 0x21 CH[0] – PCIe TX[8]
CH[1] – PCIe TX[9]
CH[2] – PCIe TX[10]
CH[3] – PCIe TX[11]
U4 0x20 CH[0] – PCIe TX[12]
CH[1] – PCIe TX[13]
CH[2] – PCIe TX[14]
CH[3] – PCIe TX[15]
Table 1. Front side redrivers U1 – U4 I2C addresses and corresponding TX lanes
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NXP Semiconductors UM11596
PTN3944 linear equalizer application board user manual
2.3.2 Back side redrivers
aaa-042300
C85
0.22 µF
1
2
C86
0.22 µF
C93
0.22 µF C94
0.22 µF
C95
0.22 µF C96
0.22 µF
C97
0.22 µF C98
0.22 µF
C99
0.22 µF C100
0.22 µF
C87
0.22 µF
6
33
32
28
27
25
24
20
19
18
17
22
23
30
36
7
C88
0.22 µF
C89
0.22 µF
9
10
C90
0.22 µF
C91
0.22 µF
14
15
C92
0.22 µF 34
35
NC1
NC2
13
16
29
3
11
21
VDD
VCCA
VCCB
VCCC
VCCD
12
5
4
B1_TEST1
RX_IN3N
RX_IN3P
RX_IN2N
RX_IN2P
RX_IN1N
RX_IN1P
RX_IN0N
RX_IN0P
IN3N
IN3P
IN2N
IN2P
IN1N
IN1P
IN0N
IN0P
RX_OUT3N
GND
I2C Address
010-1011 (0x2B)
FG1_B1
FG2_B1
SCL2
SDA2
FG1_B1
FG2_B1
SCL2
SDA2
SCL
SDA
RX_OUT3P
RX_OUT2N
RX_IN0P
RX_IN0N
RX_IN1P
RX_IN1N
RX_IN2P
RX_IN2N
RX_IN3P
RX_IN3N
RX_OUT0P
RX_OUT0N
RX_OUT1P
RX_OUT1N
RX_OUT2P
RX_OUT2N
RX_OUT3P
RX_OUT3N
RX_OUT2P
RX_OUT1N
RX_OUT1P
RX_OUT0N
RX_OUT0P
OUT3N
OUT3P
ADDR3
ADDR4
ADDR2
ADDR1
FG2
FG1
OUT2N
OUT2P
OUT1N
OUT1P
OUT0N
OUT0P
CTL1_B1
CTL2_B1
CTL3_B1
B1_TEST1
PTNVCC5
CTL1_B1
CTL2_B1
CTL3_B1
TEST1
LCTL1
LCTL2
LCTL3
8
26
GND6 GND5 GND4
GND3 GND2 GND1
TEST2
GND
GND
PESD3V3R1BSFD65
D66
D67
D68
D69
D70
D71
D72
D73
D74
D75
D76
D77
D78
D79
D80
39 38 37 31404142
VDD1V8
U5
PTN3944
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
Figure 9. Back side U5 redrivers schematic
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NXP Semiconductors UM11596
PTN3944 linear equalizer application board user manual
aaa-042301
C106
0.22 µF
1
2
C107
0.22 µF
C114
0.22 µF C115
0.22 µF
C116
0.22 µF C117
0.22 µF
C118
0.22 µF C119
0.22 µF
C120
0.22 µF C121
0.22 µF
C108
0.22 µF
6
33
32
28
27
25
24
20
19
18
17
22
23
30
36
7
C109
0.22 µF
C110
0.22 µF
9
10
C111
0.22 µF
C112
0.22 µF
14
15
C113
0.22 µF 34
35
NC1
NC2
13
16
29
3
11
21
VDD
VCCA
VCCB
VCCC
VCCD
12
5
4
B2_TEST1
RX_IN7N
RX_IN7P
RX_IN6N
RX_IN6P
RX_IN5N
RX_IN5P
RX_IN4N
RX_IN4P
IN3N
IN3P
IN2N
IN2P
IN1N
IN1P
IN0N
IN0P
RX_OUT7N
GND
I2C Address
010-1010 (0x2A)
FG1_B2
FG2_B2
SCL2
SDA2
FG1_B2
FG2_B2
SCL2
SDA2
SCL
SDA
RX_OUT7P
RX_OUT6N
RX_IN4P
RX_IN4N
RX_IN5P
RX_IN5N
RX_IN6P
RX_IN6N
RX_IN7P
RX_IN7N
RX_OUT4P
RX_OUT4N
RX_OUT5P
RX_OUT5N
RX_OUT6P
RX_OUT6N
RX_OUT7P
RX_OUT7N
RX_OUT6P
RX_OUT5N
RX_OUT5P
RX_OUT4N
RX_OUT4P
OUT3N
OUT3P
ADDR3
ADDR4
ADDR2
ADDR1
FG2
FG1
OUT2N
OUT2P
OUT1N
OUT1P
OUT0N
OUT0P
CTL1_B2
CTL2_B2
CTL3_B2
B2_TEST1
PTNVCC5
CTL1_B2
CTL2_B2
CTL3_B2
TEST1
LCTL1
LCTL2
LCTL3
8
26
GND6 GND5 GND4
GND3 GND2 GND1
TEST2
GND
GND
PESD3V3R1BSFD81
D82
D83
D84
D85
D86
D87
D88
D89
D90
D91
D92
D93
D94
D95
D96
39 38 37 31404142
VDD1V8
U6
PTN3944
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
R11
56 kΩ
Figure 10. Back side U6 redrivers schematic
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NXP Semiconductors UM11596
PTN3944 linear equalizer application board user manual
aaa-042302
C127
0.22 µF
1
2
C128
0.22 µF
C135
0.22 µF C136
0.22 µF
C137
0.22 µF C138
0.22 µF
C139
0.22 µF C140
0.22 µF
C141
0.22 µF C142
0.22 µF
C129
0.22 µF
6
33
32
28
27
25
24
20
19
18
17
22
23
30
36
7
C130
0.22 µF
C131
0.22 µF
9
10
C132
0.22 µF
C133
0.22 µF
14
15
C134
0.22 µF 34
35
NC1
NC2
13
16
29
3
11
21
VDD
VCCA
VCCB
VCCC
VCCD
12
5
4
B3_TEST1
RX_IN11N
RX_IN11P
RX_IN10N
RX_IN10P
RX_IN9N
RX_IN9P
RX_IN8N
RX_IN8P
IN3N
IN3P
IN2N
IN2P
IN1N
IN1P
IN0N
IN0P
RX_OUT11N
GND
I2C Address
010-1001 (0x29)
FG1_B3
FG2_B3
SCL2
SDA2
FG1_B3
FG2_B3
SCL2
SDA2
SCL
SDA
RX_OUT11P
RX_OUT10N
RX_IN8P
RX_IN8N
RX_IN9P
RX_IN9N
RX_IN10P
RX_IN10N
RX_IN11P
RX_IN11N
RX_OUT8P
RX_OUT8N
RX_OUT9P
RX_OUT9N
RX_OUT10P
RX_OUT10N
RX_OUT11P
RX_OUT11N
RX_OUT10P
RX_OUT9N
RX_OUT9P
RX_OUT8N
RX_OUT8P
OUT3N
OUT3P
ADDR3
ADDR4
ADDR2
ADDR1
FG2
FG1
OUT2N
OUT2P
OUT1N
OUT1P
OUT0N
OUT0P
CTL1_B3
CTL2_B3
CTL3_B3
B3_TEST1
PTNVCC5
CTL1_B3
CTL2_B3
CTL3_B3
TEST1
LCTL1
LCTL2
LCTL3
8
26
GND6 GND5 GND4
GND3 GND2 GND1
TEST2
GND
GND
PESD3V3R1BSFD97
D98
D99
D100
D101
D102
D103
D104
D105
D106
D107
D108
D109
D110
D111
D112
39 38 37 31404142
VDD1V8
U7
PTN3944
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
R15
200 kΩ
Figure 11. Back side U7 redrivers schematic
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NXP Semiconductors UM11596
PTN3944 linear equalizer application board user manual
aaa-042303
C148
0.22 µF
1
2
C149
0.22 µF
C156
0.22 µF C157
0.22 µF
C158
0.22 µF C159
0.22 µF
C160
0.22 µF C161
0.22 µF
C162
0.22 µF C163
0.22 µF
C150
0.22 µF
6
33
32
28
27
25
24
20
19
18
17
22
23
30
36
7
C151
0.22 µF
C152
0.22 µF
9
10
C153
0.22 µF
C154
0.22 µF
14
15
C155
0.22 µF 34
35
NC1
NC2
13
16
29
3
11
21
VDD
VCCA
VCCB
VCCC
VCCD
12
5
4
B4_TEST1
RX_IN15N
RX_IN15P
RX_IN14N
RX_IN14P
RX_IN13N
RX_IN13P
RX_IN12N
RX_IN12P
IN3N
IN3P
IN2N
IN2P
IN1N
IN1P
IN0N
IN0P
RX_OUT15N
GND
I2C Address
010-1000 (0x28)
FG1_B4
FG2_B4
SCL2
SDA2
FG1_B4
FG2_B4
SCL2
SDA2
SCL
SDA
RX_OUT15P
RX_OUT14N
RX_IN12P
RX_IN12N
RX_IN13P
RX_IN13N
RX_IN14P
RX_IN14N
RX_IN15P
RX_IN15N
RX_OUT12P
RX_OUT12N
RX_OUT13P
RX_OUT13N
RX_OUT14P
RX_OUT14N
RX_OUT15P
RX_OUT15N
RX_OUT14P
RX_OUT13N
RX_OUT13P
RX_OUT12N
RX_OUT12P
OUT3N
OUT3P
ADDR3
ADDR4
ADDR2
ADDR1
FG2
FG1
OUT2N
OUT2P
OUT1N
OUT1P
OUT0N
OUT0P
CTL1_B4
CTL2_B4
CTL3_B4
B4_TEST1
PTNVCC5
CTL1_B4
CTL2_B4
CTL3_B4
TEST1
LCTL1
LCTL2
LCTL3
8
26
GND6 GND5 GND4
GND3 GND2 GND1
TEST2
GND
GND
PESD3V3R1BSFD113
D114
D115
D116
D117
D118
D119
D120
D121
D122
D123
D124
D125
D126
D127
D128
39 38 37 31404142
GND
U8
PTN3944
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
PESD3V3R1BSF
VDD1V8
Figure 12. Back side U8 redrivers schematic
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NXP Semiconductors UM11596
PTN3944 linear equalizer application board user manual
aaa-042304
GND
PTNVCC5VDD1V8
FB5
3 A
25 MΩ C101
0.1 µF
C102
0.1 µF
C103
0.1 µF
C104
0.1 µF
C105
0.1 µF
Figure 13. Schematic - back side
There are four PTN3944 on the back side of the AIC. Each PTN3944 component is
responsible for 4 lanes of receivers from PCIe device side to the motherboard side. Each
PTN3944 component is assigned a unique I2C address. See Table 2.
Designator I2C Address Corresponding PCIe TX Lanes
U5 0x2B CH[0] – PCIe RX[0]
CH[1] – PCIe RX[1]
CH[2] – PCIe RX[2]
CH[3] – PCIe RX[3]
U6 0x2A CH[0] – PCIe RX[4]
CH[1] – PCIe RX[5]
CH[2] – PCIe RX[6]
CH[3] – PCIe RX[7]
U7 0x29 CH[0] – PCIe RX[8]
CH[1] – PCIe RX[9]
CH[2] – PCIe RX[10]
CH[3] – PCIe RX[11]
U8 0x28 CH[0] – PCIe RX[12]
CH[1] – PCIe RX[13]
CH[2] – PCIe RX[14]
CH[3] – PCIe RX[15]
Table 2. Back side redrivers U5 – U8 I2C addresses and corresponding TX lanes
2.3.3 Front side redriver control switches
aaa-042305
GND
R40
VDD1V8
10
9
9
-
+
1
T1_TEST1
CTL1_T1
CTL2_T1
CTL3_T1
T2_TEST1
CTL1_T2
CTL2_T2
CTL3_T2
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
10
10 kΩ R41
K1
KAT1108E
10 kΩ
R42
10 kΩ R43
10 kΩ
R44
10 kΩ R45
10 kΩ
R46
10 kΩ R47
10 kΩ
Figure 14. Front side K1 control switch schematic
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NXP Semiconductors UM11596
PTN3944 linear equalizer application board user manual
aaa-042306
GND
R48
VDD1V8
10
9
9
-
+
1
T3_TEST1
CTL1_T3
CTL2_T3
CTL3_T3
T4_TEST1
CTL1_T4
CTL2_T4
CTL3_T4
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
10
10 kΩ R49
K2
KAT1108E
10 kΩ
R50
10 kΩ R51
10 kΩ
R52
10 kΩ R53
10 kΩ
R54
10 kΩ R55
10 kΩ
Figure 15. Front side K2 control switch schematic
aaa-042307
GND
R76
VDD1V8
10
9
9
-
+
1
FG1_T1
FG2_T1
FG1_T2
FG2_T2
FG1_T3
FG2_T3
FG1_T4
FG2_T4
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
10
10 kΩ R77
K5
KAT1108E
10 kΩ
R78
10 kΩ R79
10 kΩ
R80
10 kΩ R81
10 kΩ
R82
10 kΩ R83
10 kΩ
Figure 16. Front side K5 control switch schematic
Switch Switch Position Description
1 U1 (Top/Front) Test Pin, Connect To GND
2 U1 (Top/Front) LCTL1, Peaking Gain Setting
3 U1 (Top/Front) LCTL2, Peaking Gain Setting
4 U1 (Top/Front) LCTL3, Output Linear Swing Setting
5 U2 (Top/Front) Test Pin, Connect To GND
6 U2 (Top/Front) LCTL1, Peaking Gain Setting
7 U2 (Top/Front) LCTL2, Peaking Gain Setting
K1
8 U2 (Top/Front) LCTL3, Output Linear Swing Setting
Table 3. Front side redriver K1, K2, and K5 control switch positions and
descriptions
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NXP Semiconductors UM11596
PTN3944 linear equalizer application board user manual
Switch Switch Position Description
1 U3 (Top/Front) Test Pin, Connect To GND
2 U3 (Top/Front) LCTL1, Peaking Gain Setting
3 U3 (Top/Front) LCTL2, Peaking Gain Setting
4 U3 (Top/Front) LCTL3, Output Linear Swing Setting
5 U4 (Top/Front) Test Pin, Connect To GND
6 U4 (Top/Front) LCTL1, Peaking Gain Setting
7 U4 (Top/Front) LCTL2, Peaking Gain Setting
K2
8 U4 (Top/Front) LCTL3, Output Linear Swing Setting
1 U1 (Top/Front) FG1, Flat Gain Control Setting
2 U1 (Top/Front) FG2, Flat Gain Control Setting
3 U2 (Top/Front) FG1, Flat Gain Control Setting
4 U2 (Top/Front) FG2, Flat Gain Control Setting
5 U3 (Top/Front) FG1, Flat Gain Control Setting
6 U3 (Top/Front) FG2, Flat Gain Control Setting
7 U4 (Top/Front) FG1, Flat Gain Control Setting
K5
8 U4 (Top/Front) FG2, Flat Gain Control Setting
Table 3. Front side redriver K1, K2, and K5 control switch positions and
descriptions...continued
2.3.4 Back side redriver control switches
aaa-042308
GND
R56
VDD1V8
10
9
9
-
+
1
B1_TEST1
CTL1_B1
CTL2_B1
CTL3_B1
B2_TEST1
CTL1_B2
CTL2_B2
CTL3_B2
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
10
10 kΩ R57
K3
KAT1108E
10 kΩ
R58
10 kΩ R59
10 kΩ
R60
10 kΩ R61
10 kΩ
R62
10 kΩ R63
10 kΩ
Figure 17. Back side K3 control switch schematic
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NXP Semiconductors UM11596
PTN3944 linear equalizer application board user manual
aaa-042309
GND
R64
VDD1V8
10
9
9
-
+
1
B3_TEST1
CTL1_B3
CTL2_B3
CTL3_B3
B4_TEST1
CTL1_B4
CTL2_B4
CTL3_B4
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
10
10 kΩ R65
K4
KAT1108E
10 kΩ
R66
10 kΩ R67
10 kΩ
R68
10 kΩ R69
10 kΩ
R70
10 kΩ R71
10 kΩ
Figure 18. Back side K4 control switch schematic
aaa-042310
GND
R84
VDD1V8
10
9
9
-
+
1
FG1_B1
FG2_B1
FG1_B2
FG2_B2
FG1_B3
FG2_B3
FG1_B4
FG2_B4
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
10
10 kΩ R85
K6
KAT1108E
10 kΩ
R86
10 kΩ R87
10 kΩ
R88
10 kΩ R89
10 kΩ
R90
10 kΩ R91
10 kΩ
Figure 19. Back side K6 control switch schematic
Switch Switch Position Description
1 U5 (Bottom/Back) Test Pin, Connect To GND
2 U5 (Bottom/Back) LCTL1, Peaking Gain Setting
3 U5 (Bottom/Back) LCTL2, Peaking Gain Setting
4 U5 (Bottom/Back) LCTL3, Output Linear Swing Setting
5 U6 (Bottom/Back) Test Pin, Connect To GND
6 U6 (Bottom/Back) LCTL1, Peaking Gain Setting
7 U6 (Bottom/Back) LCTL2, Peaking Gain Setting
K3
8 U6 (Bottom/Back) LCTL3, Output Linear Swing Setting
Table 4. Back side redrivers K3, K4, and K6 control switch positions and
descriptions
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NXP Semiconductors UM11596
PTN3944 linear equalizer application board user manual
Switch Switch Position Description
1 U7 (Bottom/Back) Test Pin, Connect To GND
2 U7 (Bottom/Back) LCTL1, Peaking Gain Setting
3 U7 (Bottom/Back) LCTL2, Peaking Gain Setting
4 U7 (Bottom/Back) LCTL3, Output Linear Swing Setting
5 U8 (Bottom/Back) Test Pin, Connect To GND
6 U8 (Bottom/Back) LCTL1, Peaking Gain Setting
7 U8 (Bottom/Back) LCTL2, Peaking Gain Setting
K4
8 U8 (Bottom/Back) LCTL3, Output Linear Swing Setting
1 U5 (Bottom/Back) FG1, Flat Gain Control Setting
2 U5 (Bottom/Back) FG2, Flat Gain Control Setting
3 U6 (Bottom/Back) FG1, Flat Gain Control Setting
4 U6 (Bottom/Back) FG2, Flat Gain Control Setting
5 U7 (Bottom/Back) FG1, Flat Gain Control Setting
6 U7 (Bottom/Back) FG2, Flat Gain Control Setting
7 U8 (Bottom/Back) FG1, Flat Gain Control Setting
K6
8 U8 (Bottom/Back) FG2, Flat Gain Control Setting
Table 4. Back side redrivers K3, K4, and K6 control switch positions and
descriptions...continued
Figure 20. Board control locations
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