NXP Semiconductors freescale KV4 Series User manual

KV4x Reference Manual
Supports MKV46, MKV45, MKV44, MKV43, MKV41, MKV40 part
numbers
Document Number: KV4XP100M150RM
Rev 2, 02/2015
Preliminary

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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................61
1.1.1 Purpose...........................................................................................................................................................61
1.1.2 Audience........................................................................................................................................................ 61
1.2 Conventions.................................................................................................................................................................. 61
1.2.1 Numbering systems........................................................................................................................................61
1.2.2 Typographic notation..................................................................................................................................... 62
1.2.3 Special terms..................................................................................................................................................62
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................63
2.2 Module Functional Categories......................................................................................................................................63
2.2.1 ARM® Cortex®-M4 Core Modules..............................................................................................................64
2.2.2 System Modules.............................................................................................................................................65
2.2.3 Memories and Memory Interfaces................................................................................................................. 66
2.2.4 Clocks.............................................................................................................................................................66
2.2.5 Security and Integrity modules...................................................................................................................... 66
2.2.6 Analog modules............................................................................................................................................. 67
2.2.7 Timer modules............................................................................................................................................... 67
2.2.8 Communication interfaces............................................................................................................................. 69
2.2.9 Human-machine interfaces............................................................................................................................ 69
2.3 Orderable part numbers and features............................................................................................................................ 70
Chapter 3
Core overview
3.1 ARM Cortex-M4 Core Configuration.......................................................................................................................... 73
3.1.1 Buses, interconnects, and interfaces.............................................................................................................. 74
3.1.2 System Tick Timer.........................................................................................................................................74
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3.1.3 Debug facilities.............................................................................................................................................. 74
3.1.4 Core privilege levels...................................................................................................................................... 75
3.2 Nested Vectored Interrupt Controller (NVIC) Configuration...................................................................................... 75
3.2.1 Interrupt priority levels.................................................................................................................................. 75
3.2.2 Non-maskable interrupt..................................................................................................................................75
3.2.3 Interrupt vector assignments ......................................................................................................................... 76
3.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration..........................................................................79
3.3.1 Wake-up sources............................................................................................................................................80
3.4 FPU Configuration........................................................................................................................................................80
3.5 JTAG Controller Configuration....................................................................................................................................81
Chapter 4
Memories and Memory Interfaces
4.1 Flash memory types......................................................................................................................................................83
4.2 Flash Memory Sizes......................................................................................................................................................83
4.3 Flash Security............................................................................................................................................................... 84
4.4 Flash Modes..................................................................................................................................................................84
4.5 Erase All Flash Contents...............................................................................................................................................84
4.6 FTFA_FOPT Register...................................................................................................................................................85
4.7 SRAM sizes.................................................................................................................................................................. 85
4.8 SRAM Arrays............................................................................................................................................................... 86
4.9 SRAM retention in low power modes.......................................................................................................................... 87
4.10 System Register file......................................................................................................................................................87
Chapter 5
Memory Map
5.1 Introduction...................................................................................................................................................................89
5.2 System Memory Map....................................................................................................................................................89
5.3 Peripheral Memory Map...............................................................................................................................................90
5.3.1 Read-after-write sequence and required serialization of memory operations................................................90
5.3.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map.......................................................................................... 91
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Chapter 6
Clock Distribution
6.1 Introduction...................................................................................................................................................................95
6.2 High-level device clocking diagram............................................................................................................................. 95
6.2.1 Clock definitions............................................................................................................................................96
6.3 Internal clocking requirements..................................................................................................................................... 97
6.3.1 Clock divider values after reset......................................................................................................................98
6.3.2 VLPR mode clocking.....................................................................................................................................99
6.4 Clock Gating.................................................................................................................................................................99
6.5 Module clocks...............................................................................................................................................................100
6.5.1 nano edge module clocking............................................................................................................................101
6.5.2 WDOG clocking............................................................................................................................................ 101
6.5.3 Debug trace clock...........................................................................................................................................102
6.5.4 PMC 1-kHz LPO clock..................................................................................................................................102
6.5.5 PORT digital filter clocking...........................................................................................................................102
6.5.6 LPTMR clocking............................................................................................................................................103
6.5.7 FlexCAN clocking......................................................................................................................................... 103
6.5.8 UART clocking..............................................................................................................................................104
6.6 External clocks .............................................................................................................................................................104
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................105
7.2 Clocking Modes............................................................................................................................................................105
7.2.1 Partial Stop.....................................................................................................................................................105
7.2.2 DMA Wakeup................................................................................................................................................106
7.2.3 Compute Operation........................................................................................................................................107
7.2.4 Peripheral Doze..............................................................................................................................................108
7.3 Power modes.................................................................................................................................................................109
7.4 Module Operation in Low Power Modes......................................................................................................................110
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7.5 Power modes shutdown sequencing............................................................................................................................. 113
7.6 Clock Gating.................................................................................................................................................................113
7.7 Flash Program Restrictions...........................................................................................................................................114
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................115
8.2 Flash Security............................................................................................................................................................... 115
8.3 Security Interactions with other Modules.....................................................................................................................116
8.3.1 Security Interactions with Debug...................................................................................................................116
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................117
9.1.1 References......................................................................................................................................................119
9.2 The Debug Port.............................................................................................................................................................119
9.2.1 JTAG-to-SWD change sequence................................................................................................................... 119
9.3 Debug Port Pin Descriptions.........................................................................................................................................120
9.4 JTAG status and control registers.................................................................................................................................120
9.4.1 MDM-AP Control Register............................................................................................................................121
9.4.2 MDM-AP Status Register.............................................................................................................................. 123
9.5 Debug Resets................................................................................................................................................................ 124
9.6 AHB-AP........................................................................................................................................................................124
9.7 ITM............................................................................................................................................................................... 125
9.8 TPIU..............................................................................................................................................................................125
9.9 DWT............................................................................................................................................................................. 126
9.10 Debug in Low Power Modes........................................................................................................................................ 126
9.10.1 Debug Module State in Low Power Modes...................................................................................................127
9.11 Debug & Security......................................................................................................................................................... 127
Chapter 10
Reset and Boot
10.1 Introduction...................................................................................................................................................................129
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10.2 Reset..............................................................................................................................................................................129
10.2.1 Power-on reset (POR).................................................................................................................................... 130
10.2.2 System resets..................................................................................................................................................130
10.2.2.1 External pin reset (PIN)............................................................................................................. 130
10.2.2.2 Low-voltage detect (LVD) reset................................................................................................ 131
10.2.2.3 Computer operating properly (COP) watchdog reset................................................................ 132
10.2.2.4 Low leakage wakeup (LLWU) reset..........................................................................................132
10.2.2.5 Multipurpose clock generator loss-of-clock (LOC) reset.......................................................... 132
10.2.2.6 Software reset (SW)...................................................................................................................133
10.2.2.7 Lockup reset (LOCKUP)........................................................................................................... 133
10.2.2.8 MDM-AP system reset request..................................................................................................133
10.2.3 Debug resets...................................................................................................................................................133
10.2.3.1 JTAG reset................................................................................................................................. 133
10.2.3.2 nTRST reset............................................................................................................................... 134
10.2.3.3 Resetting the Debug subsystem................................................................................................. 134
10.3 Boot...............................................................................................................................................................................135
10.3.1 Boot sources...................................................................................................................................................135
10.3.2 FOPT boot options.........................................................................................................................................135
10.3.3 Boot sequence................................................................................................................................................ 136
Chapter 11
Signal Multiplexing
11.1 Introduction...................................................................................................................................................................139
11.2 Port control and interrupt module features................................................................................................................... 139
11.3 Clock gating..................................................................................................................................................................140
11.4 Signal multiplexing constraints.................................................................................................................................... 141
11.5 KV4x Signal Multiplexing and Pin Assignments.........................................................................................................141
11.6 Pinout diagrams............................................................................................................................................................ 146
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Chapter 12
Port control and interrupts (PORT)
12.1 Introduction...................................................................................................................................................................151
12.2 Overview.......................................................................................................................................................................151
12.2.1 Features.......................................................................................................................................................... 151
12.2.2 Modes of operation........................................................................................................................................ 152
12.2.2.1 Run mode................................................................................................................................... 152
12.2.2.2 Wait mode..................................................................................................................................152
12.2.2.3 Stop mode.................................................................................................................................. 152
12.2.2.4 Debug mode............................................................................................................................... 152
12.3 External signal description............................................................................................................................................153
12.4 Detailed signal description............................................................................................................................................153
12.5 Memory map and register definition.............................................................................................................................153
12.5.1 Pin Control Register n (PORTx_PCRn).........................................................................................................160
12.5.2 Global Pin Control Low Register (PORTx_GPCLR)....................................................................................163
12.5.3 Global Pin Control High Register (PORTx_GPCHR)...................................................................................163
12.5.4 Interrupt Status Flag Register (PORTx_ISFR).............................................................................................. 164
12.5.5 Digital Filter Enable Register (PORTx_DFER).............................................................................................164
12.5.6 Digital Filter Clock Register (PORTx_DFCR)..............................................................................................165
12.5.7 Digital Filter Width Register (PORTx_DFWR)............................................................................................ 165
12.6 Functional description...................................................................................................................................................166
12.6.1 Pin control......................................................................................................................................................166
12.6.2 Global pin control.......................................................................................................................................... 167
12.6.3 External interrupts..........................................................................................................................................167
12.6.4 Digital filter....................................................................................................................................................168
Chapter 13
System Integration Module (SIM)
13.1 Introduction...................................................................................................................................................................171
13.1.1 Features.......................................................................................................................................................... 171
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13.2 Memory map and register definition.............................................................................................................................172
13.2.1 System Options Register 1 (SIM_SOPT1).................................................................................................... 173
13.2.2 System Options Register 2 (SIM_SOPT2).................................................................................................... 174
13.2.3 System Options Register 4 (SIM_SOPT4).................................................................................................... 176
13.2.4 System Options Register 5 (SIM_SOPT5).................................................................................................... 179
13.2.5 System Options Register 7 (SIM_SOPT7).................................................................................................... 180
13.2.6 System Options Register 8 (SIM_SOPT8).................................................................................................... 182
13.2.7 System Options Register 9 (SIM_SOPT9).................................................................................................... 185
13.2.8 System Device Identification Register (SIM_SDID).....................................................................................186
13.2.9 System Clock Gating Control Register 4 (SIM_SCGC4)..............................................................................188
13.2.10 System Clock Gating Control Register 5 (SIM_SCGC5)..............................................................................190
13.2.11 System Clock Gating Control Register 6 (SIM_SCGC6)..............................................................................192
13.2.12 System Clock Gating Control Register 7 (SIM_SCGC7)..............................................................................194
13.2.13 System Clock Divider Register 1 (SIM_CLKDIV1).....................................................................................194
13.2.14 Flash Configuration Register 1 (SIM_FCFG1)............................................................................................. 197
13.2.15 Flash Configuration Register 2 (SIM_FCFG2)............................................................................................. 198
13.2.16 Unique Identification Register High (SIM_UIDH)....................................................................................... 199
13.2.17 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................199
13.2.18 Unique Identification Register Mid Low (SIM_UIDML)............................................................................. 200
13.2.19 Unique Identification Register Low (SIM_UIDL)........................................................................................ 200
13.2.20 System Clock Divider Register 4 (SIM_CLKDIV4).....................................................................................201
13.2.21 Miscellaneous Control Register (SIM_MISCTRL).......................................................................................202
13.2.22 Miscellaneous Control Register 2 (SIM_MISCTRL2)..................................................................................203
13.2.23 WDOG Control Register (SIM_WDOGC)....................................................................................................206
13.2.24 Power Control Register (SIM_PWRC)..........................................................................................................207
13.2.25 ADC Channel 6/7 Mux Control Register (SIM_ADCOPT)..........................................................................209
13.3 Functional description...................................................................................................................................................211
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Chapter 14
Kinetis Flashloader
14.1 Introduction...................................................................................................................................................................213
14.2 Functional Description..................................................................................................................................................214
14.2.1 Memory Maps................................................................................................................................................214
14.2.2 Start-up Process..............................................................................................................................................215
14.2.3 Clock Configuration.......................................................................................................................................217
14.2.4 Flashloader Protocol...................................................................................................................................... 217
14.2.4.1 Command with no data phase.................................................................................................... 217
14.2.4.2 Command with incoming data phase.........................................................................................218
14.2.4.3 Command with outgoing data phase..........................................................................................220
14.2.5 Flashloader Packet Types...............................................................................................................................222
14.2.5.1 Ping packet.................................................................................................................................222
14.2.5.2 Ping Response Packet................................................................................................................ 223
14.2.5.3 Framing Packet.......................................................................................................................... 223
14.2.5.4 Command packet........................................................................................................................225
14.2.5.5 Data packet.................................................................................................................................227
14.2.5.6 Response packet.........................................................................................................................227
14.2.6 Flashloader Command API............................................................................................................................229
14.2.6.1 GetProperty command............................................................................................................... 229
14.2.6.2 SetProperty command................................................................................................................231
14.2.6.3 FlashEraseAll command............................................................................................................ 233
14.2.6.4 FlashEraseRegion command......................................................................................................234
14.2.6.5 FillMemory command................................................................................................................235
14.2.6.6 WriteMemory command............................................................................................................237
14.2.6.7 Read memory command............................................................................................................ 239
14.2.6.8 Execute command......................................................................................................................241
14.2.6.9 Reset command..........................................................................................................................241
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14.3 Peripherals Supported................................................................................................................................................... 242
14.3.1 I2C Peripheral................................................................................................................................................ 242
14.3.2 SPI Peripheral................................................................................................................................................ 244
14.3.3 UART Peripheral........................................................................................................................................... 246
14.3.4 CAN (or FlexCAN) Peripheral...................................................................................................................... 249
14.4 Get/SetProperty Command Properties..........................................................................................................................251
14.4.1 Property Definitions.......................................................................................................................................252
14.4.1.1 CurrentVersion Property............................................................................................................252
14.4.1.2 AvailablePeripherals Property................................................................................................... 252
14.4.1.3 AvailableCommands Property................................................................................................... 253
14.5 Kinetis Flashloader Status Error Codes........................................................................................................................ 253
Chapter 15
Reset Control Module (RCM)
15.1 Introduction...................................................................................................................................................................255
15.2 Reset memory map and register descriptions............................................................................................................... 255
15.2.1 System Reset Status Register 0 (RCM_SRS0).............................................................................................. 256
15.2.2 System Reset Status Register 1 (RCM_SRS1).............................................................................................. 257
15.2.3 Reset Pin Filter Control register (RCM_RPFC)............................................................................................ 259
15.2.4 Reset Pin Filter Width register (RCM_RPFW)............................................................................................. 260
15.2.5 Sticky System Reset Status Register 0 (RCM_SSRS0).................................................................................261
15.2.6 Sticky System Reset Status Register 1 (RCM_SSRS1).................................................................................262
Chapter 16
System Mode Controller (SMC)
16.1 Introduction...................................................................................................................................................................265
16.2 Modes of operation....................................................................................................................................................... 265
16.3 Memory map and register descriptions.........................................................................................................................267
16.3.1 Power Mode Protection register (SMC_PMPROT).......................................................................................268
16.3.2 Power Mode Control register (SMC_PMCTRL)...........................................................................................269
16.3.3 Stop Control Register (SMC_STOPCTRL)...................................................................................................271
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16.3.4 Power Mode Status register (SMC_PMSTAT)............................................................................................. 272
16.4 Functional description...................................................................................................................................................273
16.4.1 Power mode transitions..................................................................................................................................273
16.4.2 Power mode entry/exit sequencing................................................................................................................ 276
16.4.2.1 Stop mode entry sequence..........................................................................................................276
16.4.2.2 Stop mode exit sequence............................................................................................................276
16.4.2.3 Aborted stop mode entry............................................................................................................276
16.4.2.4 Transition to wait modes............................................................................................................277
16.4.2.5 Transition from stop modes to Debug mode..............................................................................277
16.4.3 Run modes......................................................................................................................................................277
16.4.3.1 RUN mode................................................................................................................................. 277
16.4.3.2 Very-Low Power Run (VLPR) mode........................................................................................ 278
16.4.3.3 High Speed Run (HSRUN) mode.............................................................................................. 278
16.4.4 Wait modes.................................................................................................................................................... 279
16.4.4.1 WAIT mode............................................................................................................................... 279
16.4.4.2 Very-Low-Power Wait (VLPW) mode......................................................................................280
16.4.5 Stop modes.....................................................................................................................................................280
16.4.5.1 STOP mode................................................................................................................................281
16.4.5.2 Very-Low-Power Stop (VLPS) mode........................................................................................281
16.4.5.3 Very-Low-Leakage Stop (VLLSx) modes.................................................................................281
16.4.6 Debug in low power modes........................................................................................................................... 282
Chapter 17
Miscellaneous Control Module (MCM)
17.1 Introduction...................................................................................................................................................................285
17.1.1 Features.......................................................................................................................................................... 285
17.2 Memory map/register descriptions............................................................................................................................... 285
17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................286
17.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 286
17.2.3 Control Register (MCM_CR)........................................................................................................................ 287
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17.2.4 Interrupt Status Register (MCM_ISR)...........................................................................................................289
17.2.5 Compute Operation Control Register (MCM_CPO)..................................................................................... 291
17.3 Functional description...................................................................................................................................................292
17.3.1 Interrupts........................................................................................................................................................ 292
17.3.1.1 Non-maskable interrupt..............................................................................................................292
17.3.1.2 Normal interrupt.........................................................................................................................292
17.4 Functional description...................................................................................................................................................293
17.4.1 Interrupts........................................................................................................................................................ 293
17.4.1.1 Determining source of the interrupt...........................................................................................293
Chapter 18
Power Management Controller (PMC)
18.1 Introduction...................................................................................................................................................................295
18.2 Features.........................................................................................................................................................................295
18.3 Low-voltage detect (LVD) system................................................................................................................................295
18.3.1 LVD reset operation.......................................................................................................................................296
18.3.2 LVD interrupt operation.................................................................................................................................296
18.3.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 296
18.4 I/O retention..................................................................................................................................................................297
18.5 Memory map and register descriptions.........................................................................................................................297
18.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1).......................................................... 298
18.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2).......................................................... 299
18.5.3 Regulator Status And Control register (PMC_REGSC)................................................................................300
Chapter 19
Low-Leakage Wakeup Unit (LLWU)
19.1 Chip-specific LLWU information.................................................................................................................................303
19.2 Introduction...................................................................................................................................................................304
19.2.1 Features.......................................................................................................................................................... 304
19.2.2 Modes of operation........................................................................................................................................ 304
19.2.2.1 VLLS modes.............................................................................................................................. 305
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19.2.2.2 Non-low leakage modes.............................................................................................................305
19.2.2.3 Debug mode............................................................................................................................... 305
19.2.3 Block diagram................................................................................................................................................305
19.3 LLWU signal descriptions............................................................................................................................................ 305
19.4 Memory map/register definition................................................................................................................................... 306
19.4.1 LLWU Pin Enable 1 register (LLWU_PE1)..................................................................................................307
19.4.2 LLWU Pin Enable 2 register (LLWU_PE2)..................................................................................................308
19.4.3 LLWU Pin Enable 3 register (LLWU_PE3)..................................................................................................309
19.4.4 LLWU Pin Enable 4 register (LLWU_PE4)..................................................................................................310
19.4.5 LLWU Pin Enable 5 register (LLWU_PE5)..................................................................................................311
19.4.6 LLWU Pin Enable 6 register (LLWU_PE6)..................................................................................................312
19.4.7 LLWU Pin Enable 7 register (LLWU_PE7)..................................................................................................313
19.4.8 LLWU Pin Enable 8 register (LLWU_PE8)..................................................................................................315
19.4.9 LLWU Module Enable register (LLWU_ME).............................................................................................. 316
19.4.10 LLWU Pin Flag 1 register (LLWU_PF1)......................................................................................................317
19.4.11 LLWU Pin Flag 2 register (LLWU_PF2)......................................................................................................319
19.4.12 LLWU Pin Flag 3 register (LLWU_PF3)......................................................................................................321
19.4.13 LLWU Pin Flag 4 register (LLWU_PF4)......................................................................................................322
19.4.14 LLWU Module Flag 5 register (LLWU_MF5)..............................................................................................324
19.4.15 LLWU Pin Filter 1 register (LLWU_FILT1)................................................................................................ 326
19.4.16 LLWU Pin Filter 2 register (LLWU_FILT2)................................................................................................ 327
19.5 Functional description...................................................................................................................................................328
19.5.1 VLLS modes.................................................................................................................................................. 328
19.5.2 Initialization................................................................................................................................................... 328
Chapter 20
Crossbar Switch Lite (AXBS-Lite)
20.1 Crossbar-Light Switch Configuration...........................................................................................................................331
20.1.1 Crossbar Switch Master Assignments............................................................................................................332
20.1.2 Crossbar Switch Slave Assignments..............................................................................................................332
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20.2 Introduction...................................................................................................................................................................332
20.2.1 Features.......................................................................................................................................................... 332
20.3 Memory Map / Register Definition...............................................................................................................................333
20.4 Functional Description..................................................................................................................................................333
20.4.1 General operation...........................................................................................................................................333
20.4.2 Arbitration......................................................................................................................................................334
20.4.2.1 Arbitration during undefined length bursts................................................................................334
20.4.2.2 Fixed-priority operation............................................................................................................. 334
20.4.2.3 Round-robin priority operation.................................................................................................. 335
20.5 Initialization/application information........................................................................................................................... 336
Chapter 21
Peripheral Bridge (AIPS-Lite)
21.1 Number of peripheral bridges....................................................................................................................................... 337
21.2 Memory map.................................................................................................................................................................337
21.3 PACR registers..............................................................................................................................................................337
21.4 AIPS_Lite PACRE-P register reset values................................................................................................................... 337
21.5 Introduction...................................................................................................................................................................338
21.5.1 Features.......................................................................................................................................................... 338
21.5.2 General operation...........................................................................................................................................338
21.6 Memory map/register definition................................................................................................................................... 339
21.6.1 Master Privilege Register A (AIPS_MPRA)................................................................................................. 339
21.6.2 Peripheral Access Control Register (AIPS_PACRn).....................................................................................342
21.6.3 Peripheral Access Control Register (AIPS_PACRn).....................................................................................347
21.7 Functional description...................................................................................................................................................351
21.7.1 Access support............................................................................................................................................... 352
Chapter 22
Direct memory access multiplexer (DMAMUX)
22.1 Chip-specific DMAMUX information......................................................................................................................... 353
22.1.1 DMA MUX request sources.......................................................................................................................... 353
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22.1.2 DMA transfers via PIT trigger.......................................................................................................................355
22.2 Introduction...................................................................................................................................................................355
22.2.1 Overview........................................................................................................................................................355
22.2.2 Features.......................................................................................................................................................... 356
22.2.3 Modes of operation........................................................................................................................................ 356
22.3 External signal description............................................................................................................................................357
22.4 Memory map/register definition................................................................................................................................... 357
22.4.1 Channel Configuration register (DMAMUX_CHCFGn).............................................................................. 358
22.5 Functional description...................................................................................................................................................359
22.5.1 DMA channels with periodic triggering capability........................................................................................359
22.5.2 DMA channels with no triggering capability.................................................................................................361
22.5.3 Always-enabled DMA sources...................................................................................................................... 361
22.6 Initialization/application information........................................................................................................................... 363
22.6.1 Reset...............................................................................................................................................................363
22.6.2 Enabling and configuring sources..................................................................................................................363
Chapter 23
Direct Memory Access Controller (eDMA)
23.1 Introduction...................................................................................................................................................................367
23.1.1 eDMA system block diagram........................................................................................................................ 367
23.1.2 Block parts..................................................................................................................................................... 368
23.1.3 Features.......................................................................................................................................................... 369
23.2 Modes of operation....................................................................................................................................................... 370
23.3 Memory map/register definition................................................................................................................................... 371
23.3.1 TCD memory................................................................................................................................................. 371
23.3.2 TCD initialization.......................................................................................................................................... 371
23.3.3 TCD structure.................................................................................................................................................371
23.3.4 Reserved memory and bit fields.....................................................................................................................372
23.3.1 Control Register (DMA_CR).........................................................................................................................383
23.3.2 Error Status Register (DMA_ES).................................................................................................................. 386
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23.3.3 Enable Request Register (DMA_ERQ)......................................................................................................... 388
23.3.4 Enable Error Interrupt Register (DMA_EEI).................................................................................................390
23.3.5 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................... 392
23.3.6 Set Enable Error Interrupt Register (DMA_SEEI)........................................................................................ 393
23.3.7 Clear Enable Request Register (DMA_CERQ).............................................................................................394
23.3.8 Set Enable Request Register (DMA_SERQ).................................................................................................395
23.3.9 Clear DONE Status Bit Register (DMA_CDNE)..........................................................................................396
23.3.10 Set START Bit Register (DMA_SSRT)........................................................................................................ 397
23.3.11 Clear Error Register (DMA_CERR)..............................................................................................................398
23.3.12 Clear Interrupt Request Register (DMA_CINT)........................................................................................... 399
23.3.13 Interrupt Request Register (DMA_INT)........................................................................................................400
23.3.14 Error Register (DMA_ERR).......................................................................................................................... 402
23.3.15 Hardware Request Status Register (DMA_HRS).......................................................................................... 405
23.3.16 Enable Asynchronous Request in Stop Register (DMA_EARS)...................................................................408
23.3.17 Channel n Priority Register (DMA_DCHPRIn)............................................................................................ 410
23.3.18 TCD Source Address (DMA_TCDn_SADDR).............................................................................................411
23.3.19 TCD Signed Source Address Offset (DMA_TCDn_SOFF)..........................................................................411
23.3.20 TCD Transfer Attributes (DMA_TCDn_ATTR)...........................................................................................412
23.3.21 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO)...................................413
23.3.22 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).........................................................................................................414
23.3.23 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES)....................................................................................................... 415
23.3.24 TCD Last Source Address Adjustment (DMA_TCDn_SLAST)...................................................................416
23.3.25 TCD Destination Address (DMA_TCDn_DADDR).....................................................................................417
23.3.26 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)..................................................................417
23.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES).............................................................................................................418
23.3.28 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO).............................................................................................................. 419
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23.3.29 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)............ 420
23.3.30 TCD Control and Status (DMA_TCDn_CSR).............................................................................................. 421
23.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES).............................................................................................................423
23.3.32 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO).............................................................................................................. 424
23.4 Functional description...................................................................................................................................................425
23.4.1 eDMA basic data flow................................................................................................................................... 425
23.4.2 Fault reporting and handling..........................................................................................................................428
23.4.3 Channel preemption....................................................................................................................................... 431
23.4.4 Performance................................................................................................................................................... 431
23.4.4.1 Peak transfer rates...................................................................................................................... 431
23.4.4.2 Peak request rates.......................................................................................................................432
23.4.4.3 eDMA performance example.....................................................................................................434
23.5 Initialization/application information........................................................................................................................... 435
23.5.1 eDMA initialization....................................................................................................................................... 435
23.5.2 Programming errors....................................................................................................................................... 437
23.5.3 Arbitration mode considerations....................................................................................................................438
23.5.3.1 Fixed channel arbitration........................................................................................................... 438
23.5.3.2 Round-robin channel arbitration................................................................................................ 438
23.5.4 Performing DMA transfers............................................................................................................................ 438
23.5.4.1 Single request.............................................................................................................................438
23.5.4.2 Multiple requests........................................................................................................................440
23.5.4.3 Using the modulo feature...........................................................................................................442
23.5.5 Monitoring transfer descriptor status............................................................................................................. 442
23.5.5.1 Testing for minor loop completion............................................................................................ 442
23.5.5.2 Reading the transfer descriptors of active channels...................................................................443
23.5.5.3 Checking channel preemption status..........................................................................................444
23.5.6 Channel Linking.............................................................................................................................................444
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23.5.7 Dynamic programming.................................................................................................................................. 445
23.5.7.1 Dynamically changing the channel priority...............................................................................445
23.5.7.2 Dynamic channel linking........................................................................................................... 446
23.5.7.3 Dynamic scatter/gather.............................................................................................................. 446
Chapter 24
External Watchdog Monitor (EWM)
24.1 Chip-specific EWM information.................................................................................................................................. 451
24.1.1 EWM clocks...................................................................................................................................................451
24.1.2 EWM low-power modes................................................................................................................................ 451
24.1.3 EWM_OUT pin state in low power modes....................................................................................................451
24.2 Introduction...................................................................................................................................................................452
24.2.1 Features.......................................................................................................................................................... 452
24.2.2 Modes of Operation....................................................................................................................................... 453
24.2.2.1 Stop Mode..................................................................................................................................453
24.2.2.2 Debug Mode...............................................................................................................................453
24.2.3 Block Diagram............................................................................................................................................... 453
24.3 EWM Signal Descriptions............................................................................................................................................ 454
24.4 Memory Map/Register Definition.................................................................................................................................454
24.4.1 Control Register (EWM_CTRL)................................................................................................................... 455
24.4.2 Service Register (EWM_SERV)....................................................................................................................456
24.4.3 Compare Low Register (EWM_CMPL)........................................................................................................456
24.4.4 Compare High Register (EWM_CMPH).......................................................................................................457
24.5 Functional Description..................................................................................................................................................457
24.5.1 The EWM_out Signal.................................................................................................................................... 457
24.5.2 The EWM_in Signal...................................................................................................................................... 458
24.5.3 EWM Counter................................................................................................................................................459
24.5.4 EWM Compare Registers.............................................................................................................................. 459
24.5.5 EWM Refresh Mechanism.............................................................................................................................459
24.5.6 EWM Interrupt...............................................................................................................................................460
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Chapter 25
Watchdog Timer (WDOG)
25.1 Chip-specific WDOG information................................................................................................................................461
25.1.1 WDOG clocks................................................................................................................................................461
25.1.2 WDOG low-power modes............................................................................................................................. 461
25.2 Introduction...................................................................................................................................................................462
25.3 Features.........................................................................................................................................................................462
25.4 Functional overview......................................................................................................................................................463
25.4.1 Unlocking and updating the watchdog...........................................................................................................465
25.4.2 Watchdog configuration time (WCT)............................................................................................................466
25.4.3 Refreshing the watchdog................................................................................................................................467
25.4.4 Windowed mode of operation........................................................................................................................467
25.4.5 Watchdog disabled mode of operation...........................................................................................................467
25.4.6 Low-power modes of operation..................................................................................................................... 467
25.4.7 Debug modes of operation............................................................................................................................. 468
25.5 Testing the watchdog.................................................................................................................................................... 468
25.5.1 Quick test....................................................................................................................................................... 469
25.5.2 Byte test..........................................................................................................................................................469
25.6 Backup reset generator..................................................................................................................................................471
25.7 Generated resets and interrupts.....................................................................................................................................471
25.8 Memory map and register definition.............................................................................................................................472
25.8.1 Watchdog Status and Control Register High (WDOG_STCTRLH)............................................................. 472
25.8.2 Watchdog Status and Control Register Low (WDOG_STCTRLL).............................................................. 474
25.8.3 Watchdog Time-out Value Register High (WDOG_TOVALH)...................................................................475
25.8.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)....................................................................475
25.8.5 Watchdog Window Register High (WDOG_WINH).................................................................................... 476
25.8.6 Watchdog Window Register Low (WDOG_WINL)..................................................................................... 476
25.8.7 Watchdog Refresh register (WDOG_REFRESH)......................................................................................... 477
25.8.8 Watchdog Unlock register (WDOG_UNLOCK)...........................................................................................477
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