NXP Semiconductors LPC11E Series User manual

UM10518
LPC11Exx User manual
Rev. 3.5 — 21 December 2016 User manual
Document information
Info Content
Keywords LPC11Exx, ARM Cortex-M0, microcontroller, LPC11E11, LPC11E12,
LPC11E14, LPC11E13, LPC11E3x, LPC11E37H, LPC11E35, I/O Handler.
Abstract LPC11Exx User manual.

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LPC11Exx User manual
Revision history
Rev Date Description
3.5 20161221 LPC11Exx User manual
Modifications:
•Updated Section 19.8.8 “RAM used by ISP command handler”, Section 19.8.9 “RAM used by IAP command
handler”, and Section 19.13 “IAP commands”: Added on-chip local ROM.
•Updated Table 317 “IAP Prepare sector(s) for write operation command”, Table 318 “IAP Copy RAM to flash
command”, Table 319 “IAP Erase Sector(s) command”: Deleted The boot sector can not be prepared by this
command.
3.4 20140908 LPC11Exx User manual
Modifications:
•Added part LPC11E35FHI33/501.
3.3 20140611 LPC11Exx User manual
Modifications:
•I/O Handler interrupt added in Table 48 “Connection of interrupt sources to the Vectored Interrupt Controller”.
•NVIC register description added. See Section 5.5.
3.2 20140401 LPC11Exx User manual
Modifications:
•Table 13 “Internal resonant crystal control register (IRCCTRL, address 0x4004 8028) bit description” added.
•Watchdog interrupt flag polarity corrected: This flag is cleared by writing a 1 to the WDINT bit in the MOD register
(Section 15.8.1 “Watchdog mode register”).
•Use of IAP mode with power profiles clarified. Use power profiles in default mode when executing IAP
commands. See Section 19.13 “IAP commands” and Section 5.3.
•Section 5.3 added to clarify use of power profiles.
•Remark added to Section 3.9.4.3 “Wake-up from Deep-sleep mode” and Section 3.9.5.3 “Wake-up from
Power-down mode”: After wake-up, reprogram the clock source for the main clock.
•Pin description tables for RESET/PIO0_0 updated: In deep power-down mode, this pin must be pulled HIGH
externally. The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is
not needed. See Chapter 8 “LPC11Exx Pin configuration”.
•Pin description notes relating to open-drain I2C-bus pins updated for clarity. Chapter 8 “LPC11Exx Pin
configuration”.
•Pin description of the WAKEUP pin updated for clarity. Chapter 8 “LPC11Exx Pin configuration”.
3.1 20131220 LPC11Exx User manual
Modifications:
•SYSAHBCLKCTRL reset value corrected. Table 5.
•Reserved function added to IOCON pin configuration registers PIO0_8 and PIO0_9. See Table 61 and Table 62.
3 20131125 LPC11Exx User manual

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LPC11Exx User manual
Modifications:
•Boot loader description clarified. See Section 19.4.
•Part LPC11E37HFBD64/401 added.
•Clock for SRAM2 block added in SYSAHBCLKCTRL register. See Table 19.
•SRAM memory naming updated in Chapter 2 “LPC11Exx Memory mapping”.
•Description of ISP Go command: example added. See Section 19.12.8.
•API pointer structure updated in Figure 8 and Figure 64.
•Power Profiles API pointer definitions corrected. See Section 5.4.
•Chapter 22 “LPC11Exx I/O Handler” added.
•Chapter 18 “LPC11Exx I/O EEPROM” added to summarize the EEPROM functionality and features.
•Section 19.13 “IAP commands” updated.
2 20121025 LPC11Exx User manual
Modifications:
•SRAM use by boot loader specified in Section 18.2.
•Description of interrupt use with IAP calls updated (see Section 18.8.7).
•Description of ISP Go command updated (only Thumb mode allowed).
•Update EEPROM write command (see Section 18.13.11). The top 64 bytes are reserved for the 4 kB EEPROM
only.
•Figure 60 corrected.
•Remove the following step to execute before entering Deep power-down: Enable the IRC. This step is not longer
required. See Section 3.9.6 “Deep power-down mode”.
•Description of the BYPASS bit corrected in Table 11 “System oscillator control register (SYSOSCCTRL, address
0x4004 8020) bit description””.
•FREQSEL bit values updated in Table 12 “Watchdog oscillator control register (WDTOSCCTRL, address 0x4004
8024) bit description”.
•Editorial updates to Section 9.4.1 and Section 9.6.4.
•BOD interrupt level 0 removed. See Section 3.5.22 “BOD control register”.
•Explained use of interrupts with Power profiles in Section 5.3 “General description”.
•Remove instruction breakpoints from feature list for SWD. See Section 19.2.
•Register offset of the CR1 register corrected in timers CT16B0 and CT32B0. See Table 214 and Table 235.
•Bit position of the CAP1 interrupt flag corrected in the IR registers of timers CT16B0 and CT32B0. See Table 216
and Table 235.
•Bit positions of the CAP1 edge and interrupt control bits corrected in the CCR registers of timers CT16B0 and
CT32B0. See Table 224 and Table 245.
•Bit values of the CAP1 counter mode and capture input select bits corrected in the CTCR registers of timers
CT16B0 and CT32B0. See Table 231 and Table 252.
•Polarity of FILTR bit corrected in IOCON registers TDI_PIO0_11 to PIO0_16, and PIO0_21 and PIO0_22. See
Chapter 7 “LPC11Exx I/O configuration”.
•Parts LPC11E3x added.
Revision history …continued
Rev Date Description

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Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NXP Semiconductors UM10518
LPC11Exx User manual
1 20120208 LPC11Exx User manual
Revision history …continued
Rev Date Description

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1.1 Introduction
The LPC11Exx are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for
8/16-bit microcontroller applications, offering performance, low power, simple instruction
set and memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC11Exx operate at CPU frequencies of up to 50 MHz. The peripheral complement
of the LPC11Exx includes up to 32 kB of flash memory, up to 8 kB of SRAM data memory,
one Fast-mode Plus I2C-bus interface, one RS-485/EIA-485 USART with support for
synchronous mode and smart card interface, two SSP interfaces, four general purpose
counter/timers, a 10-bit ADC, and up to 54 general purpose I/O pins.
The I/O Handler is a software library-supported hardware engine that can be used to add
performance, connectivity and flexibility to system designs. It is available on the
LPC11E37HFBD64/401. The I/O Handler can emulate serial interfaces such as UART,
I2C, and I2S with no or very low additional CPU load and can off-load the CPU by
performing processing-intensive functions like DMA transfers in hardware. Software
libraries for multiple I/O Handler applications are available on http://www.LPCware.com.
For additional documentation, see Section 24.2 “References”.
1.2 Features
•System:
–ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
–ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
–Non-Maskable Interrupt (NMI) input selectable from several input sources.
–System tick timer.
•Memory:
–Up to 32 kB on-chip flash program memory (LPC11E1x).
–Up to 128 kB on-chip flash program memory with sector (4 kB) and page erase
(256 byte) access (LPC11E3x).
–Up to 4 kB on-chip EEPROM data memory; byte erasable and byte programmable.
–Up to 12 kB SRAM data memory.
–16 kB boot ROM.
–In-System Programming (ISP) and In-Application Programming (IAP) for flash and
EEPROM via on-chip bootloader software.
–ROM-based 32-bit integer division routines.
•Debug options:
–Standard JTAG test interface for BSDL.
–Serial Wire Debug.
UM10518
Chapter 1: LPC11Exx Introductory information
Rev. 3.5 — 21 December 2016 User manual

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Chapter 1: LPC11Exx Introductory information
•Digital peripherals:
–Up to 54 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down
resistors, repeater mode, and open-drain mode.
–Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.
–Two GPIO grouped interrupt modules enable an interrupt based on a
programmable pattern of input states of a group of GPIO pins.
–High-current source output driver (20 mA) on one pin.
–High-current sink driver (20 mA) on true open-drain pins.
–Four general-purpose counter/timers with a total of up to 5 capture inputs and 13
match outputs.
–Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal
low-power WatchDog Oscillator (WDO).
•Analog peripherals:
–10-bit ADC with input multiplexing among eight pins.
•Serial interfaces:
–USART with fractional baud rate generation, internal FIFO, a full modem control
handshake interface, and support for RS-485/9-bit mode and synchronous mode.
USART supports an asynchronous smart card interface (ISO 7816-3).
–Two SSP controllers with FIFO and multi-protocol capabilities.
–I2C-bus interface supporting the full I2C-bus specification and Fast-mode Plus with
a data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.
•I/O Handler for hardware emulation of serial interfaces and DMA; supported through
software libraries.(LPC11E37HFBD64/401 only.)
•Clock generation:
–Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).
–12 MHz high-frequency Internal RC oscillator (IRC) that can optionally be used as
a system clock.
–Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable
frequency output.
–PLL allows CPU operation up to the maximum CPU rate with the system oscillator
or the IRC as clock sources.
–Clock output function with divider that can reflect the crystal oscillator, the main
clock, the IRC, or the watchdog oscillator.
•Power control:
–Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep, Deep-sleep, Power-down, and Deep power-down modes.
–Power profiles residing in boot ROM allow optimized performance and minimized
power consumption for any given application through one simple function call.
–Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
–Processor wake-up from Deep-sleep and Power-down modes via reset, selectable
GPIO pins, or a watchdog interrupt.
–Processor wake-up from Deep power-down mode using one special function pin.

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Chapter 1: LPC11Exx Introductory information
–Power-On Reset (POR).
–Brownout detect with four separate thresholds for interrupt and forced reset.
•Unique device serial number for identification.
•Single 3.3 V power supply (1.8 V to 3.6 V).
•Temperature range 40 C to +85 C.
•Available as LQFP64, LQFP48, HVQFN33 (7x7), and HVQFN33 (5x5) packages.

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Chapter 1: LPC11Exx Introductory information
1.3 Ordering information
[1] Top 64 byte are reserved for 4 kB EEPROM.
[2] This part includes I/O Handler; additional 2 kB of SRAM1 available for I/O Handler library only; see Table 3 “LPC11Exx memory
configuration”.
Table 1. Ordering information
Type number Package
Name Description Version
LPC11E35FHI33/501 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 550.85 mm n/a
LPC11E11FHN33/101 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 7 7 0.85 mm n/a
LPC11E12FBD48/201 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11E13FBD48/301 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11E14FHN33/401 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 7 7 0.85 mm n/a
LPC11E14FBD48/401 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11E14FBD64/401 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2
LPC11E36FBD64/501 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2
LPC11E36FHN33/501 HVQFN33 plastic thermal enhanced very thin quad flat package; no leads; 33
terminals; body 7 7 0.85 mm n/a
LPC11E37FBD48/501 LQFP48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm SOT313-2
LPC11E37HFBD64/401 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2
LPC11E37FBD64/501 LQFP64 plastic low profile quad flat package; 64 leads; body 10 10 1.4 mm SOT314-2
Table 2. Part ordering options
Part Number Flash EEPROM Total
general
purpose
SRAM
I2C-bus
FM+ USART SSP ADC channels GPIO
LPC11E11FHN33/101 8 kB 512 B 4 kB 1 1 2 8 28
LPC11E12FBD48/201 16 kB 1 kB 6 kB 1 1 2 8 40
LPC11E13FBD48/301 24 kB 2 kB 8 kB 1 1 2 8 40
LPC11E14FHN33/401 32 kB 4 kB[1] 10 kB 1 1 2 8 28
LPC11E14FBD48/401 32 kB 4 kB[1] 10 kB 1 1 2 8 40
LPC11E14FBD64/401 32 kB 4 kB[1] 10 kB 1 1 2 8 54
LPC11E35FHI33/501 64 kB 4 kB[1] 12 kB 1 1 2 8 26
LPC11E36FBD64/501 96 kB 4 kB[1] 12 kB 1 1 2 8 54
LPC11E36FHN33/501 96 kB 4 kB[1] 12 kB 1 1 2 8 28
LPC11E37FBD48/501 128 kB 4 kB[1] 12 kB 1 1 2 8 40
LPC11E37HFBD64/401[2] 128 kB 4 kB[1] 10 kB 1 1 2 8 54
LPC11E37FBD64/501 128 kB 4 kB[1] 12 kB 1 1 2 8 54

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Chapter 1: LPC11Exx Introductory information
1.4 Block diagram
(1) Not available on HVQFN33 packages.
(2) CT16B0/1_CAP1, CT32B1_CAP1 available on the LQFP64 package only. CT32B0_CAP1 available on the LQFP64 and
LQFP48 packages only.
Fig 1. Block diagram
SRAM
4/6/8/10 kB
ARM
CORTEX-M0
TEST/DEBUG
INTERFACE
FLASH
8/16/24/32 kB
HIGH-SPEED
GPIO
AHB TO APB
BRIDGE
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
RESET
SWD, JTAG
LPC11E1x
slave
slave slave slave
ROM
16 kB
slave
AHB-LITE BUS
GPIO ports 0/1
CLKOUT
IRC, WDO
SYSTEM OSCILLATOR
POR
PLL0
BOD
10-bit ADC
USART/
SMARTCARD INTERFACE AD[7:0]
RXD
TXD
CTS, RTS, DTR
SCLK
GPIO INTERRUPTS
32-bit COUNTER/TIMER 0
CT32B0_MAT[3:0]
CT32B0_CAP[1:0](2)
32-bit COUNTER/TIMER 1
CT32B1_MAT[3:0]
CT32B1_CAP[1:0](2)
DCD, DSR(1), RI(1)
16-bit COUNTER/TIMER 1
WINDOWED WATCHDOG
TIMER
GPIO GROUP0 INTERRUPTS
CT16B1_MAT[1:0]
16-bit COUNTER/TIMER 0
CT16B0_MAT[2:0]
CT16B0_CAP[1:0](2)
CT16B1_CAP[1:0](2)
GPIO pins
GPIO pins
GPIO GROUP1 INTERRUPTS
GPIO pins
system bus
SSP0 SCK0, SSEL0,
MISO0, MOSI0
SSP1 SCK1, SSEL1,
MISO1, MOSI1
I2C-BUS
IOCON
SYSTEM CONTROL
PMU
SCL, SDA
XTALIN XTALOUT
002aag683
EEPROM
512 B
1/2/4 kB

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Chapter 1: LPC11Exx Introductory information
(1) Not available on HVQFN33 packages.
(2) CT16B0_CAP1, CT16B1_CAP1 available on LQFP64 packages only; CT32B0_CAP1 available LQFP48, and LQFP64
packages only; CT32B1_CAP1 available in LQFP64 packages only.
(3) LPC11E37HFBD64/401 only.
Fig 2. Block diagram
SRAM
10/12 kB
ARM
CORTEX-M0
TEST/DEBUG
INTERFACE
FLASH
64/96/128 kB
HIGH-SPEED
GPIO
AHB TO APB
BRIDGE
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
RESET
SWD, JTAG
LPC11E3x
slave
slave slave slave
ROM
16 kB
slave
AHB-LITE BUS
GPIO ports 0/1
CLKOUT
IRC, WDO
SYSTEM OSCILLATOR
POR
PLL0
BOD
10-bit ADC
USART/
SMARTCARD INTERFACE AD[7:0]
RXD
TXD
CTS, RTS, DTR
SCLK
GPIO INTERRUPTS
32-bit COUNTER/TIMER 0
CT32B0_MAT[3:0]
CT32B0_CAP[1:0](2)
32-bit COUNTER/TIMER 1
CT32B1_MAT[3:0]
CT32B1_CAP[1:0](2)
DCD, DSR(1), RI(1)
16-bit COUNTER/TIMER 1
WINDOWED WATCHDOG
TIMER
GPIO GROUP0 INTERRUPTS
CT16B1_MAT[1:0]
16-bit COUNTER/TIMER 0
CT16B0_MAT[2:0]
CT16B0_CAP[1:0](2)
CT16B1_CAP[1:0](2)
GPIO pins
GPIO pins
GPIO GROUP1 INTERRUPTS
GPIO pins
system bus
SSP0 SCK0, SSEL0,
MISO0, MOSI0
SSP1 SCK1, SSEL1,
MISO1, MOSI1
I2C-BUS
IOCON
SYSTEM CONTROL
PMU
SCL, SDA
XTALIN XTALOUT
002aah401
EEPROM
4 kB
master
I/O
HANDLER(3)
IOH_[20:0]

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2.1 How to read this chapter
See Table 3 for the memory configuration of the LPC11Exx parts.
[1] Top 64 byte are reserved for 4 kB EEPROM.
[2] For I/O Handler use only.
2.2 Memory map
The LPC11Exx incorporates several distinct memory regions, shown in the following
figures. Figure 3 shows the overall map of the entire address space from the user
program viewpoint following reset.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
UM10518
Chapter 2: LPC11Exx Memory mapping
Rev. 3.5 — 21 December 2016 User manual
Table 3. LPC11Exx memory configuration
Part Flash in
kB Main SRAM0 at 0x1000 0000
in kB
SRAM1 at
0x2000 0000
in kB
SRAM2 at
0x2000 4000
in kB
EEPROM
in kB
LPC11E11FHN33/101 8 4 - - 0.5
LPC11E12FBD48/201 16 6 - - 1
LPC11E13FBD48/301 24 8 - - 2
LPC11E14FHN33/401 32 8 2 - 4 [1]
LPC11E14FBD48/401 32 8 2 - 4
[1]
LPC11E14FBD64/401 32 8 2 - 4
[1]
LPC11E35FHI33/501 64 8 2 2 4 [1]
LPC11E36FBD64/501 96 8 2 2 4
[1]
LPC11E36FHN33/501 96 8 2 2 4
[1]
LPC11E37FBD48/501 128 8 2 2 4
[1]
LPC11E37HFBD64/401 128 8 2[2] 24
[1]
LPC11E37FBD64/501 128 8 2 2 4
[1]

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Chapter 2: LPC11Exx Memory mapping
Fig 3. LPC11E1x memory map
APB peripherals
0x4000 4000
0x4000 8000
0x4000 C000
0x4001 0000
0x4001 8000
0x4002 0000
0x4002 8000
0x4003 8000
0x4003 C000
0x4004 0000
0x4004 4000
0x4004 8000
0x4004 C000
0x4004 C000
0x4005 8000
0x4005 C000
0x4006 0000
0x4006 4000
0x4008 0000
0x4002 4000
0x4001 C000
0x4001 4000
0x4000 0000
WWDT
32-bit counter/timer 0
32-bit counter/timer 1
ADC
USART/SMART CARD
PMU
I
2
C-bus
20 - 21 reserved
10 - 13 reserved
reserved
reserved
25 - 31 reserved
0
1
2
3
4
5
6
7
8
9
16
15
14
17
18
reserved
reserved
0x0000 0000
0 GB
0.5 GB
4 GB
1 GB
0x1000 1800
0x1FFF 0000
0x1FFF 4000
0x2000 0000
0x5000 0000
0x5000 4000
0xFFFF FFFF
reserved
reserved
2 kB SRAM1 (LPC11E14/401)
reserved
0x4000 0000
0x4008 0000
APB peripherals
GPIO
0x2000 0800
6 kB SRAM0 (LPC11E12/201) 0x1000 1000
4 kB SRAM0 (LPC11E11/101)
0x1000 2000
8 kB SRAM0 (LPC11E13/301
LPC11E14/401)
0x1000 0000
LPC11E1x
0x0000 6000
24 kB on-chip flash (LPC11E13) 0x0000 4000
16 kB on-chip flash (LPC11E12) 0x0000 2000
8 kB on-chip flash (LPC11E11)
0x0000 8000
32 kB on-chip flash (LPC11E14)
16 kB boot ROM
0x0000 0000
0x0000 00C0
active interrupt vectors
reserved
reserved
SSP0
SSP1
16-bit counter/timer 1
16-bit counter/timer 0
IOCON
system control
19 GPIO interrupts
22
23 GPIO GROUP0 INT
24 GPIO GROUP1 INT
flash/EEPROM controller
0xE000 0000
0xE010 0000
private peripheral bus

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Chapter 2: LPC11Exx Memory mapping
Fig 4. LPC11E3x memory map
APB peripherals
0x4000 4000
0x4000 8000
0x4000 C000
0x4001 0000
0x4001 8000
0x4002 0000
0x4002 8000
0x4003 8000
0x4003 C000
0x4004 0000
0x4004 4000
0x4004 8000
0x4004 C000
0x4004 C000
0x4005 8000
0x4005 C000
0x4006 0000
0x4006 4000
0x4008 0000
0x4002 4000
0x4001 C000
0x4001 4000
0x4000 0000
WWDT
32-bit counter/timer 0
32-bit counter/timer 1
ADC
USART/SMART CARD
PMU
I
2
C-bus
20 - 21 reserved
10 - 13 reserved
reserved
reserved
25 - 31 reserved
0
1
2
3
4
5
6
7
8
9
16
15
14
17
18
reserved
reserved
0x0000 0000
0 GB
0.5 GB
4 GB
1 GB
0x1000 0000
0x1FFF 0000
0x1FFF 4000
0x2000 0000
0x5000 0000
0x5000 4000
0xFFFF FFFF
reserved
reserved
reserved
2 kB SRAM2
reserved
reserved
0x4000 0000
0x4008 0000
0x4008 4000
APB peripherals
GPIO
0x2000 4000
0x2000 4800
0x1000 2000
8 kB SRAM0
LPC11E3x
0x0001 8000
96 kB on-chip flash (LPC11E36)
0x0002 0000
0x0001 0000
128 kB on-chip flash (LPC11E37)
64 kB on-chip flash (LPC11E35)
16 kB boot ROM
0x0000 0000
0x0000 00C0
active interrupt vectors
002aah405
reserved
reserved
SSP0
SSP1
16-bit counter/timer 1
16-bit counter/timer 0
IOCON
system control
19 GPIO interrupts
22
23 GPIO GROUP0 INT
24 GPIO GROUP1 INT
flash/EEPROM controller
0xE000 0000
0xE010 0000
private peripheral bus
2 kB SRAM1/
I/O Handler code area
for LPC11E37HFBD64/401
0x2000 0800

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User manual Rev. 3.5 — 19 December 2016 14 of 424
3.1 How to read this chapter
The system control block is identical for all LPC11Exx parts.
The DEVICE_ID register contains the device id numbers for the LPC11E1x parts. For
LPC11E3x parts, see the ISP/IAP Read Part Id command (Table 311 “LPC11Exx device
identification numbers”).
Bit RAM2 in the SYSAHBCLKCTRL register is available for parts LPC11E3x and reserved
for parts LPC11E1x. See Table 20.
Remark: For part LPC11E37H, enable the SRAM1 clock for running the I/O Handler
software library code in the SYSAHBCLKCTRL register. See Table 20.
3.2 Introduction
The system configuration block controls oscillators, some aspects of the power
management, and the clock generation of the LPC11Exx. Also included in this block is a
register for remapping flash, SRAM, and ROM memory areas.
3.3 Pin description
Table 4 shows pins that are associated with system control block functions.
3.4 Clocking and power control
See Figure 5 for an overview of the LPC11Exx Clock Generation Unit (CGU).
The LPC11Exx include three independent oscillators. These are the system oscillator, the
Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for
more than one purpose as required in a particular application.
Following reset, the LPC11Exx will operate from the Internal RC oscillator until switched
by software. This allows systems to operate without an external crystal and the bootloader
code to operate at a known frequency.
The SYSAHBCLKCTRL register gates the system clock to the various peripherals and
memories. USART and SSP have individual clock dividers to derive peripheral clocks
from the main clock.
UM10518
Chapter 3: LPC11Exx System control block
Rev. 3.5 — 19 December 2016 User manual
Table 4. Pin summary
Pin name Pin
direction Pin description
CLKOUT O Clockout pin
PIO0 and PIO1 pins I Eight pins can be selected as external interrupt
pins from all available GPIO pins (see Table 33).

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Chapter 3: LPC11Exx System control block
The main clock, and the clock outputs from the IRC, the system oscillator, and the
watchdog oscillator can be observed directly on the CLKOUT pin.
3.5 Register description
All system control block registers are on word address boundaries. Details of the registers
appear in the description of each function.
In addition to the system control block registers described in Table 5, the flash access
timing register, which can be re-configured as part the system setup, is described in
Table 6. This register is not part of the system configuration block.
All address offsets not shown in Table 5 and Table 6 are reserved and should not be
written.
Fig 5. LPC11Exx CGU block diagram
watchdog oscillator
IRC oscillator
SYSTEM CLOCK
DIVIDER
SYSAHBCLKCTRLn
(AHB clock enable)
CPU, system control,
PMU
memories,
peripheral clocks
SSP0 PERIPHERAL
CLOCK DIVIDER SSP0
SSP1 PERIPHERAL
CLOCK DIVIDER SSP1
USART PERIPHERAL
CLOCK DIVIDER UART
WDT
WDCLKSEL
(WDT clock select)
watchdog oscillator
IRC oscillator
system oscillator CLKOUT PIN CLOCK
DIVIDER CLKOUT pin
CLKOUTUEN
(CLKOUT update enable)
002aag687
system clock
SYSTEM PLL
IRC oscillator
system oscillator
watchdog oscillator
MAINCLKSEL
(main clock select)
SYSPLLCLKSEL
(system PLL clock select)
main clock
IRC oscillator
n

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Chapter 3: LPC11Exx System control block
Table 5. Register overview: system control block (base address 0x4004 8000)
Name Access Offset Description Reset
value Reset value
after boot
Reference
SYSMEMREMAP R/W 0x000 System memory remap 0 0 Table 7
PRESETCTRL R/W 0x004 Peripheral reset control 0 0 Table 8
SYSPLLCTRL R/W 0x008 System PLL control 0 0 Table 9
SYSPLLSTAT R 0x00C System PLL status 0 0 Table 10
- - 0x010 Reserved - - -
- - 0x014 Reserved - - -
SYSOSCCTRL R/W 0x020 System oscillator control 0x000 0x000 Table 11
WDTOSCCTRL R/W 0x024 Watchdog oscillator control 0x0A0 0x0A0 Table 12
IRCCTRL R/W 0x028 IRC control 0x080 - Table 13
- - 0x02C Reserved - - -
SYSRSTSTAT R/W 0x030 System reset status register 0 0 Table 14
SYSPLLCLKSEL R/W 0x040 System PLL clock source select 0 0 Table 15
SYSPLLCLKUEN R/W 0x044 System PLL clock source update enable 0 0 Table 16
- R/W 0x048 Reserved - - -
- R/W 0x04C Reserved - - -
MAINCLKSEL R/W 0x070 Main clock source select 0 0 Table 17
MAINCLKUEN R/W 0x074 Main clock source update enable 0 0 Table 18
SYSAHBCLKDIV R/W 0x078 System clock divider 0x001 0x001 Table 19
SYSAHBCLKCTRL R/W 0x080 System clock control 0x3F 0x0800
485F Table 20
SSP0CLKDIV R/W 0x094 SSP0 clock divider 0 0 Table 21
UARTCLKDIV R/W 0x098 UART clock divider 0 0 Table 22
SSP1CLKDIV R/W 0x09C SSP1 clock divider 0 0 Table 23
- - 0x0A0 -
0x0BC Reserved ---
- - 0x0C0 Reserved - - -
- - 0x0C4 Reserved - - -
- - 0x0C8 Reserved - - -
- - 0x0CC Reserved - - -
CLKOUTSEL R/W 0x0E0 CLKOUT clock source select 0 0 Table 24
CLKOUTUEN R/W 0x0E4 CLKOUT clock source update enable 0 0 Table 25
CLKOUTDIV R/W 0x0E8 CLKOUT clock divider 0 0 Table 26
PIOPORCAP0 R 0x100 POR captured PIO status 0 user
dependent user dependent Table 27
PIOPORCAP1 R 0x104 POR captured PIO status 1 user
dependent user dependent Table 28
BODCTRL R/W 0x150 Brown-Out Detect 0 0 Table 29
SYSTCKCAL R/W 0x154 System tick counter calibration 0x0 0x0 Table 30
IRQLATENCY R/W 0x170 IQR delay. Allows trade-off between
interrupt latency and determinism. 0x0000 0010 0x0000 0010
NMISRC R/W 0x174 NMI Source Control 0 0 Table 32

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Chapter 3: LPC11Exx System control block
3.5.1 System memory remap register
The system memory remap register selects whether the exception vectors are read from
boot ROM, flash, or SRAM. By default, the flash memory is mapped to address 0x0000
0000. When the MAP bits in the SYSMEMREMAP register are set to 0x0 or 0x1, the boot
ROM or RAM respectively are mapped to the bottom 512 bytes of the memory map
(addresses 0x0000 0000 to 0x0000 0200).
PINTSEL0 R/W 0x178 GPIO Pin Interrupt Select register 0 0 0 Table 33
PINTSEL1 R/W 0x17C GPIO Pin Interrupt Select register 1 0 0 Table 33
PINTSEL2 R/W 0x180 GPIO Pin Interrupt Select register 2 0 0 Table 33
PINTSEL3 R/W 0x184 GPIO Pin Interrupt Select register 3 0 0 Table 33
PINTSEL4 R/W 0x188 GPIO Pin Interrupt Select register 4 0 0 Table 33
PINTSEL5 R/W 0x18C GPIO Pin Interrupt Select register 5 0 0 Table 33
PINTSEL6 R/W 0x190 GPIO Pin Interrupt Select register 6 0 0 Table 33
PINTSEL7 R/W 0x194 GPIO Pin Interrupt Select register 7 0 0 Table 33
- 0x198 Reserved - - -
- 0x19C Reserved - - -
STARTERP0 R/W 0x204 Start logic 0 interrupt wake-up enable
register 0 00Table 34
STARTERP1 R/W 0x214 Start logic 1 interrupt wake-up enable
register 1 00Table 35
PDSLEEPCFG R/W 0x230 Power-down states in deep-sleep mode 0xFFFF 0xFFFF Table 36
PDAWAKECFG R/W 0x234 Power-down states for wake-up from
deep-sleep 0xEDF0 0xEDF0 Table 37
PDRUNCFG R/W 0x238 Power configuration register 0xEDF0 0xEDF0 Table 38
DEVICE_ID R 0x3F4 Device ID part
dependent part dependent Table 39
Table 5. Register overview: system control block (base address 0x4004 8000) …continued
Name Access Offset Description Reset
value Reset value
after boot
Reference
Table 6. Register overview: flash control block (base address 0x4003 C000)
Name Access Offset Description Reset value Reference
FLASHCFG R/W 0x010 Flash read access configuration - Table 40

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Chapter 3: LPC11Exx System control block
3.5.2 Peripheral reset control register
This register allows software to reset specific peripherals. A 0 in an assigned bit in this
register resets the specified peripheral. A 1 negates the reset and allows peripheral
operation.
Remark: Before accessing the SSP and I2C peripherals, write a 1 to this register to
ensure that the reset signals to the SSP and I2C are de-asserted.
3.5.3 System PLL control register
This register connects and enables the system PLL and configures the PLL multiplier and
divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various
clock sources. The input frequency is multiplied to a higher frequency and then divided
down to provide the actual clock used by the CPU, peripherals, and memories. The PLL
can produce a clock up to the maximum allowed for the CPU.
Table 7. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit
description
Bit Symbol Value Description Reset
value
1:0 MAP System memory remap. Value 0x3 is reserved. 0x2
0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot
ROM.
0x1 User RAM Mode. Interrupt vectors are re-mapped to Static
RAM.
0x2 User Flash Mode. Interrupt vectors are not re-mapped and
reside in Flash.
31:2 - - Reserved -
Table 8. Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit
description
Bit Symbol Value Description Reset
value
0 SSP0_RST_N SSP0 reset control 0
0 Resets the SSP0 peripheral.
1 SSP0 reset de-asserted.
1 I2C_RST_N I2C reset control 0
0 Resets the I2C peripheral.
1 I2C reset de-asserted.
2 SSP1_RST_N SSP1 reset control 0
0 Resets the SSP1 peripheral.
1 SSP1 reset de-asserted.
3 - Reserved -
31:4 - - Reserved -

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Chapter 3: LPC11Exx System control block
3.5.4 System PLL status register
This register is a Read-only register and supplies the PLL lock status (see
Section 3.10.1).
3.5.5 System oscillator control register
This register configures the frequency range for the system oscillator.
Table 9. System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description
Bit Symbol Value Description Reset
value
4:0 MSEL Feedback divider value. The division value M is the
programmed MSEL value + 1.
00000: Division ratio M = 1
to
11111: Division ratio M = 32
0
6:5 PSEL Post divider ratio P. The division ratio is 2 P. 0
0x0 P = 1
0x1 P = 2
0x2 P = 4
0x3 P = 8
31:7 - - Reserved. Do not write ones to reserved bits. -
Table 10. System PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description
Bit Symbol Value Description Reset
value
0 LOCK PLL lock status 0
0 PLL not locked
1 PLL locked
31:1 - - Reserved -
Table 11. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit
description
Bit Symbol Value Description Reset
value
0 BYPASS Bypass system oscillator 0x0
0 Oscillator is not bypassed.
1 Bypass enabled. PLL input (sys_osc_clk) is fed
directly from the XTALIN pin bypassing the
oscillator. Use this mode when using an external
clock source instead of the crystal oscillator.
1 FREQRANGE Determines frequency range for Low-power
oscillator. 0x0
0 1 - 20 MHz frequency range.
1 15 - 25 MHz frequency range
31:2 - - Reserved 0x00

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Chapter 3: LPC11Exx System control block
3.5.6 Watchdog oscillator control register
This register configures the watchdog oscillator. The oscillator consists of an analog and a
digital part. The analog part contains the oscillator function and generates an analog clock
(Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the
required output clock frequency wdt_osc_clk. The analog output frequency (Fclkana) can
be adjusted with the FREQSEL bits between 600 kHz and 4.6 MHz. With the digital part
Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits.
The output clock frequency of the watchdog oscillator can be calculated as
wdt_osc_clk = Fclkana/(2 (1 + DIVSEL)) = 9.4 kHz to 2.3 MHz (nominal values).
Remark: Any setting of the FREQSEL bits will yield a Fclkana value within 40% of the
listed frequency value. The watchdog oscillator is the clock source with the lowest power
consumption. If accurate timing is required, use the IRC or system oscillator.
Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog
oscillator frequency must be programmed by writing to the WDTOSCCTRL register before
using the watchdog oscillator.
Table 12. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit
description
Bit Symbol Value Description Reset
value
4:0 DIVSEL Select divider for Fclkana.
wdt_osc_clk = Fclkana/ (2 (1 + DIVSEL))
00000: 2 (1 + DIVSEL) = 2
00001: 2 (1 + DIVSEL) = 4
to
11111: 2 (1 + DIVSEL) = 64
0
8:5 FREQSEL Select watchdog oscillator analog output frequency
(Fclkana). 0x00
0x1 0.6 MHz
0x2 1.05 MHz
0x3 1.4 MHz
0x4 1.75 MHz
0x5 2.1 MHz
0x6 2.4 MHz
0x7 2.7 MHz
0x8 3.0 MHz
0x9 3.25 MHz
0xA 3.5 MHz
0xB 3.75 MHz
0xC 4.0 MHz
0xD 4.2 MHz
0xE 4.4 MHz
0xF 4.6 MHz
31:9 - - Reserved 0x00