NXP Semiconductors LPC1102 User manual

UM10429
LPC1102 User manual
Rev. 1 — 20 October 2010 User manual
Document information
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Keywords ARM Cortex-M0, LPC1102, LPC1102UK
Abstract LPC1102 User manual

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For sales office addresses, please send an email to: [email protected]
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LPC1102 UM
Revision history
Rev Date Description
1 20101020 LPC1102 User manual

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1.1 Introduction
The LPC1102 is an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit
microcontroller applications, offering performance, low power, simple instruction set and
memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC1102 operates at CPU frequencies of up to 50 MHz.
The peripheral complement of the LPC1102 includes 32 kB of flash memory, 8 kB of data
memory, one RS-485/EIA-485 UART, one SPI interface with SSP features, four general
purpose counter/timers, a 10-bit ADC, and 11 general purpose I/O pins.
1.2 Features
•System:
–ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
–ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
–Serial Wire Debug.
–System tick timer.
•Memory:
–32 kB on-chip flash programming memory.
–8 kB SRAM.
–In-Application Programming (IAP) and In-System Programming (ISP) support via
on-chip bootloader software.
•Digital peripherals:
–11 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.
–GPIO pins can be used as edge and level sensitive interrupt sources.
–Four general purpose counter/timers with a total of one capture input and nine
match outputs.
–Programmable WatchDog Timer (WDT).
•Analog peripherals:
–10-bit ADC with input multiplexing among five pins.
UM10429
Chapter 1: LPC1102 Introductory information
Rev. 1 — 20 October 2010 User manual

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Chapter 1: LPC1102 Introductory information
•Serial interfaces:
–UART with fractional baud rate generation, internal FIFO, and RS-485 support.
–One SPI controller with SSP features and with FIFO and multi-protocol capabilities.
•Clock generation:
–12 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used
as a system clock.
–Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.
–PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from an external clock or the internal RC
oscillator.
–Clock output function with divider that can reflect the external clock, IRC clock,
CPU clock, and the Watchdog clock.
•Power control:
–Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep and Deep-sleep modes.
–Power profiles residing in boot ROM allowing to optimize performance and
minimize power consumption for any given application through one simple function
call.
–Two reduced power modes: Sleep and Deep-sleep modes.
–Processor wake-up from Deep-sleep mode via a dedicated start logic using up to
six of the functional pins.
–Power-On Reset (POR).
–Brownout detect with four separate thresholds for interrupt and forced reset.
•Unique device serial number for identification.
•Single 3.3 V power supply (1.8 V to 3.6 V).
•Available as WLCSP16 package.
1.3 Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
LPC1102UK WLCSP16 wafer level chip-size package; 16 bumps; 2.17 ×2.32 ×0.6 mm -
Table 2. Ordering options
Type number Flash Total
SRAM UART I2C/ Fm+ SPI ADC channels Package
LPC1102UK 32 kB 8 kB 1 - 1 5 WLCSP16

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Chapter 1: LPC1102 Introductory information
1.4 Block diagram
Fig 1. LPC1102 Block diagram
SRAM
8 kB
ARM
CORTEX-M0
TEST/DEBUG
INTERFACE
FLASH
32 kB
HIGH-SPEED
GPIO
AHB TO APB
BRIDGE
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
XTALIN
RESET
clocks and
controls
SWD
LPC1102
002aaf524
slave
slave
slave slave
ROM
slave
AHB-LITE BUS
GPIO port
PIO0/1
IRC
POR
SPI
10-bit ADC
UART
32-bit COUNTER/TIMER 0
WDT
IOCONFIG
CT32B0_MAT[3,1,0]
AD[4:0]
RXD
TXD
SYSTEM CONTROL
PMU
32-bit COUNTER/TIMER 1
CT32B1_MAT[2:0]
CT32B1_CAP0
16-bit COUNTER/TIMER 1
16-bit COUNTER/TIMER 0
CT16B0_MAT[2:0]
SCK, MISO,
MOSI
system bus

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Chapter 1: LPC1102 Introductory information
1.5 ARM Cortex-M0 processor
The ARM Cortex-M0 processor is described in detail in Section 19.2 “About the
Cortex-M0 processor and core peripherals”. For the LPC1102, the ARM Cortex-M0
processor core is configured as follows:
•System options:
–The Nested Vectored Interrupt Controller (NVIC) is included and supports up to 32
interrupts.
–The system tick timer is included.
•Debug options: Serial Wire Debug is included with two watchpoints and four
breakpoints.

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2.1 How to read this chapter
Table 3 shows the memory configuration for the LPC1102 part.
2.2 Memory map
Figure 2 shows the memory and peripheral address space of the LPC1102.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
On the LPC1102, the GPIO ports are the only AHB peripherals. The APB peripheral area
is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either
type is allocated 16 kB of space. This allows simplifying the address decoding for each
peripheral.
All peripheral register addresses are 32-bit word aligned regardless of their size. An
implication of this is that word and half-word registers must be accessed all at once. For
example, it is not possible to read or write the upper byte of a word register separately.
UM10429
Chapter 2: LPC1102 Memory mapping
Rev. 1 — 20 October 2010 User manual
Table 3. LPC1102 memory configuration
Part Flash SRAM
Suffix
LPC1102 32 kB 8 kB

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Chapter 2: LPC1102 Memory mapping
Fig 2. LPC1102 memory map
0x5000 0000
0x5001 0000
0x5002 0000
0x5020 0000
AHB peripherals
127 - 16 reserved
GPIO PIO1
7-4
0x5003 0000
0x5004 0000
reserved
reserved
11-8
15-12
GPIO PIO0
3-0
APB peripherals
0x4000 4000
0x4000 8000
0x4000 C000
0x4001 0000
0x4001 8000
0x4002 0000
0x4002 8000
0x4003 8000
0x4003 C000
0x4004 0000
0x4004 4000
0x4004 8000
0x4004 C000
0x4005 8000
0x4005 C000
0x4008 0000
0x4002 4000
0x4001 C000
0x4001 4000
0x4000 0000
WDT
32-bit counter/timer 0
32-bit counter/timer 1
ADC
UART
PMU
reserved
13 - 10 reserved
reserved
reserved
21 - 19 reserved
31 - 23 reserved
0
1
2
3
4
5
6
7
8
9
16
15
14
17
18
reserved
reserved
reserved
0x0000 0000
0 GB
0.5 GB
4 GB
1 GB
0x1000 2000
0x1FFF 0000
0x1FFF 4000
0x2000 0000
0x4000 0000
0x4008 0000
0x5000 0000
0x5020 0000
0xFFFF FFFF
reserved
reserved
reserved
APB peripherals
AHB peripherals
8 kB SRAM 0x1000 0000
LPC1102
0x0000 8000
32 kB on-chip flash
16 kB boot ROM
0x0000 0000
0x0000 00C0
active interrupt vectors
002aaf526
reserved
SPI
16-bit counter/timer 1
16-bit counter/timer 0
IOCONFIG
system control
22 reserved
flash controller
0xE000 0000
0xE010 0000
private peripheral bus

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3.1 How to read this chapter
This chapter applies to part LPC1102.
3.2 Introduction
The system configuration block controls oscillators, start logic, and clock generation of the
LPC1102. Also included in this block are registers for setting the priority for AHB access
and a register for remapping flash, SRAM, and ROM memory areas.
3.3 Pin description
Table 4 shows pins that are associated with system control block functions.
3.4 Clocking and power control
See Figure 3 for an overview of the LPC1102 Clock Generation Unit (CGU).
The LPC1102 include three independent oscillators. These are the system oscillator, the
Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for
more than one purpose as required in a particular application.
Following reset, the LPC1102 will operate from the Internal RC oscillator until switched by
software. This allows systems to operate without any external crystal and the bootloader
code to operate at a known frequency.
The SYSAHBCLKCTRL register gates the system clock to the various peripherals and
memories. UART, the WDT, and SPI0 have individual clock dividers to derive peripheral
clocks from the main clock.
For details on power control see Section 3.8.
UM10429
Chapter 3: LPC1102 System configuration
Rev. 1 — 20 October 2010 User manual
Table 4. Pin summary
Pin name Pin direction Pin description
PIO0_0; PIO0_8 to PIO0_11 I Start logic wake-up pins port 0
PIO1_0 I Start logic wake-up pin port 1

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Chapter 3: LPC1102 System configuration
3.5 Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
See Section 3.11 for the flash access timing register, which can be re-configured as part
the system setup. This register is not part of the system configuration block.
Fig 3. LPC1102 CGU block diagram
SYSTEM PLL
IRC oscillator
system oscillator watchdog oscillator
IRC oscillator
watchdog oscillator
MAINCLKSEL
(main clock select)
SYSPLLCLKSEL
(system PLL clock select)
SYSTEM CLOCK
DIVIDER
AHB clock 0
(system)
AHBCLKCTRL[1:18]
SPI0 PERIPHERAL
CLOCK DIVIDER SPI0_PCLK
UART PERIPHERAL
CLOCK DIVIDER UART_PCLK
WDT CLOCK
DIVIDER WDT_PCLK
WDTUEN
(WDT clock update enable)
main clock
system clock
IRC oscillator
AHB clocks
1 to 18
(memories
and peripherals)
18
sys_pllclkout
sys_pllclkin
Table 5. Register overview: system control block (base address 0x4004 8000)
Name Access Address offset Description Reset
value Reference
SYSMEMREMAP R/W 0x000 System memory remap 0x002 Table 6
PRESETCTRL R/W 0x004 Peripheral reset control 0x000 Table 7
SYSPLLCTRL R/W 0x008 System PLL control 0x000 Table 8
SYSPLLSTAT R 0x00C System PLL status 0x000 Table 9
- - 0x010 - 0x01C Reserved - -
SYSOSCCTRL R/W 0x020 System oscillator control 0x000 Table 10
WDTOSCCTRL R/W 0x024 Watchdog oscillator control 0x000 Table 11
IRCCTRL R/W 0x028 IRC control 0x080 Table 12
- - 0x02C Reserved - -

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Chapter 3: LPC1102 System configuration
SYSRSTSTAT R 0x030 System reset status register 0x000 Table 13
- - 0x034 - 0x03C Reserved - -
SYSPLLCLKSEL R/W 0x040 System PLL clock source select 0x000 Table 14
SYSPLLCLKUEN R/W 0x044 System PLL clock source update enable 0x000 Table 15
- - 0x048 - 0x06C Reserved - -
MAINCLKSEL R/W 0x070 Main clock source select 0x000 Table 16
MAINCLKUEN R/W 0x074 Main clock source update enable 0x000 Table 17
SYSAHBCLKDIV R/W 0x078 System AHB clock divider 0x001 Table 18
- - 0x07C Reserved - -
SYSAHBCLKCTRL R/W 0x080 System AHB clock control 0x85F Table 19
- - 0x084 - 0x090 Reserved - -
SSP0CLKDIV R/W 0x094 SPI0 clock divder 0x000 Table 20
UARTCLKDIV R/W 0x098 UART clock divder 0x000 Table 21
- - 0x09C Reserved - -
- - 0x0A0-0x0CC Reserved - -
WDTCLKSEL R/W 0x0D0 WDT clock source select 0x000 Table 22
WDTCLKUEN R/W 0x0D4 WDT clock source update enable 0x000 Table 23
WDTCLKDIV R/W 0x0D8 WDT clock divider 0x000 Table 24
- - 0x0DC Reserved - -
- - 0x0E0 Reserved - -
- - 0x0E4 Reserved - -
- - 0x0E8 Reserved - -
- - 0x0EC - 0x0FC Reserved - -
PIOPORCAP0 R 0x100 POR captured PIO status 0 user
dependent Table 25
- - 0x104 Reserved - -
- R 0x108 - 0x14C Reserved - -
BODCTRL R/W 0x150 BOD control 0x000 Table 26
SYSTCKCAL R/W 0x154 System tick counter calibration 0x004 Table 27
- - 0x158 - 0x1FC Reserved - -
STARTAPRP0 R/W 0x200 Start logic edge control register 0 Table 28
STARTERP0 R/W 0x204 Start logic signal enable register 0 Table 29
STARTRSRP0CLR W 0x208 Start logic reset register 0 n/a Table 30
STARTSRP0 R 0x20C Start logic status register 0 n/a Table 31
- - 0x210 - 0x22C Reserved - -
PDSLEEPCFG R/W 0x230 Power-down states in Deep-sleep mode 0x0000
0000 Table 33
PDAWAKECFG R/W 0x234 Power-down states after wake-up from
Deep-sleep mode 0x0000 EDF0 Table 34
Table 5. Register overview: system control block (base address 0x4004 8000) …continued
Name Access Address offset Description Reset
value Reference

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Chapter 3: LPC1102 System configuration
3.5.1 System memory remap register
The system memory remap register selects whether the ARM interrupt vectors are read
from the boot ROM, the flash, or the SRAM.
3.5.2 Peripheral reset control register
This register allows software to reset the SPI peripheral. Writing a 0 to the SSP0_RST_N
bit resets the SPI0 peripheral. Writing a 1 de-asserts the reset.
Remark: Before accessing the SPI peripheral, write a 1 to this register to ensure that the
reset signal to the SPI is de-asserted.
PDRUNCFG R/W 0x238 Power-down configuration register 0x0000
EDF0 Table 35
- - 0x23C - 0x3F0 Reserved - -
DEVICE_ID R 0x3F4 Device ID part
dependent Table 36
Table 5. Register overview: system control block (base address 0x4004 8000) …continued
Name Access Address offset Description Reset
value Reference
Table 6. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit
description
Bit Symbol Value Description Reset
value
1:0 MAP System memory remap 10
0x0 Boot Loader Mode. Interrupt vectors are re-mapped to Boot
ROM.
0x1 User RAM Mode. Interrupt vectors are re-mapped to Static
RAM.
0x2 User Flash Mode. Interrupt vectors are not re-mapped and
reside in Flash.
0x3 User Flash Mode. Interrupt vectors are not re-mapped and
reside in Flash.
31:2 - - Reserved 0x00
Table 7. Peripheral reset control register (PRESETCTRL, address 0x4004 8004) bit
description
Bit Symbol Value Description Reset
value
0 SSP0_RST_N SPI0 reset control 0
0 Resets the SPI0 peripheral.
1 SPI0 reset de-asserted.
31:1 - - Reserved 0x00

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Chapter 3: LPC1102 System configuration
3.5.3 System PLL control register
This register connects and enables the system PLL and configures the PLL multiplier and
divider values. The PLL accepts an input frequency from 10 MHz to 25 MHz from various
clock sources. The input frequency is multiplied up to a high frequency, then divided down
to provide the actual clock used by the CPU, peripherals, and memories. The PLL can
produce a clock up to the maximum allowed for the CPU.
3.5.4 System PLL status register
This register is a Read-only register and supplies the PLL lock status (see
Section 3.10.1).
3.5.5 System oscillator control register
This register configures the frequency range for the system oscillator.
Table 8. System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description
Bit Symbol Value Description Reset
value
4:0 MSEL Feedback divider value. The division value M is the
programmed MSEL value + 1.
00000: Division ratio M = 1
to
11111: Division ration M = 32
0x000
6:5 PSEL Post divider ratio P. The division ratio is 2 ×P. 0x00
0x0 P = 1
0x1 P = 2
0x2 P = 4
0x3 P = 8
31:7 - - Reserved. Do not write ones to reserved bits. 0x0
Table 9. System PLL status register (SYSPLLSTAT, address 0x4004 800C) bit description
Bit Symbol Value Description Reset
value
0 LOCK PLL lock status 0x0
0 PLL not locked
1 PLL locked
31:1 - - Reserved 0x00
Table 10. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit
description
Bit Symbol Value Description Reset
value
0 BYPASS Bypass system oscillator 0x0
0 Oscillator is not bypassed.
1 Bypass enabled. PLL input (sys_osc_clk) is fed
directly from the XTALIN pin.

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Chapter 3: LPC1102 System configuration
3.5.6 Watchdog oscillator control register
This register configures the watchdog oscillator. The oscillator consists of an analog and a
digital part. The analog part contains the oscillator function and generates an analog clock
(Fclkana). With the digital part, the analog output clock (Fclkana) can be divided to the
required output clock frequency wdt_osc_clk. The analog output frequency (Fclkana) can
be adjusted with the FREQSEL bits between 500 kHz and 3.4 MHz. With the digital part
Fclkana will be divided (divider ratios = 2, 4,...,64) to wdt_osc_clk using the DIVSEL bits.
The output clock frequency of the watchdog oscillator can be calculated as
wdt_osc_clk = Fclkana⁄(2 ×(1 + DIVSEL)) = 7.8 kHz to 1.7 MHz (nominal values).
Remark: Any setting of the FREQSEL bits will yield a Fclkana value within ±40% of the
listed frequency value. The watchdog oscillator is the clock source with the lowest power
consumption. If accurate timing is required, use the IRC or system oscillator.
Remark: The frequency of the watchdog oscillator is undefined after reset. The watchdog
oscillator frequency must be programmed by writing to the WDTOSCCTRL register before
using the watchdog oscillator.
1 FREQRANGE Determines frequency range for Low-power
oscillator. 0x0
0 1 - 20 MHz frequency range.
1 15 - 25 MHz frequency range
31:2 - - Reserved 0x00
Table 10. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit
description
Bit Symbol Value Description Reset
value
Table 11. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit
description
Bit Symbol Value Description Reset
value
4:0 DIVSEL Select divider for Fclkana.
wdt_osc_clk = Fclkana/ (2 ×(1 + DIVSEL))
00000: 2 ×(1 + DIVSEL) = 2
00001: 2 ×(1 + DIVSEL) = 4
to
11111: 2 ×(1 + DIVSEL) = 64
0x00

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Chapter 3: LPC1102 System configuration
3.5.7 Internal resonant crystal control register
This register is used to trim the on-chip 12 MHz oscillator. The trim value is factory-preset
and written by the boot code on start-up.
8:5 FREQSEL Select watchdog oscillator analog output frequency
(Fclkana). 0x00
0x1 0.5 MHz
0x2 0.8 MHz
0x3 1.1 MHz
0x4 1.4 MHz
0x5 1.6 MHz
0x6 1.8 MHz
0x7 2.0 MHz
0x8 2.2 MHz
0x9 2.4 MHz
0xA 2.6 MHz
0xB 2.7 MHz
0xC 2.9 MHz
0xD 3.1 MHz
0xE 3.2 MHz
0xF 3.4 MHz
31:9 - - Reserved 0x00
Table 11. Watchdog oscillator control register (WDTOSCCTRL, address 0x4004 8024) bit
description …continued
Bit Symbol Value Description Reset
value
Table 12. Internal resonant crystal control register (IRCCTRL, address 0x4004 8028) bit
description
Bit Symbol Value Description Reset value
7:0 TRIM Trim value 0x1000 0000,
then flash will
reprogram
31:9 - - Reserved 0x00

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Chapter 3: LPC1102 System configuration
3.5.8 System reset status register
if another reset signal - for example EXTRST - remains asserted after the POR signal is
negated, then its bit is set to detected.
3.5.9 System PLL clock source select register
This register selects the clock source for the system PLL. The SYSPLLCLKUEN register
(see Section 3.5.10) must be toggled from LOW to HIGH for the update to take effect.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Remark: When using the C_CAN controller with baudrates above 100 kbit/s, the system
oscillator must be selected.
Table 13. System reset status register (SYSRSTSTAT, address 0x4004 8030) bit description
Bit Symbol Value Description Reset
value
0 POR POR reset status 0x0
0 no POR detected
1 POR detected
1 EXTRST 0x0
0 no RESET event detected
1 RESET detected
2 WDT Status of the Watchdog reset 0x0
0 no WDT reset detected
1 WDT reset detected
3 BOD Status of the Brown-out detect reset 0x0
0 no BOD reset detected
1 BOD reset detected
4 SYSRST Status of the software system reset 0x0
0 no System reset detected
1 System reset detected
31:5 - - Reserved 0x00
Table 14. System PLL clock source select register (SYSPLLCLKSEL, address 0x4004 8040)
bit description
Bit Symbol Value Description Reset
value
1:0 SEL System PLL clock source 0x00
0x0 IRC oscillator
0x1 System oscillator
0x2 Reserved
0x3 Reserved
31:2 - - Reserved 0x00

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Chapter 3: LPC1102 System configuration
3.5.10 System PLL clock source update enable register
This register updates the clock source of the system PLL with the new input clock after the
SYSPLLCLKSEL register has been written to. In order for the update to take effect, first
write a zero to the SYSPLLUEN register and then write a one to SYSPLLUEN.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
3.5.11 Main clock source select register
This register selects the main system clock which can be either any input to the system
PLL, the output from the system PLL (sys_pllclkout), or the watchdog or IRC oscillators
directly. The main system clock clocks the core, the peripherals, and the memories.
The MAINCLKUEN register (see Section 3.5.12) must be toggled from LOW to HIGH for
the update to take effect.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Remark: When using the C_CAN controller with baudrates above 100 kbit/s, the system
oscillator must be selected.
3.5.12 Main clock source update enable register
This register updates the clock source of the main clock with the new input clock after the
MAINCLKSEL register has been written to. In order for the update to take effect, first write
a zero to the MAINCLKUEN register and then write a one to MAINCLKUEN.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
Table 15. System PLL clock source update enable register (SYSPLLUEN, address 0x4004
8044) bit description
Bit Symbol Value Description Reset value
0 ENA Enable system PLL clock source update 0x0
0 No change
1 Update clock source
31:1 - - Reserved 0x00
Table 16. Main clock source select register (MAINCLKSEL, address 0x4004 8070) bit
description
Bit Symbol Value Description Reset value
1:0 SEL Clock source for main clock 0x00
0x0 IRC oscillator
0x1 Input clock to system PLL
0x2 WDT oscillator
0x3 System PLL clock out
31:2 - - Reserved 0x00

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Chapter 3: LPC1102 System configuration
3.5.13 System AHB clock divider register
This register divides the main clock to provide the system clock to the core, memories,
and the peripherals. The system clock can be shut down completely by setting the DIV
bits to 0x0.
3.5.14 System AHB clock control register
The AHBCLKCTRL register enables the clocks to individual system and peripheral blocks.
The system clock (sys_ahb_clk[0], bit 0 in the AHBCLKCTRL register) provides the clock
for the AHB to APB bridge, the AHB matrix, the ARM Cortex-M0, the Syscon block, and
the PMU. This clock cannot be disabled.
Table 17. Main clock source update enable register (MAINCLKUEN, address 0x4004 8074)
bit description
Bit Symbol Value Description Reset value
0 ENA Enable main clock source update 0x0
0 No change
1 Update clock source
31:1 - - Reserved 0x00
Table 18. System AHB clock divider register (SYSAHBCLKDIV, address 0x4004 8078) bit
description
Bit Symbol Description Reset
value
7:0 DIV System AHB clock divider values
0: System clock disabled.
1: Divide by 1.
to
255: Divide by 255.
0x01
31:8 - Reserved 0x00
Table 19. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description
Bit Symbol Value Description Reset
value
0 SYS Enables clock for AHB to APB bridge, to the AHB
matrix, to the Cortex-M0 FCLK and HCLK, to the
SysCon, and to the PMU. This bit is read only.
1
0 Reserved
1 Enable
1 ROM Enables clock for ROM. 1
0 Disable
1 Enable
2 RAM Enables clock for RAM. 1
0 Disable
1 Enable

UM10429 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User manual Rev. 1 — 20 October 2010 19 of 258
NXP Semiconductors UM10429
Chapter 3: LPC1102 System configuration
3 FLASHREG Enables clock for flash register interface. 1
0 Disabled
1 Enabled
4 FLASHARRAY Enables clock for flash array access. 1
0 Disabled
1 Enabled
5- Reserved. 0
6 GPIO Enables clock for GPIO. 1
0 Disable
1 Enable
7 CT16B0 Enables clock for 16-bit counter/timer 0. 0
0 Disable
1 Enable
8 CT16B1 Enables clock for 16-bit counter/timer 1. 0
0 Disable
1 Enable
9 CT32B0 Enables clock for 32-bit counter/timer 0. 0
0 Disable
1 Enable
10 CT32B1 Enables clock for 32-bit counter/timer 1. 0
0 Disable
1 Enable
11 SSP0 Enables clock for SPI0. 1
0 Disable
1 Enable
12 UART Enables clock for UART. Note that the UART pins
must be configured in the IOCON block before the
UART clock can be enabled.
0
0 Disable
1 Enable
13 ADC Enables clock for ADC. 0
0 Disable
1 Enable
14 - Reserved 0
15 WDT Enables clock for WDT. 0
0 Disable
1 Enable
Table 19. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description …continued
Bit Symbol Value Description Reset
value

UM10429 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User manual Rev. 1 — 20 October 2010 20 of 258
NXP Semiconductors UM10429
Chapter 3: LPC1102 System configuration
3.5.15 SPI0 clock divider register
This register configures the SPI0 peripheral clock SPI0_PCLK. The SPI0_PCLK can be
shut down by setting the DIV bits to 0x0.
3.5.16 UART clock divider register
This register configures the UART peripheral clock UART_PCLK. The UART_PCLK can
be shut down by setting the DIV bits to 0x0.
Remark: Note that the UART pins must be configured in the IOCON block before the
UART clock can be enabled.
3.5.17 WDT clock source select register
This register selects the clock source for the watchdog timer. The WDTCLKUEN register
(see Section 3.5.18) must be toggled from LOW to HIGH for the update to take effect.
Remark: When switching clock sources, both clocks must be running before the clock
source is updated.
16 IOCON Enables clock for I/O configuration block. 0
0 Disable
1 Enable
31:17 - - Reserved 0x00
Table 19. System AHB clock control register (SYSAHBCLKCTRL, address 0x4004 8080) bit
description …continued
Bit Symbol Value Description Reset
value
Table 20. SPI0 clock divider register (SSP0CLKDIV, address 0x4004 8094) bit description
Bit Symbol Description Reset
value
7:0 DIV SPI0_PCLK clock divider values
0: Disable SPI0_PCLK.
1: Divide by 1.
to
255: Divide by 255.
0x00
31:8 - Reserved 0x00
Table 21. UART clock divider register (UARTCLKDIV, address 0x4004 8098) bit description
Bit Symbol Description Reset
value
7:0 DIV UART_PCLK clock divider values
0: Disable UART_PCLK.
1: Divide by 1.
to
255: Divide by 255.
0x00
31:8 - Reserved 0x00