NXP Semiconductors LPC1102 User manual

UM10429
LPC1102 User manual
Rev. 1 — 20 October 2010 User manual
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Keywords ARM Cortex-M0, LPC1102, LPC1102UK
Abstract LPC1102 User manual

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User manual Rev. 1 — 20 October 2010 2 of 258
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LPC1102 UM
Revision history
Rev Date Description
1 20101020 LPC1102 User manual

UM10429 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User manual Rev. 1 — 20 October 2010 3 of 258
1.1 Introduction
The LPC1102 is an ARM Cortex-M0 based, low-cost 32-bit MCU, designed for 8/16-bit
microcontroller applications, offering performance, low power, simple instruction set and
memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC1102 operates at CPU frequencies of up to 50 MHz.
The peripheral complement of the LPC1102 includes 32 kB of flash memory, 8 kB of data
memory, one RS-485/EIA-485 UART, one SPI interface with SSP features, four general
purpose counter/timers, a 10-bit ADC, and 11 general purpose I/O pins.
1.2 Features
•System:
–ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
–ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
–Serial Wire Debug.
–System tick timer.
•Memory:
–32 kB on-chip flash programming memory.
–8 kB SRAM.
–In-Application Programming (IAP) and In-System Programming (ISP) support via
on-chip bootloader software.
•Digital peripherals:
–11 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.
–GPIO pins can be used as edge and level sensitive interrupt sources.
–Four general purpose counter/timers with a total of one capture input and nine
match outputs.
–Programmable WatchDog Timer (WDT).
•Analog peripherals:
–10-bit ADC with input multiplexing among five pins.
UM10429
Chapter 1: LPC1102 Introductory information
Rev. 1 — 20 October 2010 User manual

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User manual Rev. 1 — 20 October 2010 4 of 258
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Chapter 1: LPC1102 Introductory information
•Serial interfaces:
–UART with fractional baud rate generation, internal FIFO, and RS-485 support.
–One SPI controller with SSP features and with FIFO and multi-protocol capabilities.
•Clock generation:
–12 MHz internal RC oscillator trimmed to 1% accuracy that can optionally be used
as a system clock.
–Programmable watchdog oscillator with a frequency range of 7.8 kHz to 1.8 MHz.
–PLL allows CPU operation up to the maximum CPU rate without the need for a
high-frequency crystal. May be run from an external clock or the internal RC
oscillator.
–Clock output function with divider that can reflect the external clock, IRC clock,
CPU clock, and the Watchdog clock.
•Power control:
–Integrated PMU (Power Management Unit) to minimize power consumption during
Sleep and Deep-sleep modes.
–Power profiles residing in boot ROM allowing to optimize performance and
minimize power consumption for any given application through one simple function
call.
–Two reduced power modes: Sleep and Deep-sleep modes.
–Processor wake-up from Deep-sleep mode via a dedicated start logic using up to
six of the functional pins.
–Power-On Reset (POR).
–Brownout detect with four separate thresholds for interrupt and forced reset.
•Unique device serial number for identification.
•Single 3.3 V power supply (1.8 V to 3.6 V).
•Available as WLCSP16 package.
1.3 Ordering information
Table 1. Ordering information
Type number Package
Name Description Version
LPC1102UK WLCSP16 wafer level chip-size package; 16 bumps; 2.17 ×2.32 ×0.6 mm -
Table 2. Ordering options
Type number Flash Total
SRAM UART I2C/ Fm+ SPI ADC channels Package
LPC1102UK 32 kB 8 kB 1 - 1 5 WLCSP16

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Chapter 1: LPC1102 Introductory information
1.4 Block diagram
Fig 1. LPC1102 Block diagram
SRAM
8 kB
ARM
CORTEX-M0
TEST/DEBUG
INTERFACE
FLASH
32 kB
HIGH-SPEED
GPIO
AHB TO APB
BRIDGE
CLOCK
GENERATION,
POWER CONTROL,
SYSTEM
FUNCTIONS
XTALIN
RESET
clocks and
controls
SWD
LPC1102
002aaf524
slave
slave
slave slave
ROM
slave
AHB-LITE BUS
GPIO port
PIO0/1
IRC
POR
SPI
10-bit ADC
UART
32-bit COUNTER/TIMER 0
WDT
IOCONFIG
CT32B0_MAT[3,1,0]
AD[4:0]
RXD
TXD
SYSTEM CONTROL
PMU
32-bit COUNTER/TIMER 1
CT32B1_MAT[2:0]
CT32B1_CAP0
16-bit COUNTER/TIMER 1
16-bit COUNTER/TIMER 0
CT16B0_MAT[2:0]
SCK, MISO,
MOSI
system bus

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User manual Rev. 1 — 20 October 2010 6 of 258
NXP Semiconductors UM10429
Chapter 1: LPC1102 Introductory information
1.5 ARM Cortex-M0 processor
The ARM Cortex-M0 processor is described in detail in Section 19.2 “About the
Cortex-M0 processor and core peripherals”. For the LPC1102, the ARM Cortex-M0
processor core is configured as follows:
•System options:
–The Nested Vectored Interrupt Controller (NVIC) is included and supports up to 32
interrupts.
–The system tick timer is included.
•Debug options: Serial Wire Debug is included with two watchpoints and four
breakpoints.

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User manual Rev. 1 — 20 October 2010 7 of 258
2.1 How to read this chapter
Table 3 shows the memory configuration for the LPC1102 part.
2.2 Memory map
Figure 2 shows the memory and peripheral address space of the LPC1102.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
On the LPC1102, the GPIO ports are the only AHB peripherals. The APB peripheral area
is 512 kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either
type is allocated 16 kB of space. This allows simplifying the address decoding for each
peripheral.
All peripheral register addresses are 32-bit word aligned regardless of their size. An
implication of this is that word and half-word registers must be accessed all at once. For
example, it is not possible to read or write the upper byte of a word register separately.
UM10429
Chapter 2: LPC1102 Memory mapping
Rev. 1 — 20 October 2010 User manual
Table 3. LPC1102 memory configuration
Part Flash SRAM
Suffix
LPC1102 32 kB 8 kB

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User manual Rev. 1 — 20 October 2010 8 of 258
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Chapter 2: LPC1102 Memory mapping
Fig 2. LPC1102 memory map
0x5000 0000
0x5001 0000
0x5002 0000
0x5020 0000
AHB peripherals
127 - 16 reserved
GPIO PIO1
7-4
0x5003 0000
0x5004 0000
reserved
reserved
11-8
15-12
GPIO PIO0
3-0
APB peripherals
0x4000 4000
0x4000 8000
0x4000 C000
0x4001 0000
0x4001 8000
0x4002 0000
0x4002 8000
0x4003 8000
0x4003 C000
0x4004 0000
0x4004 4000
0x4004 8000
0x4004 C000
0x4005 8000
0x4005 C000
0x4008 0000
0x4002 4000
0x4001 C000
0x4001 4000
0x4000 0000
WDT
32-bit counter/timer 0
32-bit counter/timer 1
ADC
UART
PMU
reserved
13 - 10 reserved
reserved
reserved
21 - 19 reserved
31 - 23 reserved
0
1
2
3
4
5
6
7
8
9
16
15
14
17
18
reserved
reserved
reserved
0x0000 0000
0 GB
0.5 GB
4 GB
1 GB
0x1000 2000
0x1FFF 0000
0x1FFF 4000
0x2000 0000
0x4000 0000
0x4008 0000
0x5000 0000
0x5020 0000
0xFFFF FFFF
reserved
reserved
reserved
APB peripherals
AHB peripherals
8 kB SRAM 0x1000 0000
LPC1102
0x0000 8000
32 kB on-chip flash
16 kB boot ROM
0x0000 0000
0x0000 00C0
active interrupt vectors
002aaf526
reserved
SPI
16-bit counter/timer 1
16-bit counter/timer 0
IOCONFIG
system control
22 reserved
flash controller
0xE000 0000
0xE010 0000
private peripheral bus

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User manual Rev. 1 — 20 October 2010 9 of 258
3.1 How to read this chapter
This chapter applies to part LPC1102.
3.2 Introduction
The system configuration block controls oscillators, start logic, and clock generation of the
LPC1102. Also included in this block are registers for setting the priority for AHB access
and a register for remapping flash, SRAM, and ROM memory areas.
3.3 Pin description
Table 4 shows pins that are associated with system control block functions.
3.4 Clocking and power control
See Figure 3 for an overview of the LPC1102 Clock Generation Unit (CGU).
The LPC1102 include three independent oscillators. These are the system oscillator, the
Internal RC oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for
more than one purpose as required in a particular application.
Following reset, the LPC1102 will operate from the Internal RC oscillator until switched by
software. This allows systems to operate without any external crystal and the bootloader
code to operate at a known frequency.
The SYSAHBCLKCTRL register gates the system clock to the various peripherals and
memories. UART, the WDT, and SPI0 have individual clock dividers to derive peripheral
clocks from the main clock.
For details on power control see Section 3.8.
UM10429
Chapter 3: LPC1102 System configuration
Rev. 1 — 20 October 2010 User manual
Table 4. Pin summary
Pin name Pin direction Pin description
PIO0_0; PIO0_8 to PIO0_11 I Start logic wake-up pins port 0
PIO1_0 I Start logic wake-up pin port 1

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User manual Rev. 1 — 20 October 2010 10 of 258
NXP Semiconductors UM10429
Chapter 3: LPC1102 System configuration
3.5 Register description
All registers, regardless of size, are on word address boundaries. Details of the registers
appear in the description of each function.
See Section 3.11 for the flash access timing register, which can be re-configured as part
the system setup. This register is not part of the system configuration block.
Fig 3. LPC1102 CGU block diagram
SYSTEM PLL
IRC oscillator
system oscillator watchdog oscillator
IRC oscillator
watchdog oscillator
MAINCLKSEL
(main clock select)
SYSPLLCLKSEL
(system PLL clock select)
SYSTEM CLOCK
DIVIDER
AHB clock 0
(system)
AHBCLKCTRL[1:18]
SPI0 PERIPHERAL
CLOCK DIVIDER SPI0_PCLK
UART PERIPHERAL
CLOCK DIVIDER UART_PCLK
WDT CLOCK
DIVIDER WDT_PCLK
WDTUEN
(WDT clock update enable)
main clock
system clock
IRC oscillator
AHB clocks
1 to 18
(memories
and peripherals)
18
sys_pllclkout
sys_pllclkin
Table 5. Register overview: system control block (base address 0x4004 8000)
Name Access Address offset Description Reset
value Reference
SYSMEMREMAP R/W 0x000 System memory remap 0x002 Table 6
PRESETCTRL R/W 0x004 Peripheral reset control 0x000 Table 7
SYSPLLCTRL R/W 0x008 System PLL control 0x000 Table 8
SYSPLLSTAT R 0x00C System PLL status 0x000 Table 9
- - 0x010 - 0x01C Reserved - -
SYSOSCCTRL R/W 0x020 System oscillator control 0x000 Table 10
WDTOSCCTRL R/W 0x024 Watchdog oscillator control 0x000 Table 11
IRCCTRL R/W 0x028 IRC control 0x080 Table 12
- - 0x02C Reserved - -