NXP Semiconductors ADC1610S Series User manual

Quick start ADC1610S series
(F1 or F2 versions)
Demonstration board for ADC1610S series
Rev. 5 —
January 2011
Document information
Info
Keywords
Abstract
Overview
Quick start ADC1610S series
(F1 or F2 versions)
Demonstration board for ADC1610S series
January 2011
Document information
Content
PCB2131-1, Demonstration board, ADC, Converter
This document describes how to use the demonstration board for the
analog-to-digital converter ADC1610Sseries.
Quick start ADC1610S series
Quick start
This document describes how to use the demonstration board for the

NXP Semiconductors
Quick start ADC1610S series (F1 or F2 versions)
Quick start
Revision history
Rev Date Description
1 20081001 Initial version.
2 20090518 Update
3 20090610 Add SPI software description.
4 20100519 Add HSDC extension module acquisition system description.
5 20110120 Update with latest software tool.

NXP Semiconductors
Quick start
Quick start ADC1610S series (F1 or F2 versions)
Quick start
Rev. 5 — January 2011
3 of
28
1. Overview of the ADC1610S demo board
1.1 ADC1610S F1 series (CMOS digital outputs)
Figure below presents the connections to measure ADC1610S.
Fig 1. 1.1 ADC1610S setup
Register
programming
USB
SPI
DC adaptor
connected to
mains
LOGIC ANALYZER
Output data
. DO (LSB) to Dxx
(MSB) . DAV for
synchro
. OTR Out of range
P
RESENTED CONFIGURATION
. 2V
pp
input full scale
. Single Sine wave clock signal
. Input common mode from IC
. Binary ADC output
. SPI Mode
SYNTHESIZED
SIGNAL
GENERATOR
C
LOCK SIGNAL
. Sine wave
. AC
I
NPUT SIGNAL
. 2V
pp
sine wave
. AC
SYNTHESIZED
SIGNAL
GENERATOR
F
ILTER
. High-order
. Band pass

Quick start
Rev. 5 — January 2011
4 of
28
1.2 ADC1610S F2
series (LVDS/DDR digital outputs)
Figure below presents the co
nnections to measure ADC
Fig 2. ADC1610S setup
C
LOCK SIGNAL
. Sine wave
. AC
SYNTHESIZED
SIGNAL
GENERATOR
USB
SPI
Register
programming
I
NPUT SIGNAL
. 2V
pp
sine wave
. AC
SYNTHESIZED
SIGNAL
GENERATOR
F
ILTER
. High-order
. Band pass
series (LVDS/DDR digital outputs)
nnections to measure ADC
1610S.
P
RESENTED CONFIGURATI
. 2V
pp
input full scale
. Single Sine wave clock signal
. Input common mode from IC
. Binary ADC output
. SPI Mode
EXTENTION
MODULE
Data Acquisition
Optional module +
bridge
programming
DC adaptor
connected to
mains
NXP Semiconductors
Quick start
Quick start ADC1610S series (F1 or F2 versions)
RESENTED CONFIGURATI
ON
input full scale
. Single Sine wave clock signal
. Input common mode from IC
. Binary ADC output
. SPI Mode
EXTENTION
MODULE
Data Acquisition
Optional module +
bridge

NXP Semiconductors
Quick start
1.3 Power supply
The board is powered either with a 3 V
adaptor.
Table 1. Power supply
Name Function
J8 2.1 Jack connector – 5VDC
C
hange ST9 and ST10 position accordingly
J10 +3V green connector –
Power supply 3 V
J11
Change ST9 and ST10 position accordingly
CMOS version
+1.8V green connector –
Power supply 1.8 V
LVDS DDR version
+3V green connector –
Power supply
TP1 GND test point
TP2 GND test point
1.4
Input signals (IN, CLK)
The input clock signal can be either a sine wave or a LVCMOS signal.
To ensure a good evaluation of the device, the input signal and the input clock must be
synchronized toge
Moreover, the input frequency (Fi, MHz) and the clock frequency (Fclk, Msps) should
follow the formula:
, where M is an odd number of period and N is the number of samples.
Quick start ADC1610S series (F1 or F2 versions)
Rev. 5 — January 2011
The board is powered either with a 3 V
DC
and 1.8/3 V
DC
power supplies or a 5V DC
View
hange ST9 and ST10 position accordingly
Power supply 3 V
DC
Change ST9 and ST10 position accordingly
Power supply 1.8 V
DC
Power supply
1.8 V
DC
Input signals (IN, CLK)
The input clock signal can be either a sine wave or a LVCMOS signal.
To ensure a good evaluation of the device, the input signal and the input clock must be
synchronized toge
ther.
Moreover, the input frequency (Fi, MHz) and the clock frequency (Fclk, Msps) should
follow the formula:
, where M is an odd number of period and N is the number of samples.
J10 / J11
TP2
ST9/10
Quick start ADC1610S series (F1 or F2 versions)
Quick start
© NXP B.V. 2011. All rights reserved.© NXP B.V. 2011. All rights reserved.
5 of 28
power supplies or a 5V DC
The input clock signal can be either a sine wave or a LVCMOS signal.
To ensure a good evaluation of the device, the input signal and the input clock must be
Moreover, the input frequency (Fi, MHz) and the clock frequency (Fclk, Msps) should
, where M is an odd number of period and N is the number of samples.
J8
TP1
ST9/10

NXP Semiconductors
Quick start ADC1610S series (F1 or F2 versions)
Quick start
© NXP B.V. 2011. All rights reserved. © NXP B.V. 2011. All rights reserved.
Quick start Rev. 5 — January 2011 6 of 28
Table 2. Input signals
Name Function View
J1 IN connector – Analog input signal (
50
Ω
matching)
J2 CLKP connector – Single ended clock input signal (
50
Ω
matching), with a transformer.
J3 CLKM connector – Grounded on that demoboard
1.5 Output signals in CMOS version (D0 to D15, DAV, OTR)
The digital output signal is available in binary, 2’s complement or gray format.
A Data Valid Output clock (DAV) is provided by the device for the data acquisition.
Table 3. Output signals
Name Function View
J6 Array connector – ADC digital output (D0 to D15), OTR
and Data Valid (DAV)
J6
J1
J2
J3

NXP Semiconductors
Quick start ADC1610S series (F1 or F2 versions)
Quick start
© NXP B.V. 2011. All rights reserved. © NXP B.V. 2011. All rights reserved.
Quick start Rev. 5 — January 2011 7 of 28
1.6 Output signals in LVDS DDR version
The digital output signal is available in binary, 2’s complement or gray format.
A Data Valid Output clock (DAV) is provided by the device for the data acquisition.
Table 4. Output signals
Name Function View
J7 Samtec QTH connector – ADC digital output (D0 to D15)
and Data Valid (DAV)
J7

NXP Semiconductors
Quick start ADC1610S series (F1 or F2 versions)
Quick start
© NXP B.V. 2011. All rights reserved. © NXP B.V. 2011. All rights reserved.
Quick start Rev. 5 — January 2011 8 of 28
1.7 SPI Mode
The ADC1610S can be controlled either by a Serial Peripheral Interface (SPI) or by PIN.
Table 5. SPI Interface
Name Function View
J12 USB connector – SPI interface
1.8 SPI program
For more details on how to control device with SPI, refer to section 3.3.
J12

NXP Semiconductors
Quick start
Quick start ADC1610S series (F1 or F2 versions)
Quick start
Rev. 5 — January 2011
9 of
28
2. HSDC extension module: acquisition board
The figure 4 shows an overview of the extension module HSDC-EXTMOD01/DB acquisition board:
Fig 3. HSDC extension module: acquisition board
+5V
P
OWER SUPPLY
. I = 3.2 A
R
EFERENCE SIGNAL
. Typical 10 MHz
SIGNAL
GENERATOR
USB
SPI
MODULE
P
RESENTED CONFIGURATION
. Acquisition board
. External reference signal
. LVDS DDR 16-bit input stream
. CMOS 2 16-bit channels input
LVDS
DDR
I/O
CONNECTOR
. Up to 325 MHz 16-bit LVDS DDR
CMOS
I/O
CONNECTOR
. 2 channels up to 200 MHz 16-bit
J
UMPER FOR
I/O
SUPPLY
. Define either I/O is 1.8 V or 3.3 V
RED LED
FOR POWER
SUPPLY CONNECTION
RED LED
FOR
+3V3
POWER
RED LED
FOR
USB
CONNECTION
GREEN LED FOR
EMBEDDED
PLL LOCK STATUS
FLASHING RED
FOR
FPGA STATUS

NXP Semiconductors
Quick start ADC1610S series (F1 or F2 versions)
Quick start
© NXP B.V. 2011. All rights reserved.
Quick start Rev. 5 — January 2011 10 of 28
The HSDC extension module is intended for acquisition/generation and clock generation
purpose. When connected to an ADC demo-board it is intended as an acquisition system
for digital output bits delivered by ADC, either CMOS (HE14 P1 connector) or LVDS DDR
(SAMTEC QTH_060_02 P2 connector).
The board brief specification is shown below:
•32 MB memory size for acquisition pattern;
•2 16-bit channels CMOS up to 200 MHz;
•16-bit LVDS DDR input data stream up to 320 MHz;
•On-board or external reference for signal generation.
In this section the specific requirement for the use with ADC1610S demo-board will be
shown.
For more details on the HSDC-EXTMOD01/DB, please contact dataconverter-
[e-mail].
2.1 HSDC extension module: hardware initialization
Before using the generation board, make sure that you connect the USB cable prior to
the supply.
When USB and power cable are connected, the HSDC-EXTMOD will light 3 red LEDs.
The green LED close to the PLL is only when it is locked (see section 3.3).
The red LED close to FPGA reports normal behavior when flashing ¼ on, ¾ off. Any
other flashing behavior reports a failure at initialization (see section 3.3).
2.2 HSDC extension module: CMOS connector description
The figure 5 shows a brief description of the hardware connection on the HE14
connector.
For proper use of the acquisition board, make sure that resistor R86 (0 Ω) is connected
while R84 is removed.

NXP Semiconductors
Quick start ADC1610S series (F1 or F2 versions)
Quick start
© NXP B.V. 2011. All rights reserved.
Quick start Rev. 5 — January 2011 11 of 28
Fig 4. HSDC extension module: HE14 CMOS hardware schematic overview

NXP Semiconductors
Quick sta
rt
Quick start ADC1610S series (F1 or F2 versions)
Quick start
Rev. 5 — January 2011
12 of
28
3. Combo 1610S and HSDC extension module
3.1 ADC1610S setup CMOS outputs
The figure 24 below shows an overview of the whole system ADC1610S+HSDC extension module with CMOS outputs configuration for which
connection is straightforward, together with a supply extension module (release A) for the ADC1610S demo-board:
Fig 5. Evaluation set-up measurement with ADC1610S CMOS and HSDC extension module
USB
SPI
MODULE
P
RESENTED CONFIGURATION
. Single-ended clock on CLKP
. 2V
pp
input full scale
. Binary CMOS outputs
C
LOCK SIGNAL
. E.g. 122.88MHz
CLOCK
GENERATOR
R
EFERENCE SIGNAL
. E.g. 170MHz
SIGNAL
GENERATOR
+5V
POWER SUPPLY
. I = 3.2A
USB
SPI
MODULE
+5V
POWER SUPPLY
. I = 3.2A

NXP Semiconductors
Quick sta
rt
Quick start ADC1610S series (F1 or F2 versions)
Quick start
Rev. 5 — January 2011
13 of
28
3.2 ADC1610S setup LVDS/DDR outputs
The figure 24 below shows an overview of the whole system ADC1610S+HSDC extension module with CMOS outputs configuration for which
connection is straightforward, together with a supply extension module (release A) for the ADC1610S demo-board:
Fig 6. Evaluation set-up measurement with ADC1610S CMOS and HSDC extension module
USB
SPI
MODULE
P
RESENTED CONFIGURATION
. Single-ended clock on CLKP
. 2V
pp
input full scale
. Binary CMOS outputs
C
LOCK SIGNAL
. E.g. 122.88MHz
CLOCK
GENERATOR
R
EFERENCE SIGNAL
. E.g. 170MHz
SIGNAL
GENERATOR
+5V
POWER
SUPPLY
. I =
3.2
A
USB
SPI
MODULE
+5V
POWER SUPPLY
. I = 3.2A

NXP Semiconductors
Quick start ADC1610S series (F1 or F2 versions)
Quick start
© NXP B.V. 2011. All rights reserved.
Quick start Rev. 5 — January 2011 14 of 28
3.3 ADC Software tool
Run the application “SW_ADC_1_r02.exe”. This application will allow:
•the user to control features on our high speed ADC through the SPI interface available on any
ADC1610S series;
•As well as performing any online data acquisition to evaluate the performances of the
ADC1610S series.
At start-up, the program will detect any board connected to your system and display information as
can be seen on following window:
Fig 7. SW_ADC_1_r02: start-up screen
: “NXP Banner Button” will display your default internet browser to the NXP data converter home
page;
: “REFRESH” allows you to poll your system for any hardware change. It will reset any board
connected to your system;
: “QUIT” allows you quit the application;
: “INITIALIZATION” allow you to initialize the HSDC-EXTMOD board prior to any acquisition task.
In the example above, the HSDC-EXTMOD has been detected, as well as ADC1610S125.
At this moment, make sure that 4 LEDs are visible on the HSDC-EXTMOD (2 close to power plug,
1 for USB and 1 close to FPGA).
The “Info” page gives more details on the current hardware configuration for the HSDC-EXTMOD
board:





NXP Semiconductors
Quick start ADC1610S series (F1 or F2 versions)
Quick start
© NXP B.V. 2011. All rights reserved.
Quick start Rev. 5 — January 2011 15 of 28
Fig 8. SW_ADC_1_r02: “Info” page
The HSDC-EXTMOD is not yet initialized, so the embedded PLL (LMK03001 in this example) is not
locked. Initialization is only required for acquisition purpose.

NXP Semiconductors
Quick start ADC1610S series (F1 or F2 versions)
Quick start
© NXP B.V. 2011. All rights reserved.
Quick start Rev. 5 — January 2011 16 of 28
3.3.1 ADC SPI programming Functional Registers page
The page displays all SPI registers for ADC1610S series:
Fig 9. SW_ADC_1_r02: “ADC - Functional Registers” page
Perform any settings and then click on the “Send data to device” button to update the device
registers.

NXP Semiconductors
Quick start ADC1610S series (F1 or F2 versions)
Quick start
© NXP B.V. 2011. All rights reserved.
Quick start Rev. 5 — January 2011 17 of 28
3.3.2 ADC SPI programming Read Registers page
This page can be used to read all registers by clicking on the “Read all registers” button and will
display the result in the table below:
Fig 10. SW_ADC_1_r02: “ADC - Read Registers” page
When all registers have been read, it is possible to save the data to a text file. The settings are
saved in a table-like format as shown below:
Table 6. Typical saving on text file
Content of file is shown as table format
Column 1 Column 2
Address Value
05 00
06 01
08 00
10 03
11 00
12 09
13 00
14 00
15 00
16 00
17 00

NXP Semiconductors
Quick start ADC1610S series (F1 or F2 versions)
Quick start
© NXP B.V. 2011. All rights reserved.
Quick start Rev. 5 — January 2011 18 of 28
Column 1 Column 2
20 0e
21 00
22 00
Note that all data are saved in hexadecimal format.
Click on the “Save registers read to file” button to select the file to store data to. Make sure that you
store your file with “.txt” extension, this will allow you to re-use the file on the “ADC - Load
Registers” page.
3.3.3 ADC SPI programming Load Registers page
This page allows downloading configuration data to the device registers:
It is not necessary to have a file that has the whole set of registers listed. The only restriction is
regarding the formatting of the file as given in section 3.3.2.
Note: this page cannot be used to download data saved during the comparison process.
To download settings onto device registers, follow the procedure below:
•Browse to select your file (button );
•Click on “Load data” button.
A message on field and a progress bar will inform about the status of the operation until
message “download done!” is seen. The table is updated with the current values downloaded at
the fly as can be seen on figure 13.
Fig 11. SW_ADC_1_r02: “ADC - Load Registers” page





NXP Semiconductors
Quick start ADC1610S series (F1 or F2 versions)
Quick start
© NXP B.V. 2011. All rights reserved.
Quick start Rev. 5 — January 2011 19 of 28
3.3.4 Tools page
This page allows the user to calculate the coherent frequencies values involved of the acquisition
process. It gives an indication where the 6 first harmonics are located in the Nyquist zone.
Enter your analog and sampling frequencies in field.Indicate the number of samples to be
acquired, as well as the fixed parameter for the coherency calculation (Fs in our example
above). Press “UPDATE GRAPH” to look at the frequency plan, it gives also the real Fin
frequency (Refer to appendix A.1 for more details on coherency calculation):
Fig 12. SW_ADC_1_r02: “Tools” page
Note: The level of the harmonics shown does not reproduce the behavior of the ADC; they are only
given as indication for location.




NXP Semiconductors
Quick start ADC1610S series (F1 or F2 versions)
Quick start
© NXP B.V. 2011. All rights reserved.
Quick start Rev. 5 — January 2011 20 of 28
3.3.5 Acquisition page
This page will acquire data to evaluate the high dynamic performance of the device:
Fig 13. SW_ADC_1_r02: “Acquisition” page
Before proceeding to any acquisition, the user needs to do the following entries:
•the sampling frequency Fs: 122.88 Msps in our example (field );
•the input frequency Fin: 5 MHz in our example (field );
•the number of samples to be acquired 65536 in our example (field );
•indicate whether it is CMOS or LVDS DDR (field );
•Press the “INITIALIZATION” button. It will initialized the HSDC-EXTMOD board:
−FPGA is ready (red LED is flashing ¼ on and ¾ off) ;
−PLL embedded is locked (green LED is on);
•indicate whether Fin or Fs are coherent or not (field ):
−if signals are coherent, selected which Fin or Fs are fixed for the calculation (see appendix
A.1);
−If signals are not coherent, select the window for FFT processing to apply (the Blackman
window gives better results).
•Press the “ACQUIRE” button to display the results from the FFT processing. The results
fields will be updated automatically.
•press “STOP” button to stop acquisition;
•field allows to do FFT averaging over up to 255 trials, suitable for small signal analysis;
•Field allows storing dynamic results to text file. Click on the check box, enter a header as a
comment and browse to indicate where to store data file. Table 7 shows how data are stored:








