NXP Semiconductors HCS12 User manual

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USB2.0 to ATA/ATAPI Bridge
Designer Reference Manual
DRM062
Rev. 0
1/2005

USB2.0 to ATA/ATAPI Bridge Designer Reference Manual, Rev. 0
Freescale Semiconductor 3
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
USB2.0 to ATA/ATATPI Bridge
Designer Reference Manual
by: Dennis Lui and Derek Lau
Applications Engineering
Microcontroller Division
Hong Kong
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://www.freescale.com

Revision History
USB2.0 to ATA/ATAPI Bridge Designer Reference Manual, Rev. 0
4Freescale Semiconductor
The following revision history table summarizes changes contained in this document. For your
convenience, the page number designators have been linked to the appropriate location.
Revision History
Date Revision
Level Description Page Number(s)
Jan 2005 0 Initial release N/A

USB2.0 to ATA/ATAPI Bridge Designer Reference Manual, Rev. 0
Freescale Semiconductor 5
Table of Contents
Chapter 1
System Overview
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 MC9S12UF32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2
Hardware Overview
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Hardware Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 Voltage Regulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Background Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.5 USB Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.6 ATA Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Chapter 3
Software Overview
3.1 System Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1.1 Main Program. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.2 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1.3 USB Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Chapter 4
USB Module
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Endpoints Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Chapter 5
IQUEUE Module
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.2 IQUEUE Request Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Chapter 6
ATA Module
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2 ATA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2.1 Write to ATA Device Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2.2 Read from ATA Device Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table of Contents
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Chapter 7
USB Mass Storage Interface Driver
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2 USB Mass Storage Class Bulk-Only Transport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.2.1 USB Command Block Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
7.2.2 USB Command Status Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2.3 SCSI Command Descriptor Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2.4 Example of Command Block Wrapper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.3 Driver Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.3.1 Handling of USB Command Block Wrapper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.3.1.1 Commands Without Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.3.1.2 Host Sends out Data to Storage Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.3.1.3 Host Receives Data from Storage Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.3.2 Class Specific Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Chapter 8
ATA/ATAPI Driver
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2 ATA and ATAPI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.3 Software Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.3.1 Commands Without Data Transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.3.2 Host Sends out Data to ATA/ATAPI Device. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.3.3 Host Receives Data from ATA/ATAPI Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.3.4 Individual Software Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Chapter 9
Test and Customization
9.1 Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.2 Customization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.2.1 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.2.1.1 Self-powered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.2.1.2 Bus-powered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.2.1.3 Amadeus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
9.2.2 Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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Chapter 1
System Overview
1.1 Introduction
This manual describes a reference design of a Universal Serial Bus (USB) 2.0 to ATA/ATAPI Bridge
solution by using the MC9S12UF32 microcontroller.
Since the MC9S12UF32 is a highly integrated USB 2.0 high speed device for mass storage applications,
the system consists of the MC9S12UF32 and passive components only. All hardware schematic
diagrams and most firmware source codes are available as reference materials.
1.2 System Features
• USB 2.0 High Speed and Full Speed compliance
• Windows 98 SE, Windows 2000, and Windows XP Compatible
• Supports ATA/ATAPI devices higher than 137G bytes capacity
• Supports PIO mode 0 to 4
• Supports UMDA mode 0 to 4
• Maximum 60M bytes per second burst transfer rate
• In-circuit evaluation and programming
1.3 MC9S12UF32
The MC9S12UF32 microcontroller (hereafter referred as UF32) features an integrated Universal Serial
Bus (USB) 2.0 controller and physical layer transceivers to provide comprehensive USB specification
implementation for both high-speed (480 Mbps) and full-speed (12 Mbps) operations. The high-speed
operation, running at bus speeds of 30 MHz, implements fast large data transfers for applications such
as real-time movies that were impractical at the previous lower-speed operation.
Besides standard USB functionality, the UF32 enables control of external harddisk drives, CD-ROM and
DVD-ROM drives. The UF32 also enables controls of different common Flash memory devices such as
CompactFlash, Secure Digital, MultiMediaCards, SmartMedia, and Memory Stick memory cards.
The availability of up to 75 programmable I/O lines helps to minimize the system costs and enhance
flexibility.
The UF32 is designed to reduce overall system components count and improves performance by
off-loading peripheral overhead functions from the CPU. The on-board Flash enables the peripheral
system to accommodate future software changes. The UF32 can be used in card readers for popular
Flash memory cards, ATA/ATAPI bridges for external hard disks and DVD ROM, USB Flash disks and
digital wallets.
There are 100 pins and 64 pins options for the UF32. The 100 pin device is designed for card reader and
digital wallet applications while the 64 pin device is designed for ATA/ATAPI bridge with SD or USB Flash
disk with SD and MS, and other USB applications that do not require so many I/O pins.

System Overview
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MC9S12UF32 features:
• HCS12 CPU core
• 32K bytes Flash, 3.5K bytes RAM, 1.5K bytes Queue-RAM
• Universal Serial Bus 2.0 controller and transceivers
• Integrated Queue controller
• ATA/ATAPI controller
• CompactFlash controller
• Secure Digit and MultiMediaCards controller
• SmartMedia and NAND Flash controller
• Memory Stick controller
• 8-channel, 16-bit timer
• Serial communications interface
1.4 System Overview
Figure 1-1. Block Diagram of USB2.0 to ATA/ATAPI Bridge
Since UF32 is a highly integrated USB 2.0 high speed device with embedded ATA controller, the system
consists of the UF32 and passive components only.
Standard ATA (IDE) Interface
USB SIE 9S12UF32
ATA/ATAPI Device
(Harddisk, CDR, CDRW, DVDR, DVDRW...)
To PC System

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Chapter 2
Hardware Overview
2.1 Introduction
The system consists of the 64 pin package UF32 and passive components only. The major external
component is an MOSFET used for 5V to 3.3V voltage regulation. There are two reference demo boards
available: one is USB bus powered for 2.5" hard disk use, another is self-powered for 3.5" hard disk and
ATAPI devices use.
Figure 2-1. USB Bus Powered Demo Board
Figure 2-2. Self-Powered Demo Board

Hardware Overview
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2.2 Hardware Functions
Figure 2-3. Hardware Functions
The hardware functions can be divided into the following parts:
• Voltage regulation
• Background debug interface
• USB interface
• ATA interface
2.3 Voltage Regulation
The UF32 is designed for a single 5V voltage input. There are three kinds of I/Os:
• Port E of 5V I/Os
• Port J, M, and Q of 5V or 3.3V I/O powered by VDD3X
• Port A, B, S, T, and U of 5V or 3.3V I/O powered by VDDX
However, for UF32 to be used in ATA applications VDD3X and VDDX must be with 3.3V, hence, only the
port E is with 5V I/Os while the others are with 3.3V I/Os.
The UF32 has four built-in voltage regulators:
• 3.3V regulator for USB transceiver and PLL use
• 3.3V regulator (with a required external MOSFET) for I/O use
• 2.5V regulator for S12 CPU core use
• 2.5V regulator for USB transceiver use
The UF32 needs 5V power supplied to VDDR. The external MOSFET is regulated by the UF32 to provide
3.3V supply to VDD3X and VDDX. The USB transceivers and PLL are powered by the internal 3.3V
regulator and the S12 CPU core is powered by the internal 2.5V regulator.
PORTE
PORTM
PORTJ
PORTQ
PORTT
PORTU
PORTS
PORTB
PORTA
BDM
USB
ATA
CORE
USB
REG
5V 3V
2.5V
3V
5V
5V / 3.3V
3V
VDDA
VDDR
REF3V
VDD3X
VDDX
VDD Core
BKGD
USB Power
CS0–1, IOWR
DA0–2, IORD, DMACK
RESET
IORDY
DMARQ, INTRQ
D0–D7
D8–D15
MC9S12UF32
3V
5V
2.5V

Background Debug Interface
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2.4 Background Debug Interface
The single-wired background debug pin BKGD is used for software development and programming.
2.5 USB Interface
The UF32 features an integrated Universal Serial Bus (USB) 2.0 controller and physical layer
transceivers. An external 1.5kΩpullup resistor, 510Ωreference resistor, and four serial resistors are
required for USB connection. The USB power detection is used for self-powered system only.
2.6 ATA Interface
A standard 40 pin ATA connector is used. Only pullup, pulldown and serial termination resistors are
needed to connect the UF32 to the ATA device. The ATA CSEL pin is shorted to ground and the firmware
has fixed the device to be master, therefore the ATA/ATAPI device must be set for the option of either
master or cable select.

Hardware Overview
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Chapter 3
Software Overview
3.1 System Software Architecture
Figure 3-1. System Software Architecture
Figure 3-1 shows the system software architecture for the UF32 ATA/ATAPI Bridge. The mini-kernel is
designed for multi-tasks operation. In this application, it mainly handles the USB event tasks and the timer
hook function tasks after system initialization. The initialization subroutines initializes the modules of
timer, voltage regulator, ATA controller, IQUEUE RAM, IQUEUE, and USB controller. The main program
continually checks and serves different event tasks.
Mini-Kernel
for UF32 MCU Resources (Timer, IRQ...)
Interface Module
Memory Device Mass
Storage
Device
(Protocol Adapter)
Application Task
SCSI Command Module
USB Mass Storage
USB Protocol Layer

Software Overview
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Figure 3-2. Main Software Flow
3.1.1 Main Program
The USB events handler puts the UF32 into suspend when USB bus suspend is detected. The USB Mass
Storage (USBMS) handler calls corresponding routines for different USBMS commands. Other
application events handlers can be added to the main program.
3.1.2 Timer Interrupt
A 1ms timer interrupt is set. It will check if there is any timer hook functions and serve them. There are
two timer hook functions: one is a 10ms hook function to check the USB bus power, another is a 1s hook
function to check the ATA process time out. The 10ms hook function means it will be served for every
10ms which is registered in the initialization routine.
3.1.3 USB Interrupts
There are three kinds of USB interrupts:
• Interrupts for the control Endpoint 0
• Interrupts for the Bulk IN Endpoint
• Interrupts for the Bulk OUT Endpoint
All of the interrupt events are fully handled in the interrupt routines excepts the following interrupts:
• USB suspend
• USB Mass Storage reset
• USB Mass Storage Command Block Wrapper received
The above 3 interrupt routines set some flags to indicate their presence and will then be served in the
main routine.
MAIN PROGRAM
INITIALIZATION
USB EVENTS
TIMER INTERRUPT
CHECK AND SERVE
RETURN
INCREASE GLOBAL TIMER
COUNTER FOR EVERY 1ms
USBMS EVENTS
OTHER APPLICATOIN
HANDLER
USB INTERRUPTS
USB ENDPOINT 0
HANDLER
USBMS BULK OUT
RETURN
USBMS BULK IN
HANDLER
HANDLER
ANY HOOK FUNCTION
HANDLER
EVENTS HANDLERS

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Chapter 4
USB Module
4.1 Introduction
The USB module consists of an integrated Universal Serial Bus (USB) 2.0 controller and physical layer
transceivers to provide comprehensive USB specification implementation for both high-speed (480 Mbps)
and full-speed (12 Mbps) operations.
4.2 Endpoints Configurations
Table 4-1 shows the endpoints configurations. The physical Endpoint 0 and Endpoint 1 are mapped to
logical control Endpoint 0. The physical Endpoints 2 to 5 can be mapped to logical Endpoints 1 to 3.
However, only one logical endpoint can be mapped to the logical endpoint 3. The USB host only sees the
logical Endpoints.
The maximum buffer sizes of the Endpoints 4 and 5 are 64 bytes (full-speed) or 512 bytes (high-speed).
IQUEUE RAM is used as the buffers for these two endpoints. The other endpoints are associated with
dedicated 64 bytes of buffers.
In this application, only the control Endpoints and the physical Endpoints 4 and 5 are used.
Table 4-1. Endpoints Configurations
Physical
Endpoint
Logical
Endpoint
Transfer
Mode
Transfer
Type
Maximum Buffer
Size
0 0 SETUP CONTROL 64
10IN CONTROL 64
0OUT CONTROL 64
21 – 3 IN / OUT BULK / INT 64
31 – 3 IN / OUT BULK / INT 64
41 – 3 OUT ISO / BULK / INT 64 / 512
51 – 3 IN BULK / INT 64 / 512

USB Module
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Chapter 5
IQUEUE Module
5.1 Introduction
The Intelligent Queue (IQUEUE) module allows automatic data transfer between the USB module and
IQUEUE RAM, and between IQUEUE RAM and mass storage devices without CPU intervention. The
IQUEUE RAM is configured to address $2000 to $25FF by writing 0x21 to the INITEE register.
Figure 5-1. IQUEUE Module
S12 CPU
USB
ATA/ATAPI
DEVICE
IQUEUE RAM
IQUEUE
MODULE
USB IQRAM
IQRAM ATA

IQUEUE Module
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5.2 IQUEUE Request Mapping
There are four IQUEUE channels of QC1 to QC4 which can be configured to transfer data to and from
different peripherals. QC1 has the highest priority while QC4 has the lowest priority. QC1 and QC2, QC3
and QC4 can be configured as two double buffer channels. For the IQUEUE module to transfer data from
one peripheral to another automatically, a single or double buffers channel with passing through mode
must be used. For proper operation, the USB peripheral must use the channel with higher priority.
When writing data to an ATA/ATAPI device, QC1REQ is set to USB receive and QC2REQ is set to ATA
transmit. When reading data from the device, QC3REQ is set to USB transmit and QC4REQ is set to ATA
receive.
Table 5-1. IQUEUE Request Mapping
Data Flow QCnREQ Peripheral
Functions Direction
PC →USB →QRAM QC1REQ = 0 USB Rx
PC ←USB ←QRAM QC3REQ = 1 USB Tx
QRAM ←ATA QC4REQ = 2 ATA Rx
QRAM →ATA QC2REQ = 3 ATA Tx
4CF Rx
5CF Tx
6MS Rx
7MS Tx
8SD Rx
9SD Tx
10 SM Rx
11 SM Tx

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Chapter 6
ATA Module
6.1 Introduction
The ATA host controller is designed according to the AT Attachment with Packet Interface–5
(ATA/ATAPI–5) specification. It can support PIO mode 0 to 4 and UDMA mode 0 to 4 with maximum burst
transfer rate of 60M bytes per second.
The firmware is written according to the ATA/ATAPI–6 specification, therefore it can support higher than
137G byte capacity.
6.2 ATA Registers
Table 6-1 summarizes the ATA registers. There are two types of registers: (1) controls the ATA controller
and (2) registers mapped to external ATA/ATAPI device. There are special procedures to read and write
to the ATA device registers.
Table 6-1. ATA Registers
Registers Description
Host Configuration Register Configure ATA host controller
Host Status Register Host controller operating status
PIO Timing Registers 1–4 Timing registers for PIO, DMA and UDMA modes.
One Timing unit is 1/60MHz.
(i.e.: 1 in the register represents 16.67ns)
Multi-Word DMA Timing Registers 1–4
UDMA Timing Registers 1–9
ATA Drive Control Register (write)
ATA Drive Alternate Status Register (read)
These registers are mapped to external ATA device
registers with the same names based on the ATA5
specifications except the DMA Mode Register which
is for the ATA host controller to operate in DMA
mode or not.
ATA Drive Data Register
ATA Drive Feature Register
ATA Drive Error Register
ATA Drive Sector Count Register
ATA Drive Sector Number Register
ATA Drive Cylinder Low Register
ATA Drive Cylinder High Register
ATA Drive Device/Head Register
ATA Drive Cylinder High Register
ATA Drive Command and
DMA Mode Register (write)
ATA Drive Status Register (read)

ATA Module
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6.2.1 Write to ATA Device Registers
1. Wait if TIP of the Host Status Register = 1
2. ATA device register = data
3. Wait if DRAB = 1
6.2.2 Read from ATA Device Registers
1. Wait if TIP of the Host Status Register = 1
2. Data = ATA device register (dummy read)
3. Wait if DRAB = 1
4. Data = ATA device register