NXP Semiconductors SAFE ASSURE Qorivva MPC5602P User manual

MPC5602P Microcontroller Reference Manual, Rev. 4
Freescale Semiconductor 1
Qorivva MPC5602P Microcontroller
Reference Manual
Devices Supported:
MPC5601P
MPC5602P
MPC5602PRM
Rev. 4
28 Feb 2012

MPC5602P Microcontroller Reference Manual, Rev. 4
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Freescale Semiconductor 3
Preface
Overview
The primary objective of this document is to define the functionality of the MPC5602P family of
microcontrollers for use by software and hardware developers. The MPC5602P family is built on
Power Architecture®technology and integrates technologies that are important for today’s electrical
hydraulic power steering (EHPS), electric power steering (EPS), airbag applications, anti-lock braking
systems (ABS), and motor control applications.
As with any technical documentation, it is the reader’s responsibility to be sure he or she is using the most
recent version of the documentation.
To locate any published errata or updates for this document, visit the Freescale Web site at
http://www.freescale.com/.
Audience
This manual is intended for system software and hardware developers and applications programmers who
want to develop products with the MPC5602P device. It is assumed that the reader understands operating
systems, microprocessor system design, basic principles of software and hardware, and basic details of the
Power Architecture.
Chapter organization and device-specific information
This document includes chapters that describe:
• The device as a whole
• The functionality of the individual modules on the device
In the latter, any device-specific information is presented in the section “Information Specific to This
Device” at the beginning of the chapter.
References
In addition to this reference manual, the following documents provide additional information on the
operation of the MPC5602P:
• IEEE-ISTO 5001™ - 2003 and 2010, The Nexus 5001™ Forum Standard for a Global Embedded
Processor Debug Interface
• IEEE 1149.1-2001 standard - IEEE Standard Test Access Port and Boundary-Scan Architecture
• Power Architecture Book E V1.0
(http://www.freescale.com/files/32bit/doc/user_guide/BOOK_EUM.pdf)

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Chapter 1
Introduction
1.1 The MPC5602P microcontroller family ..........................................................................................35
1.2 Target applications ..........................................................................................................................36
1.2.1 Application examples .....................................................................................................36
1.2.1.1 Electric power steering .....................................................................................36
1.2.1.2 Airbag ...............................................................................................................37
1.3 Features ...........................................................................................................................................38
1.4 Critical performance parameters .....................................................................................................41
1.5 Chip-level features ..........................................................................................................................41
1.6 Module features ...............................................................................................................................43
1.6.1 High performance e200z0 core processor ......................................................................43
1.6.2 Crossbar switch (XBAR) ................................................................................................43
1.6.3 Enhanced direct memory access (eDMA) ......................................................................44
1.6.4 Flash memory .................................................................................................................44
1.6.5 Static random access memory (SRAM) .........................................................................45
1.6.6 Interrupt controller (INTC) .............................................................................................46
1.6.7 System status and configuration module (SSCM) ..........................................................46
1.6.8 System clocks and clock generation ...............................................................................47
1.6.9 Frequency-modulated phase-locked loop (FMPLL) ......................................................47
1.6.10 Main oscillator ................................................................................................................47
1.6.11 Internal RC oscillator .....................................................................................................47
1.6.12 Periodic interrupt timer (PIT) .........................................................................................48
1.6.13 System timer module (STM) ..........................................................................................48
1.6.14 Software watchdog timer (SWT) ....................................................................................48
1.6.15 Fault collection unit (FCU) ............................................................................................48
1.6.16 System integration unit – Lite (SIUL) ............................................................................49
1.6.17 Boot and censorship .......................................................................................................49
1.6.17.1 Boot assist module (BAM) ..............................................................................49
1.6.18 Error correction status module (ECSM) .........................................................................50
1.6.19 Peripheral bridge (PBRIDGE) ........................................................................................50
1.6.20 Controller area network (FlexCAN) ...............................................................................50
1.6.21 Safety port (FlexCAN) ...................................................................................................51
1.6.22 Serial communication interface module (LINFlex) .......................................................51
1.6.23 Deserial serial peripheral interface (DSPI) .....................................................................52
1.6.24 Pulse width modulator (FlexPWM) ................................................................................53
1.6.25 eTimer .............................................................................................................................54
1.6.26 Analog-to-digital converter (ADC) module ...................................................................54
1.6.27 Cross triggering unit (CTU) ...........................................................................................55
1.6.28 Nexus Development Interface (NDI) .............................................................................56
1.6.29 Cyclic redundancy check (CRC) ....................................................................................56
1.6.30 IEEE 1149.1 JTAG controller .........................................................................................56
1.6.31 On-chip voltage regulator (VREG) ................................................................................57
1.7 Developer environment ...................................................................................................................57
1.8 Package ............................................................................................................................................57

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Chapter 2
MPC5602P Memory Map
Chapter 3
Signal Description
3.1 100-pin LQFP pinout ......................................................................................................................63
3.2 64-pin LQFP pinout ........................................................................................................................64
3.3 Pin description .................................................................................................................................64
3.3.1 Power supply and reference voltage pins .......................................................................64
3.3.2 System pins .....................................................................................................................66
3.3.3 Pin multiplexing .............................................................................................................66
3.4 CTU / ADC / FlexPWM / eTimer connections ..............................................................................75
Chapter 4
Clock Description
4.1 Clock architecture ...........................................................................................................................79
4.2 Available clock domains .................................................................................................................82
4.2.1 FMPLL input reference clock ........................................................................................82
4.2.2 Clock selectors ................................................................................................................82
4.2.2.1 System clock selector 0 for SYS_CLK ............................................................82
4.2.3 Auxiliary Clock Selector 0 .............................................................................................83
4.2.4 Auxiliary Clock Selector 1 .............................................................................................83
4.2.5 Auxiliary Clock Selector 2 .............................................................................................83
4.2.6 Auxiliary clock dividers .................................................................................................83
4.2.7 External clock divider .....................................................................................................83
4.3 Alternate module clock domains .....................................................................................................84
4.3.1 FlexCAN clock domains ................................................................................................84
4.3.2 SWT clock domains .......................................................................................................84
4.3.3 Cross Triggering Unit (CTU) clock domains .................................................................84
4.3.4 Peripherals behind the IPS bus clock sync bridge ..........................................................84
4.3.4.1 FlexPWM clock domain ..................................................................................84
4.3.4.2 eTimer_0 clock domain ....................................................................................84
4.3.4.3 ADC_0 clock domain .......................................................................................85
4.3.4.4 Safety Port clock domains ................................................................................85
4.4 Clock behavior in STOP and HALT mode ......................................................................................85
4.5 System clock functional safety ........................................................................................................85
4.6 IRC 16 MHz internal RC oscillator (RC_CTL) ..............................................................................86
4.7 XOSC external crystal oscillator .....................................................................................................87
4.7.1 Functional description ....................................................................................................87
4.7.2 Register description ........................................................................................................88
4.8 Frequency Modulated Phase Locked Loop (FMPLL) ....................................................................89
4.8.1 Introduction ....................................................................................................................89
4.8.2 Overview ........................................................................................................................89
4.8.3 Features ...........................................................................................................................89
4.8.4 Memory map ..................................................................................................................90

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4.8.5 Register description ........................................................................................................90
4.8.5.1 Control Register (CR) ......................................................................................90
4.8.5.2 Modulation Register (MR) ...............................................................................92
4.8.6 Functional description ....................................................................................................93
4.8.6.1 Normal mode ....................................................................................................93
4.8.6.2 Progressive clock switching .............................................................................93
4.8.6.3 Normal Mode with frequency modulation .......................................................94
4.8.6.4 Powerdown mode .............................................................................................96
4.8.7 Recommendations ..........................................................................................................96
4.9 Clock Monitor Unit (CMU) ............................................................................................................96
4.9.1 Overview ........................................................................................................................96
4.9.2 Main features ..................................................................................................................97
4.9.3 Functional description ....................................................................................................97
4.9.3.1 Crystal clock monitor .......................................................................................97
4.9.3.2 PLL clock monitor ...........................................................................................98
4.9.3.3 System clock monitor .......................................................................................98
4.9.3.4 Frequency meter ...............................................................................................99
4.9.4 Memory map and register description ............................................................................99
4.9.4.1 Control Status Register (CMU_0_CSR) ........................................................100
4.9.4.2 Frequency Display Register (CMU_0_FDR) ................................................101
4.9.4.3 High Frequency Reference Register FMPLL_0 (CMU_0_HFREFR_A) ......101
4.9.4.4 Low Frequency Reference Register FMPLL_0 (CMU_0_LFREFR_A) .......102
4.9.4.5 Interrupt Status Register (CMU_0_ISR) ........................................................102
4.9.4.6 Measurement Duration Register (CMU_0_MDR) ........................................103
Chapter 5
Clock Generation Module (MC_CGM)
5.1 Overview .......................................................................................................................................105
5.2 Features .........................................................................................................................................106
5.3 External Signal Description ..........................................................................................................107
5.4 Memory Map and Register Definition ..........................................................................................107
5.5 Register Descriptions ....................................................................................................................112
5.5.1 Output Clock Enable Register (CGM_OC_EN) ..........................................................112
5.5.2 Output Clock Division Select Register (CGM_OCDS_SC) ........................................113
5.5.3 System Clock Select Status Register (CGM_SC_SS) ..................................................114
5.5.4 System Clock Divider Configuration Register (CGM_SC_DC0) ................................114
5.5.5 Auxiliary Clock 0 Select Control Register (CGM_AC0_SC) ......................................115
5.5.6 Auxiliary Clock 0 Divider Configuration Register (CGM_AC0_DC0) ......................116
5.5.7 Auxiliary Clock 1 Select Control Register (CGM_AC1_SC) ......................................116
5.5.8 Auxiliary Clock 1 Divider Configuration Register (CGM_AC1_DC0) ......................117
5.5.9 Auxiliary Clock 2 Select Control Register (CGM_AC2_SC) ......................................118
5.5.10 Auxiliary Clock 2 Divider Configuration Register (CGM_AC2_DC0) ......................119
5.6 Functional Description ..................................................................................................................119
5.7 System Clock Generation ..............................................................................................................119
5.7.1 System Clock Source Selection ....................................................................................120

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5.7.2 System Clock Disable ...................................................................................................120
5.7.3 System Clock Dividers .................................................................................................120
5.8 Auxiliary Clock Generation ..........................................................................................................120
5.8.1 Auxiliary Clock Source Selection ................................................................................123
5.8.2 Auxiliary Clock Dividers .............................................................................................123
5.9 Dividers Functional Description ...................................................................................................123
5.10 Output Clock Multiplexing ...........................................................................................................124
5.11 Output Clock Division Selection ...................................................................................................124
Chapter 6
Power Control Unit (MC_PCU)
6.1 Introduction ...................................................................................................................................125
6.1.1 Overview ......................................................................................................................125
6.1.2 Features .........................................................................................................................126
6.2 External Signal Description ..........................................................................................................126
6.3 Memory Map and Register Definition ..........................................................................................126
6.3.1 Memory Map ................................................................................................................126
6.3.2 Register Descriptions ....................................................................................................127
6.3.2.1 Power Domain Status Register (PCU_PSTAT) ..............................................127
Chapter 7
Mode Entry Module (MC_ME)
7.1 Introduction ...................................................................................................................................129
7.1.1 Overview ......................................................................................................................129
7.1.2 Features .........................................................................................................................131
7.1.3 Modes of Operation ......................................................................................................131
7.2 External Signal Description ..........................................................................................................132
7.3 Memory Map and Register Definition ..........................................................................................132
7.3.1 Memory Map ................................................................................................................133
7.3.2 Register Description .....................................................................................................140
7.3.2.1 Global Status Register (ME_GS) ...................................................................140
7.3.2.2 Mode Control Register (ME_MCTL) ............................................................142
7.3.2.3 Mode Enable Register (ME_ME) ..................................................................143
7.3.2.4 Interrupt Status Register (ME_IS) .................................................................144
7.3.2.5 Interrupt Mask Register (ME_IM) .................................................................145
7.3.2.6 Invalid Mode Transition Status Register (ME_IMTS) ..................................146
7.3.2.7 Debug Mode Transition Status Register (ME_DMTS) ..................................147
7.3.2.8 RESET Mode Configuration Register (ME_RESET_MC) ...........................150
7.3.2.9 TEST Mode Configuration Register (ME_TEST_MC) .................................150
7.3.2.10 SAFE Mode Configuration Register (ME_SAFE_MC) ................................151
7.3.2.11 DRUN Mode Configuration Register (ME_DRUN_MC) .............................151
7.3.2.12 RUN0…3 Mode Configuration Registers (ME_RUN0…3_MC) .................152
7.3.2.13 HALT0 Mode Configuration Register (ME_HALT0_MC) ...........................152
7.3.2.14 STOP0 Mode Configuration Register (ME_STOP0_MC) ............................153
7.3.2.15 Peripheral Status Register 0 (ME_PS0) .........................................................155

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7.3.2.16 Peripheral Status Register 1 (ME_PS1) .........................................................155
7.3.2.17 Peripheral Status Register 2 (ME_PS2) .........................................................156
7.3.2.18 Run Peripheral Configuration Registers (ME_RUN_PC0…7) .....................156
7.3.2.19 Low-Power Peripheral Configuration Registers (ME_LP_PC0…7) .............157
7.3.2.20 Peripheral Control Registers (ME_PCTL0…143) .........................................158
7.4 Functional Description ..................................................................................................................159
7.4.1 Mode Transition Request ..............................................................................................159
7.4.2 Modes Details ...............................................................................................................160
7.4.2.1 RESET Mode .................................................................................................160
7.4.2.2 DRUN Mode ..................................................................................................161
7.4.2.3 SAFE Mode ....................................................................................................161
7.4.2.4 TEST Mode ....................................................................................................162
7.4.2.5 RUN0…3 Modes ...........................................................................................162
7.4.2.6 HALT0 Mode .................................................................................................163
7.4.2.7 STOP0 Mode ..................................................................................................163
7.4.3 Mode Transition Process ..............................................................................................164
7.4.3.1 Target Mode Request .....................................................................................164
7.4.3.2 Target Mode Configuration Loading .............................................................164
7.4.3.3 Peripheral Clocks Disable ..............................................................................165
7.4.3.4 Processor Low-Power Mode Entry ................................................................166
7.4.3.5 Processor and System Memory Clock Disable ..............................................166
7.4.3.6 Clock Sources Switch-On ..............................................................................166
7.4.3.7 Flash Modules Switch-On ..............................................................................167
7.4.3.8 Pad Outputs-On ..............................................................................................167
7.4.3.9 Peripheral Clocks Enable ...............................................................................167
7.4.3.10 Processor and Memory Clock Enable ............................................................167
7.4.3.11 Processor Low-Power Mode Exit ..................................................................167
7.4.3.12 System Clock Switching ................................................................................167
7.4.3.13 Pad Switch-Off ...............................................................................................168
7.4.3.14 Clock Sources (with no Dependencies) Switch-Off ......................................169
7.4.3.15 Clock Sources (with Dependencies) Switch-Off ...........................................169
7.4.3.16 Flash Switch-Off ............................................................................................169
7.4.3.17 Current Mode Update .....................................................................................169
7.4.4 Protection of Mode Configuration Registers ................................................................172
7.4.5 Mode Transition Interrupts ...........................................................................................172
7.4.5.1 Invalid Mode Configuration Interrupt ............................................................172
7.4.5.2 Invalid Mode Transition Interrupt ..................................................................172
7.4.5.3 SAFE Mode Transition Interrupt ...................................................................174
7.4.5.4 Mode Transition Complete Interrupt .............................................................174
7.4.6 Peripheral Clock Gating ...............................................................................................174
7.4.7 Application Example ....................................................................................................175
Chapter 8
Reset Generation Module (MC_RGM)
8.1 Introduction ...................................................................................................................................177

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8.1.1 Overview ......................................................................................................................177
8.1.2 Features .........................................................................................................................178
8.1.3 Reset Sources ................................................................................................................179
8.2 External Signal Description ..........................................................................................................180
8.3 Memory Map and Register Definition ..........................................................................................180
8.3.1 Register Descriptions ....................................................................................................182
8.3.1.1 Functional Event Status Register (RGM_FES) ..............................................182
8.3.1.2 Destructive Event Status Register (RGM_DES) ............................................184
8.3.1.3 Functional Event Reset Disable Register (RGM_FERD) ..............................185
8.3.1.4 Destructive Event Reset Disable Register (RGM_DERD) ............................186
8.3.1.5 Functional Event Alternate Request Register (RGM_FEAR) .......................187
8.3.1.6 Functional Event Short Sequence Register (RGM_FESS) ............................188
8.3.1.7 Functional Bidirectional Reset Enable Register (RGM_FBRE) ....................190
8.4 Functional Description ..................................................................................................................191
8.4.1 Reset State Machine .....................................................................................................191
8.4.1.1 PHASE0 Phase ...............................................................................................192
8.4.1.2 PHASE1 Phase ...............................................................................................193
8.4.1.3 PHASE2 Phase ...............................................................................................193
8.4.1.4 PHASE3 Phase ...............................................................................................193
8.4.1.5 IDLE Phase ....................................................................................................193
8.4.2 Destructive Resets ........................................................................................................194
8.4.3 External Reset ...............................................................................................................194
8.4.4 Functional Resets ..........................................................................................................195
8.4.5 Alternate Event Generation ..........................................................................................195
8.4.6 Boot Mode Capturing ...................................................................................................196
Chapter 9
Interrupt Controller (INTC)
9.1 Introduction ...................................................................................................................................197
9.2 Features .........................................................................................................................................197
9.3 Block diagram ...............................................................................................................................199
9.4 Modes of operation ........................................................................................................................199
9.4.1 Normal mode ................................................................................................................199
9.4.1.1 Software vector mode ....................................................................................199
9.4.1.2 Hardware vector mode ...................................................................................200
9.4.1.3 Debug mode ...................................................................................................200
9.4.1.4 Stop mode .......................................................................................................200
9.5 Memory map and registers description .........................................................................................201
9.5.1 Module memory map ...................................................................................................201
9.5.2 Registers description ....................................................................................................201
9.5.2.1 INTC Module Configuration Register (INTC_MCR) ...................................202
9.5.2.2 INTC Current Priority Register (INTC_CPR) ...............................................203
9.5.2.3 INTC Interrupt Acknowledge Register(INTC_IACKR) ...............................204
9.5.2.4 INTC End-of-Interrupt Register (INTC_EOIR) ............................................205