PerfecTron OXY5323A User manual

1
Safety Information
Electrical safety
To prevent electrical shock hazard, disconnect the power cable from the electrical outlet before
relocating the system.
When adding or removing devices to or from the system, ensure that the power cables for the
devices are unplugged before the signal cables are connected. If possible, disconnect all power
cables from the existing system before you add a device.
Before connecting or removing signal cables from the motherboard, ensure that all power cables
are unplugged.
Seek professional assistance before using an adapter or extension cord. These devices could
interrupt the grounding circuit.
Make sure that your power supply is set to the correct voltage in your area.
If you are not sure about the voltage of the electrical outlet you are using, contact your local
power company.
If the power supply is broken, do not try to fix it by yourself. Contact a qualified service
technician or your local distributor.
Operation safety
Before installing the motherboard and adding devices on it, carefully read all the manuals that
came with the package.
Before using the product, make sure all cables are correctly connected and the power cables are
not damaged. If you detect any damage, contact your dealer immediately.
To avoid short circuits, keep paper clips, screws, and staples away from connectors, slots,
sockets and circuitry.
Avoid dust, humidity, and temperature extremes. Do not place the product in any area where it
may become wet.
Place the product on a stable surface.
If you encounter any technical problems with the product, contact your local distributor
Statement
All rights reserved. No part of this publication may be reproduced in any form or by any means,
without prior written permission from the publisher.
All trademarks are the properties of the respective owners.
All product specifications are subject to change without prior notice

2
Revision History
Revision
Date (yyyy/mm/dd)
Changes
V1.0
2021/09/08
First release
Packing List
Item
Description
Q’ty
1
OXY5323A
1
2
Driver CD+ User’s manual
1
Ordering information
OXY5323A-01ET
Intel®Apollo Lake-I E3930,DDR3L 1867 MHz, 1 x 204-pin SO-DIMM, Max. 8GB (Non-ECC),2 x Intel® I210-IT Giga
LAN,4 x USB 3.0,1 x HDMI 1.4, 1 x VGA,2 x RJ-45,Normal Temperature: -20°C to 70°C
OXY5323A-01UT
Intel®Apollo Lake-I E3930,DDR3L 1867 MHz, 1 x 204-pin SO-DIMM, Max. 8GB (Non-ECC),2 x Intel® I210-IT Giga
LAN,4 x USB 3.0,1 x HDMI 1.4, 1 x VGA,2 x RJ-45,Wide Temperature (Optional*) : -40°C to 85°C
OXY5323A-02ET
Intel®Apollo Lake-M N3350,DDR3L 1867 MHz, 1 x 204-pin SO-DIMM, Max. 8GB (Non-ECC),2 x Intel® I210- IT
Giga LAN,4 x USB 3.0,1 x HDMI 1.4, 1 x VGA,2 x RJ-45,Normal Temperature:-20°C to 70°C
OXY5323A-02UT
Intel®Apollo Lake-M N3350,DDR3L 1867 MHz, 1 x 204-pin SO-DIMM, Max. 8GB (Non-ECC),2 x Intel® I210- IT Giga
LAN,4 x USB 3.0,1 x HDMI 1.4, 1 x VGA,2 x RJ-45, Wide Temperature (Optional*):-40°C to 85°C
OXY5323A-03ET
Intel®Apollo Lake-M N4200,DDR3L 1867 MHz, 1 x 204-pin SO-DIMM, Max. 8GB (Non-ECC),2 x Intel® I210- IT
Giga LAN,4 x USB 3.0,1 x HDMI 1.4, 1 x VGA,2 x RJ-45,Normal Temperature:-20°C to 70°C
OXY5323A-03UT
Intel®Apollo Lake-M N4200,DDR3L 1867 MHz, 1 x 204-pin SO-DIMM, Max. 8GB (Non-ECC),2 x Intel® I210- IT Giga
LAN,4 x USB 3.0,1 x HDMI 1.4, 1 x VGA,2 x RJ-45, Wide Temperature (Optional*):-40°C to 85°C

3
Table of Contents
Chapter 1 : Production Introduction........................................................................................................... 5
1.1Block Diagram....................................................................................................................................... 5
1.2 Specifications ....................................................................................................................................... 6
1.3I/O Placement ....................................................................................................................................... 7
Chapter 2 : Jumpers and Connectors ........................................................................................................ 8
2.1 LVDS panel pin Header....................................................................................................................... 8
2.2 eDP panel pin Header.......................................................................................................................... 9
2.3 Audio .................................................................................................................................................. 10
2.4 2ea LAN port ...................................................................................................................................... 11
2.5 SATA .................................................................................................................................................. 11
2.6 Super I/O ............................................................................................................................................ 11
2.7 Back Panel I/O.................................................................................................................................... 11
2.8 USB .................................................................................................................................................... 12
2.9 PCI Express Expansion Slots............................................................................................................. 12
2.10 Expansion Slot Layout..................................................................................................................... 13
2.11 Front Panel....................................................................................................................................... 13
2.12 MiAPI feature.................................................................................................................................... 14
2.13 Serial Port......................................................................................................................................... 14
2.14 AT/ATX, CMOS , mSATA header in silkscreen / feature................................................................. 15
2.15 SATA power 1.25mm cable pin header ........................................................................................... 15
2.16 ATX power 4P/DC power 4.2mm pin header................................................................................... 16
2.17 Thermal Management and Fan Control ........................................................................................... 17
2.18 CPU Fans......................................................................................................................................... 17
2.19 Fan Header Requirements............................................................................................................... 18
Chapter 3 : BIOS Specification.................................................................................................................. 18
3.1 MAIN PAGE........................................................................................................................................ 18
3.2 ADVANCED PAGE............................................................................................................................. 22
3.2.1 INTEL(R) I210 GIGABIT NETWORK CONNECTION –00:22:4D:4D:00:01…………………………25
3.2.2 NIC CONFIGURATION……………………………………………………………………………………….27
3.2.3 INTEL(R) I210 GIGABIT NETWORK CONNECTION –00:22:4D:4D:00:02…………………………29
3.2.4 NIC CONFIGURATION……………………………………………………………………………………30
3.3DRIVER HEALTH................................................................................................................................ 31
3.3.1 INTEL(R) PRO/1000 7.3.20 PCI-E………………………………………………………………………33

4
3.4 TRUSTED COMPUTING ................................................................................................................... 35
3.5 SMART SETTINGS............................................................................................................................ 37
3.6 NCT6116D SUPER IO CONFIGURATION........................................................................................ 38
3.7 S5 RTC WAKE SETTINGS(NO FUNCTION WHEN DEEPSX POWER POLICIES ENABLED) ...... 41
3.8 CPU CONFIGURATION..................................................................................................................... 44
3.9 NETWORK STACK CONFIGURATION............................................................................................. 50
3.10PLATFROM TRUST TECHNOLOGY................................................................................................ 51
3.11 CHIPSET.......................................................................................................................................... 52
3.12 SECURITY ....................................................................................................................................... 58
3.12.1 HDD SECURITY CONFIGURATION…………………………………………………………………60
3.12.2SECURE BOOT MODE…………………………………………………………………………………62
3.12.3KEY MANAGERMENT……………………………………………………………………………………64
3.13 BOOT ............................................................................................................................................... 69
3.14 SAVE & EXIT.................................................................................................................................... 73

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Chapter 1 : Production Introduction
1.1 Block Diagram

6
1.2 Specifications
System
CPU
Apollo Lake-M
N3350/N4200
Apollo Lake-I E3930
Memory type
DDR3L 1867 MHz, 1 x 204-pin SO-DIMM, Max. 8GB (Non-ECC)
Chipset
Intel® SoC Integrated
Graphics
Intel® HD Graphics
Ethernet
2 x Intel® I210-IT Giga LAN
Audio>
Realtek® ALC662
I/O Chipset
Nuvoton NCT6116D
TPM
Nuvoton NPCT650ABCYX TPM2.0 (Optional)
Expansion
Slot
Storage: Mini PCIe Full size (USB / PCIe / SATA), w/ SIM Card Holder
Wireless: M.2 2230 E key (PCIe / USB)
BIOS
AMI BIOS
H / W
Monitor
Temperature Monitor, Voltage Monitor
Watchdog
Timer
1 to 255 Steps by Software Program
Smart Fan
Control
CPU Fan
Graphics
VGA
Up to 1920 x 1200 @60 Hz
HDMI
Up to 4K (3840 x 2160) @30 Hz
LVDS>
Up to 1920 x 1200 @60 Hz>
eDP (Option)
Up to 4K (3840 x 2160) @60 Hz>
Rear I/O
USB
4 x USB 3.0>
Display I/O
1 x HDMI 1.4, 1 x VGA
LAN I/O
2 x RJ-45>
Internal Connectors
Storage
2 x SATAIII ( 1 x SATA is multiplexed with 1 x mSATA port)
USB
2 x USB 2.0
Display I/O
1 x LVDS, 1 x eDP
1 x Backlight Connector
Audio I/O
1 x Audio Header (Front Panel Mic-in & Line-out)
Serial Port
4 x RS232 (One Supports RS232/422/485)
GPIO
1 x Miap Header (Programmable. Support 10-bit GPIO)
Fan
1 x 4-pin CPU Fan Header
Power
1 x 8V to 24V ATX Power Connector, 1 x AT/ATX Mode Select Jumper
Others
1 x CMOS Jumper

7
Power Requirement
Power Input
8V to 24V Wide Range DC Input w/4-pin ATX connector (Pitch: 4.2mm)
Environmental
Operating
Temperature
Normal Temperature:-20°C to 70°C
Wide Temperature (Optional*) : -40°C to 85°C
Storage
Temperature
-40°C to 85°C (-40°F to 185°F)
Operating
Humidity
10% to 95% R/H, non-condensing
Certification
CE & FCC Class B
OS
OS Support
Windows® 10 64-bit
1.3 I/O Placement

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Chapter 2 : Jumpers and Connectors
2.1 FRONT_PANEL1 (JLVDS1) LVDS panel pin out define
PIN
DEFINITION
PIN
DEFINITION
1
Minus signal of odd
channel 0 (LVDS)
2
Minus signal of odd
channel 0 (LVDS)
3
Plus signal of odd
channel 0 (LVDS)
4
Plus signal of odd
channel 0 (LVDS)
5
Minus signal of odd
channel 1 (LVDS)
6
Minus signal of odd
channel 1 (LVDS)
7
Plus signal of odd
channel 1 (LVDS)
8
Plus signal of odd
channel 1 (LVDS)
9
Minus signal of odd
channel 2 (LVDS)
10
Ground
11
Plus signal of odd
channel 2 (LVDS)
12
Minus signal of odd
channel 2 (LVDS)
13
Ground
14
Plus signal of odd
channel 2 (LVDS)
15
Minus signal of odd
clock channel (LVDS)
16
Minus signal of odd
clock channel (LVDS)
17
Plus signal of odd clock
channel (LVDS)
18
Plus signal of odd clock
channel (LVDS)
19
Minus signal of odd
channel 3 (LVDS)
20
Minus signal of odd
channel 3 (LVDS)
21
Plus signal of odd
channel 3 (LVDS)
22
Plus signal of odd
channel 3 (LVDS)
23
Ground
24
Ground
25
NC
26
NC
27
Power Supply +12.0V
28
Power Supply +12.0V
29
Power Supply +12.0V
30
Power Supply +12.0V

9
2.2 EDP1 Pin out define
Pin
Signal
Pin
Signal
1
NC_ Reserved
21
LCD_VCC
2
High-speed _GND
22
LCD_ Self _ Test-or-
NC
3
Lane3_N(DDPD_[3]N)
23
LCD_GND
4
Lane3_P(DDPD_[3]P)
24
LCD_GND
5
High-speed_ GND
25
LCD_GND
6
Lane2_N(DDPD_[2]N)
26
LCD_GND
7
Lane2_P(DDPD_[2]P)
27
HDP(DDPD_HPD)
8
High-speed_ GND
28
BKLT_GND
9
Lane1_N(DDPD_[1]N)
29
BKLT_GND
10
Lane1_P(DDPD_[1]P)
30
BKLT_GND
11
High-speed_ GND
31
BKLT_GND
12
Lane0_N(DDPD_[0]N)
32
BKLT_ENABLE
13
Lane0_P(DDPD_[0]P)
33
BKLT_PWM_DIM
14
High-speed_ GND
34
NC_ Reserved
15
AUX_CH_P(DDPD_AUXP)
35
NC_ Reserved
16
AUX_CH_N(DDPD_AUXN)
36
BKLT_PWR
17
High-speed_ GND
37
BKLT_PWR
18
LCD_VCC
38
BKLT_PWR
19
LCD_VCC
39
BKLT_PWR
20
LCD_VCC
40
NC_ Reserved
LCD_PS1 : Panel LCD voltage selection header pin-out
Pin
Signal
Description
1
Key
No pin
2
3.3V
3.3V option
(Default)
3
12V
12V option
4
LCD_VCC
Send voltage to
connector
5
Key
No pin
6
5V
5V option
3.3V
5V
12V
12V
12V
12V
Pins 2&4: Jumper position for 3.3V
Pins 6&4: Jumper position for 5V
Pins 3&4: Jumper position for 12V

10
BKLT_PS1 : Backlight inverter voltage selection header
Pin
Signal
Description
1
5V
5V option
2
BKLT_PWR
BKLT_PWR
3
12V
12V option (default)
FPD_PWR1 Pin out define
Pin
Signal
Description
1
BKLT_EN
Backlight enable
2
BKLT_PWM
Backlight control
3
BKLT_PWR
Backlight inverter power
4
BKLT_PWR
Backlight inverter power
5
BKLT_GND/Brightness _GND
Ground (shared)
6
BKLT_GND/Brightness _GND
Ground (shared)
7
Brightness _Up
Panel brightness increase
8
Brightness _Down
Panel brightness decrease
2.3 FPAUDIO2 Audio Pin out define
Pin
Pin Assignment
Pin
Pin Assignment
1
MIC2 L (Microphone 2 Left)
2
AGND (Analog Ground)
3
MIC2 R (Microphone 2 Right)
4
AVCC (Analog VCC Power)
5
FRO-R (Front Right)
6
MIC2_JD (Microphone 2 Jack
Detect)
7
F_IO_SEN (Front I/O Sensor)
8
Key
9
FRO-L (Front Left)
10
LINE2_JD (LINE 2 Jack Detect)
5V
12V
5V
12V
1
2
4
6
10
3
5
7
9
FPAUDIO2
4
10
9
7
6
5
3
2
1
Port2L
Sense _Send
Port2R
Port1R
Port1L
Sense2_Ret
Key(no pin)
Sense1_Ret
Presence#
Ground

11
2.4 LAN port
Diagram
LED
Color
State
Condition
Link
N/A
Off
LAN link is not established
Green
On
LAN link is established
Blinking
LAN activity occurring
Speed
N/A
Off
10 Mb/s data rate
Green
On
100 Mb/s data rate
Yellow
On
1000 Mb/s data rate
2.5 SATA
SATA PORT0: This is optional port from mini PCI-E and SATA0 Connector
One fully-shrouded right angle internal SATA gen 3 ports (colored GREY)
SATA PORT1
one fully-shrouded right ang
Note: All SATA must be compliant with the Serial ATA Revision 3.0 Specification, as noted in the
Reference Documentation section.
2.6 Super I/O
Board must support the following features through a Super IO c

Support for as one fan headers as required in section 1.4.2 -

Support for non-
Legacy I/O (for applicable ports)
2.7 Back Panel I/O

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2.8 USB
Front panel USB header pin-out define (FP_USB1)
Pin
Signal
Pin
Signal
FP_USB1
1
+5V DC
2
+5V DC
3
Data (negative)
4
Data (negative)
5
Data (positive)
6
Data (positive)
7
Ground
8
Ground
9
Key (no pin)
10
No Connect
Rear USB3.0 I/O port (J5/J10)
Pin
Number
Signal Name
Description
Mating Sequence
J5/J10
1
VBUS
Power
Second
2
D-
USB 2.0
differential pair
Third
3
D+
4
GND
Ground for
power return
Second
5
StdA _SSRX-
SuperSpeed
receiver
differential pair
Last
6
StdA_ SSRX+
7
GND_DRAIN
Ground for
signal return
8
StdA_ SSTX-
SuperSpeed
transmitter
differential pair
9
StdA_ SSTX+
Shell
Shield
Connector
metal shell
First
2.9 PCI Express Expansion Slots
Board’s PCI Express slot(s) must be PCI Express Specification v2.0 compliant and compatible with PCI Express
v2.0 and v1.1 add-in cards.
PCI Express x16 slot must be compatible with x16/x8/x4/x1 PCI Express add-on cards. PCIe x16 slot’s retention
mechanism must be consistent across Intel desktop boards.
PCI Express x4 slot(s) must be compatible with PCI Express x4 and x1 add-on cards. Slot power capability must
comply with 25W requirement as defined in the PCI Express Card Electromechanical
3.0 Specification.
PCI Express x1 slot(s) must be compatible with x1 PCI Express add-on cards.
Route WAKE# to support ACPI wake events.
Design must provide SMBus routed to all PCI Express slots, with individual/per slot de-stuffing option via
strapping resistor (strapping resistor must be stuffed by default).
1
2
9
10
1
2
3
4
5
6
7
8
9

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Follow the ATX specification and Industrial DFA (Design for Assembly) standard requirements for connector
placement and spacing.
Keep-out zone of PCI Express v3.0 x16 slot must allow use of double-width and long graphics cards without
blocking access to any connectors (i.e. SATA ports, DIMM connector tabs, front panel audio header, …).
2.10 Expansion Slot Layout
Slot Configuration
Electrical
Physical Connector
Color
J43
M.2 key M socket
M.2 Key E socket
Black
J25
PCI Express 3.0 x1
Mini PCIE
Black
2.11 Front Panel Pin out define (JS2)
Pin
Signal Name
Description
Pin
Signal Name
Description
1
HDD_POWER_LED
Pull-up
resistor (750Ώ)
to +5V
2
POWER_LED_MAIN
[Out] Front panel LED (main
color)
3
HDD_LED#
[Out] Hard
disk activity
LED
4
POWER_LED_ALT
[Out] Front panel LED (alt
color)
5
GROUND
Ground
6
POWER_SWITCH#
[In] Power switch
7
RESET_SWITCH#
[In] Reset
switch
8
GROUND
Ground
9
+5V_DC
Power
10
KEY
No pin
PWR_LED
(+) (-)
ON / OFF
(+) (-)
HDD_LED
RESET

14
2.12 J_MiAPI_1 Pin out define
Pin
Signal Name
Pin
Signal Name
1
MAPI_GPIO1
2
VCC
3
MAPI_GPIO2
4
MAPI_GPIO6
5
MAPI_GPIO3
6
MAPI_GPIO7
7
MAPI_GPIO4
8
MAPI_GPIO8
9
MAPI_GPIO5
10
MAPI_GPIO9
11
Watchdog Timer
12
MAPI_GPIO10
13
Power Button
14
SMB_MAIN_DATA
15
UART_TX
16
SMB_MAIN_CLK
17
UART_RX
18
5VSB
19
GND
20
N/C
2.13 Serial Port
J_RS485_P4, J_RS232_P2 Serial port header pin out define
RS232_P1P3 Serial port header pin out define
Pin
Signal
Pin
Signal
RS485/RS422/RS232 feature:
RS232
RS232
1
DCD (Data Carrier
Detect)
2
RXD# (Receive Data)
3
TXD# (Transmit Data)
4
DTR (Data Terminal
Ready)
5
Ground
6
DSR (Data Set Ready)
7
RTS (Request To Send)
8
CTS (Clear To Send)
9
RI (Ring Indicator)
10
NC
11
DCD (Data Carrier
Detect)
12
RXD# (Receive Data)
13
TXD# (Transmit Data)
14
DTR (Data Terminal
Ready)
15
Ground
16
DSR (Data Set Ready)
17
RTS (Request To Send)
18
CTS (Clear To Send)
19
RI (Ring Indicator)
20
NC
RXD#
DTR
DSR
CTS
KEY (no pair)
DCD
TXD#
GROUND
RTX
RI

15
2.14 AT/ATX, CMOS , mSATA header in silkscreen / feature (J_AT_CMOS1) pin out define
JUMPER
J_AT_CMOS1
(1-2)
Clear CMOS
(1-3)
Normal
(4-6)
ATX
(6-8)
AT
(5-7)
PCIE
(5-7) NA
mSATA
JUMPER
(1-2)
(1-3)
Clear CMOS
Clear CMOS
Normal
JUMPER
(8-6)
(4-6)
AT/ATX
AT Mode
ATX(Default)
mSATA detection function:
JUMPER
(5-7) IN
(5-7) NA
mSATA/PCIE
PCIE 3G
Module(Default)
mSATA
2.15 SATA power 1.25mm cable pin out define
J_SATA_PWR1
Pin
signal
1
5V
2
GND
3
NC
J_SATA_PWR2
Pin
signal
1
VCC3
2
GND
3
VCC
4
+12V
CMOS clear
Normal: 1-3
Clear CMOS: 1-2

16
2.16 ATX power 4P/DC power 4.2mm pin out define
J_PW4P_1
Pin
signal
1
GND
2
GND
3
Power 8V~24V
4
Power 8V~24V

17
2.17 Thermal Management and Fan Control
Nuvoton NCT6104D SuperIO: backup alternate solution as it leverages existing hardware in the designs,
but software infrastructure must be put in place to support this solution.
Regardless of solution chosen, BIOS/driver/tools support and subsystem validation is required, even if
solution is not needed by pilot.
Board must use SuperIO solution for hardware monitoring and thermal management. SuperIO
implementation must be supported by BIOS, tools and drivers necessary for custom thermal profile
management no later than by fab B samples.
BIOS/tools/driver support and subsystem validation is required.
The thermal management capability must support temperature sensors near CPU VR FETs as well as near
or on the memory components; shall only one temperature sensor be feasible it must be located near
the CPU VR FETs.
The following thermal management features must be supported:
Temperature monitoring at the following locations:
•remote diode near CPU VR FETs
•remote diode near or on the memory components
Voltage monitoring (in priority order): +12V, V_SM, CPU VCC_VCGI, CPU VNN_SVID
2.18 CPU Fans
Processor fan header (J20) :

18
2.19 Fan Header Requirements
The below requirements must be met for the 4-
Closed loop fan speed control via the FANPWM0 signal routed to pin-


Clearly label
Locate closest to the CPU as required by the CDPG boxed CPU
Chapter 3 : BIOS Specification
This chapter provides information about how to set up BIOS and use BIOS menu items to adjust basic function
settings.
3.1 MAIN PAGE

19