Philips TDA8443A User manual

DATA SHEET
Product specification
Supersedes data of November 1992
File under Integrated Circuits, IC02
1995 Mar 07
INTEGRATED CIRCUITS
Philips Semiconductors
TDA8443A
I2C-bus controlled YUV/RGB switch

1995 Mar 07 2
Philips Semiconductors Product specification
I2C-bus controlled YUV/RGB switch TDA8443A
FEATURES
•Two RGB/YUV selectable clamped inputs with
associated synchronization
•RGB/YUV matrix
•3-state switching with an OFF-state
•Selectable gain
•I2C-bus or non-I2C-bus mode
•Address selection for 7 devices
•Fast switching.
GENERAL DESCRIPTION
The TDA8443A is a general purpose two-channel switch
for YUV or RGB signals. One channel provides matrixing
from RGB to YUV, which can be bypassed.
The IC is controlled via I2C-bus by seven different
addresses or can be used in a non-I2C-bus mode. In the
non-I2C-bus mode, control of the circuit is achieved by DC
voltages.
QUICK REFERENCE DATA
ORDERING INFORMATION
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
VPsupply voltage (pin 18) 10.8 12.0 13.2 V
IPsupply current −65 90 mA
RGB/YUV channels
Z19-22 output impedance (pin 19) −730Ω
Z
20-22 output impedance (pin 20) −730Ω
Z
21-22 output impedance (pin 21) −730Ω
B bandwidth −3 dB; mode 0 or 2 −25 −MHz
+3 dB; mode 0 or 2 −12 −MHz
±3 dB; mode 1 −10 −MHz
VO(p−p) maximum output amplitude of YUV
signals (peak-to-peak value) gain ×1 2.1 −−V
gain ×2 4.2 −−V
T
amb operating ambient temperature 0 −+70 °C
TYPE
NUMBER PACKAGE
NAME DESCRIPTION VERSION
TDA8443A DIP24 plastic dual in-line package; 24 leads (600 mil) SOT101-1

1995 Mar 07 3
Philips Semiconductors Product specification
I2C-bus controlled YUV/RGB switch TDA8443A
BLOCK DIAGRAM
Fig.1 Block diagram.
handbook, full pagewidth
MLD003
A4 A3 A2 A1
I C-BUS INTERFACE/
DECODER
2
20 21 2319 22181716151413 24
B3 B2 B1
MATRIX
RGB/YUV
CLAMP CLAMP CLAMP
CLAMP PULSE
GENERATOR
CLAMP CLAMP CLAMP
2456710111289
TDA8443A
3 1
FAST
SWITCHING
SELfast
switching
SYNC2B/ (B Y)
input
internal
voltage
R/ (R Y)
input
G/Y
input
B/ (B Y)
input
SYNC1
ON
input G/Y input R/ (R Y) input
channel 1 channel 2
SDA SCL S0 S1 S2 VGND SYNC
output clamp pulse generator
R/ (R Y)
input
G/Y
input
B/ (B Y)
input
outputs
P

1995 Mar 07 4
Philips Semiconductors Product specification
I2C-bus controlled YUV/RGB switch TDA8443A
PINNING
SYMBOL PIN DESCRIPTION
SEL 1 select input
(non-I2C-bus mode only)
SYNC2 2 synchronization input for
Channel 2
FS 3 fast switching input
R/±(R−Y)IN 4 R or (R−Y) signal input
G/Y IN 5 G or Y signal input
B/±(B−Y)IN 6 B or (B−Y) signal input
VINT 7 internal voltage supply
SYNC1 8 synchronization input for
Channel 1
ON 9 ON input
R/−(R−Y)IN 10 R or −(R−Y) signal input
G/Y IN 11 G or Y signal input
B/−(B−Y)IN 12 B or −(B−Y) signal input
SDA 13 serial data input/output; I2C-bus
SCL 14 serial clock input; I2C-bus
S0 15 address selection input 0
S1 16 address selection input 1
S2 17 address selection input 2
VP18 supply voltage
B/−(B−Y)OUT 19 B or −(B−Y) signal output
G/Y OUT 20 G or Y signal output
R/−(R−Y)OUT 21 R or −(R−Y) signal output
GND 22 ground
SYNC 23 synchronization output
CLAMP 24 clamping pulse generator
input/output Fig.2 Pin configuration.
handbook, halfpage
TDA8443A
MLD004
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SEL
SYNC2
FS
R/ (R Y) IN
G/Y IN
B/ (B Y) IN
V INT
SYNC1
ON
R/ (R Y) IN
G/Y IN
B/ (B Y) IN
CLAMP
SYNC
GND
R/ (R Y) OUT
G/Y OUT
B/ (B Y) OUT
V
S2
S1
S0
SCL
SDA
P

1995 Mar 07 5
Philips Semiconductors Product specification
I2C-bus controlled YUV/RGB switch TDA8443A
FUNCTIONAL DESCRIPTION
The circuit contains two sets of inputs (see Fig.1). Both
channels can receive RGB or YUV signals. Each set of
inputs has its own synchronization input, which internally
generates a pulse to clamp the inputs. The internal
clamping pulse can also be controlled by a signal (e.g. a
sandcastle pulse) applied to pin 24. The pulse will occur
during the time that the signal at pin 24 is between
5.5 and 6.5 V. If both a sync signal and a pin 24 signal are
used the signal should be applied to pin 24 via a 1 kΩ
resistor.
RGB signals of Channel 2 can be matrixed to YUV signals.
The outputs can be set in a high impedance OFF state,
which allows the use of seven devices in parallel
(I2C-bus mode).
The circuit can be controlled by an I2C-bus compatible
microcontroller or directly by DC voltages. The fast
switching input can be operated via pin 16 of the
peritelevision connector.
I2C-bus mode
The protocol for the devices in I2C-bus mode is shown
in Fig.3.
Table 1 Protocol bit description
BIT DESCRIPTION
STA start condition
MA2 to MA0 address selection bits; see Table 2
ACK acknowledge bit
D7 channel selection bit; see Table 3
D6 matrix selection bit; see Table 3
D5 to D3 gain control bits; see Table 4
D2 fast switching priority bit; see Table 5
D1 and D0 output state control bits; see Table 6
STO stop condition
Fig.3 I2C-bus protocol.
handbook, full pagewidth
STA 1 1 0 1 MA2 MA1 MA0 0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK STO
MSA003
See Table 1.

1995 Mar 07 6
Philips Semiconductors Product specification
I2C-bus controlled YUV/RGB switch TDA8443A
Table 2 Address selection
Notes
1. L = LOW level input voltage.
2. H = HIGH level input voltage.
3. ∗= non-I2C-bus operation.
Table 3 Mode control bits D7 and D6
Table 4 Gain setting (see also Table 9)
Matrix equations
The relationship between output and input signals of the matrix is as follows:
Y = 0.3R + 0.59G + 0.11B
R−Y = 0.7R −0.59G −0.11B
B−Y=−0.3R −0.59G + 0.89B
ADDRESS SELECT PINS(1)(2) ADDRESS SELECT BITS
S2 (PIN 17) S1 (PIN 16) S0 (PIN 15) MA2 MA1 MA0
LLL∗
(3) ∗(3) ∗(3)
LLH001
LHL010
LHH011
HLL100
HLH101
HHL110
HHH111
MODE D7 D6 FUNCTION
0 0 0 Channel 2 selected, no matrix
1 0 1 Channel 2 selected, matrix active
2 1 0 Channel 1 selected
−1 1 not allowed
D5 D4 D3 A1 A2, A3, A4 B1, B3 B2
00011−1 0.45
0011111
0 1 0 not allowed −−
01111−1 0.45
10022−1 0.45
1012111
1102211
11121−1 0.45

1995 Mar 07 7
Philips Semiconductors Product specification
I2C-bus controlled YUV/RGB switch TDA8443A
Table 5 Priority/fast switching bit D2
Note
1. X = don't care.
D2 FAST SWITCHING
(PIN 3) MODE
0X
(1) 0 to 2, depending on
D7, D6
1 0.4 V 2
Table 6 Output state control bits
Note
1. X = don't care.
D1 D0 PIN 9 FUNCTION
0X
(1) X(1) OFF
10LOFF
10HON
11X
(1) ON
Power-on reset
If the circuit is switched on in the I2C-bus mode, all bits of D0 to D7 are set to zero.
Table 7 Non-I2C-bus mode (S2 = S1 = S0 = L)
CONTROL MODE SWITCHED BY
FS (PIN 3) GAIN SETTINGS B1, B3 B2
PIN 13 PIN 14 PIN 1 A1 A4, A3, A2
L L L 2 or 0 1 1 1 1
L L H 2 or 0 1 2 1 1
L H L 2 or 1 1 1 −1 0.45
L H H 2 or 0 1 1 −1 0.45
H L L 2 or 0 2 1 1 1
H L H 2 or 0 2 2 1 1
H H L 2 or 1 2 1 −1 0.45
H H H 2 or 0 2 1 −1 0.45
Table 8 Fast switching input (pin 3)
FS MODE SELECTED
≤0.4 V mode 2
1 to 3 V mode 0 or mode 1 as set by control
Table 9 ON input (pin 9)
ON FUNCTION
L OFF; no output signal; high impedance
OFF-state
H function is determined in Table 7

1995 Mar 07 8
Philips Semiconductors Product specification
I2C-bus controlled YUV/RGB switch TDA8443A
LIMITING VALUES
In accordance with the Absolute Maximum System (IEC 134).
CHARACTERISTICS
VP= 12 V; Tamb =25°C; unless otherwise specified.
SYMBOL PARAMETER MIN. MAX. UNIT
VPsupply voltage (pin 18) −14 V
VI(SDA) input voltage (pin 13) −0.3 14 V
VI(SCL) input voltage (pin 14) −0.3 14 V
Vninput voltage any other pin −0.3 VP+ 0.3 V
IO(max) maximum output current −20 mA
Tamb operating ambient temperature 0 +70 °C
Tstg IC storage temperature range −55 +125 °C
Tjmaximum junction temperature −+125 °C
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply
VPsupply voltage (pin 18) 10.8 12.0 13.2 V
IPsupply current −65 90 mA
RGB/YUV channels
Gabs absolute gain difference
(programmed value) −010%
G
rel relative gain difference between Y output and the
(R−Y) and (B−Y) channel
outputs
−010%
between any other two
channels −05%
I
Iinput current −0.5 1.0 µA
|Z19-22|output impedance (pin 19) −730Ω
|Z
20-22|output impedance (pin 20) −730Ω
|Z
21-22|output impedance (pin 21) −730Ω
B bandwidth −3 dB; mode 0 or 2 −25 −MHz
+3 dB; mode 0 or 2 −12 −MHz
±3 dB; mode 1 −10 −MHz
tdiff mutual time difference at output all inputs of one source
connected together −−25 ns
Vo(p-p) maximum output amplitude of YUV
signals (peak-to-peak value) gain ×1 2.1 −−V
gain ×2 4.2 −−V
α
ct crosstalk note 1; fi= 5 MHz; between
inputs of same source −−−30 dB
note 1; between same source −−−40 dB
αoff isolation (OFF state) fi= 10 MHz 50 −−dB

1995 Mar 07 9
Philips Semiconductors Product specification
I2C-bus controlled YUV/RGB switch TDA8443A
Gdiff(p-p) differential gain at nominal output
signals (peak-to-peak value) R−Y = 1.05 V (p-p) −−10 %
B−Y = 1.33 V (p-p) −−10 %
Y = 0.34 V (p-p) −−10 %
S/N signal-to-noise ratio nominal input; B = 5 MHz;
note 2 50 −−dB
SVRR supply voltage ripple rejection note 3 30 −−dB
VODC output levels during clamping −5.3 −V
Synchronization channels
Gdiff gain difference (programmed value) −−10 %
B bandwidth −3dB −50 −MHz
+3 dB; gain ×1−20 −MHz
±3 dB; gain ×2−13 −MHz
Vi(p-p) input amplitude of sync signal for
correct operation of clamp pulse
generator (peak-to-peak value)
0.2 −2.5 V
|Z23-22|output impedance (pin 23) −20 30 Ω
Vo(p-p) maximum undistorted output
amplitude (pin 23)
(peak-to-peak value)
2.5 −−V
V
ODC output level on top of sync pulse 1.5 1.9 2.4 V
I2C-bus inputs for SDA, SCL
VIH HIGH level input voltage 3 −VPV
VIL LOW level input voltage −0.3 −1.5 V
IIH HIGH level input current −−10 µA
IIL LOW level input current −−10 µA
I2C-bus output for SDA (open collector)
VOL LOW level output voltage IOL =3mA −−0.4 V
Address selection inputs for S0, S1, S2
VIH HIGH level input voltage 3 −VPV
VIL LOW level input voltage −0.3 −0.4 V
IIH HIGH level input current −010µA
I
IL LOW level input current −50 −10 0 µA
Fast switching input
VIH HIGH level input voltage 1 −3V
V
IL LOW level input voltage −0.3 −0.4 V
IIH HIGH level input current −0 500 µA
IIL LOW level input current −100 −−µA
t
sw switching time see Fig.5 −10 −ns
tdswitching delay see Fig.5 −20 −ns
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1995 Mar 07 10
Philips Semiconductors Product specification
I2C-bus controlled YUV/RGB switch TDA8443A
Notes
1. Crosstalkisdefined as the unwanted data transfer from an output, driven at nominal level, to other inputs andoutputs
on the IC and is expressed as a ratio in dBs.
2. Signal-to-noise ratio =
3. Supply voltage ripple rejection =
Select input
VIH HIGH level input voltage 3 −VPV
VIL LOW level input voltage −0.3 −0.4 V
IIH HIGH level input current −010µA
I
IL LOW level input current −50 −10 0 µA
ON input
VIH HIGH level input voltage 3 −VPV
VIL LOW level input voltage −0.3 −1.5 V
IIH HIGH level input current −−10 µA
IIL LOW level input current −−10 µA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
20log Vop p–()
V
no rms()
----------------------- B 5 MHz=()
20log VRR supply()
V
RR at the output()
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