
Contents
PHYTEC Messtechnik GmbH 2015 L-807e.A1 i
List of Figures..................................................................................................iii
List of Tables ................................................................................................... iv
Conventions, Abbreviations and Acronyms .............................................................. v
Preface ........................................................................................................ viii
1Introduction..............................................................................................1
1.1 Features of the phyCORE-MPC5676/57xx ........................................................... 1
1.1.1 Internal Features of the MPC5676R........................................................ 2
1.2 Memory configuration of the phyCORE-MPC5676/57xx......................................... 2
1.3 Other Board-Level Features............................................................................. 2
1.4 Block Diagram.............................................................................................. 3
1.5 phyCORE-MPC5676/57xx Component Placement ................................................. 4
1.6 Minimum Requirements to operate the phyCORE-MPC5676/57xx ............................ 6
2Pin Description...........................................................................................7
3Jumpers ................................................................................................. 24
4Power Requirements.................................................................................. 34
4.1 Voltage Supervisor and Reset .........................................................................35
5System Configuration and Booting................................................................ 36
6System Memory ........................................................................................ 37
6.1 External Standard Flash Memory (U100,U101)...................................................37
6.2 Synchronous Burst SRAM(U102,U103) .............................................................38
6.3 SPI EEPROM (U6) .........................................................................................39
6.3.1 EEPROM Write Protection Control (J30) .................................................39
6.4 SPI Flash Memory (U19) ) ..............................................................................39
7FPGA System Logic Device U18 ..................................................................... 40
7.1 Addressing the FPGA from MPC........................................................................40
7.2 Configuration of the FPGA..............................................................................40
7.3 FPGA connector X3 .......................................................................................40
8Serial Interfaces....................................................................................... 41
8.1 Universal Asynchronous Interface ...................................................................41
8.2 CAN Interface..............................................................................................42
8.3 SPI Interface...............................................................................................42
9LAN9221I Ethernet Controller...................................................................... 43
9.1.1 Ethernet Transformer.........................................................................43
9.1.2 Addressing the Ethernet Controller e ....................................................44
9.1.3 Software Reset of the Ethernet Controller ..............................................44
9.1.4 MAC Address ....................................................................................44
10 Real-Time Clock M41T93 (U7) ...................................................................... 45
11 JTAG/OnCE/Nexus Debufg Interface .............................................................. 46
12 Technical Specifications ............................................................................. 47
13 Hints for Integrating and Handling the phyCORE-MPC5676/57xx ......................... 50
13.1 Integrating the phyCORE-MPC5676/57xx..........................................................50
13.2 Handling the phyCORE-MPC5676/57xx .............................................................50