Phytec phyCORE-MPC5554 User manual

A product of a PHYTEC Technology Holding company
phyCORE-MPC5554
(with MPC5567 extension)
Hardware Manual
Edition December 2008
Downloaded from Arrow.com.

phyCORE-MPC5554
PHYTEC Messtechnik GmbH 2008 L-484e_2
In this manual are descriptions for copyrighted products that are not explicitly
indicated as such. The absence of the trademark () and copyright () symbols
does not imply that a product is not protected. Additionally, registered patents and
trademarks are similarly not expressly indicated in this manual.
The information in this document has been carefully checked and is believed to be
entirely reliable. However, PHYTEC Messtechnik GmbH assumes no
responsibility for any inaccuracies. PHYTEC Messtechnik GmbH neither gives
any guarantee nor accepts any liability whatsoever for consequential damages
resulting from the use of this manual or its associated product. PHYTEC
Messtechnik GmbH reserves the right to alter the information contained herein
without prior notification and accepts no responsibility for any damages which
might result.
Additionally, PHYTEC Messtechnik GmbH offers no guarantee nor accepts any
liability for damages arising from the improper usage or improper installation of
the hardware or software. PHYTEC Messtechnik GmbH further reserves the right
to alter the layout and/or design of the hardware without prior notification and
accepts no liability for doing so.
Copyright 2008 PHYTEC Messtechnik GmbH, D-55129 Mainz.
Rights - including those of translation, reprint, broadcast, photomechanical or
similar reproduction and storage or processing in computer systems, in whole or
in part - are reserved. No reproduction may occur without the express written
consent from PHYTEC Messtechnik GmbH.
EUROPE NORTH AMERICA
Address: PHYTEC Technologie Holding AG
Robert-Koch-Str. 39
D-55129 Mainz
GERMANY
PHYTEC America LLC
203 Parfitt Way SW, Suite G100
Bainbridge Island, WA 98110
USA
Ordering
Information: [phone]
[email protected] 1 [phone] [email protected]
Technical
Support: [phone]
[email protected] 1 [phone] [email protected]
Fax: [phone] [phone]
Web Site: http://www.phytec.de http://www.phytec.com
Edition: December 2008
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Contents
PHYTEC Messtechnik GmbH 2008 L-484e_2
Preface...........................................................................................................1
1Introduction.........................................................................................3
1.1 Block Diagram .............................................................................6
1.2 View of the phyCORE-MPC5554................................................7
1.3 Minimum Requirements to Operate the phyCORE-MPC5554 ...9
2Pin Description..................................................................................10
2.1 phyCORE equipped with MPC5554..........................................11
2.2 phyCORE equipped with MPC5567..........................................22
3Jumpers..............................................................................................24
4Power Requirements.........................................................................34
4.1 Voltage Supervision and Reset ..................................................35
5System Start-Up Configuration.......................................................36
6System Memory.................................................................................39
6.1 External Standard Flash Memory (U3, U4)...............................40
6.2 Synchronous Burst SRAM (U5, U6) .........................................42
6.3 Serial Memory (U15).................................................................43
7FPGA System Logic Device U21......................................................45
7.1 FPGA Firmware Development...................................................47
7.2 FPGA Basic Firmware...............................................................47
8Serial Interfaces.................................................................................49
8.1 RS-232 Interface ........................................................................49
8.2 CAN Interface ............................................................................50
8.3 JTAG/OnCE/Nexus Debug Interface.........................................51
9LAN91C111 Ethernet Controller....................................................53
9.1 Addressing the Ethernet Controller............................................53
9.2 Interrupt......................................................................................54
9.3 MAC Address.............................................................................55
9.4 Ethernet EEPROM U18 .............................................................55
9.5 10/100Base-T Interface..............................................................55
10 Real-Time Clock RTC-8564 (U16)..................................................56
11 phyCORE Development Board PCM-979......................................57
11.1 Concept of the phyCORE Development Board PCM-979 ........57
11.2 Development Board PCM-979 Overview..................................58
11.2.1 Connectors, Buttons, LED’s .........................................58
11.2.2 Jumpers on the phyCORE Development Board PCM-
979.................................................................................61
11.3 Functional Components on the phyCORE Development Board
PCM-979....................................................................................65
11.3.1 Power Supply at X5 ......................................................65
11.3.2 First Serial Interface at Socket P2A..............................67
11.3.3 Second Serial Interface at Socket P2B..........................67
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phyCORE-MPC5554
PHYTEC Messtechnik GmbH 2008 L-484e_2
11.3.4 First CAN Interface at Plug P1A.................................. 68
11.3.5 Second CAN Interface at Plug P1B..............................70
11.3.6 Programmable LED D6 ................................................72
11.3.7 Pin Assignment Summary of the phyCORE, the
Expansion Bus and the Patch Field............................... 72
11.3.7.1 Pin Assignment for the phy CORE MPC5554......74
11.3.7.2 Pin Assignment for the phy CORE MPC5557......82
11.3.8 JTAG/Once/Nexus Debug Interface.............................90
11.3.9 Reduced JTAG/OnCE/NEXUS Pin Header Connector
X2..................................................................................90
11.3.10 Full JTAG/OnCE/NEXUS Pin Header Connector X3.91
11.4 Technical Specification of the Development Board.................. 92
11.5 Release Notes.............................................................................94
12 Technical Specifications................................................................... 95
13 Hints for Handling the Module ....................................................... 98
14 Design Considerations - Check List................................................99
15 Revision History..............................................................................100
AAppendices.......................................................................................101
A.1 Release Notes........................................................................... 101
Index .........................................................................................................103
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Contents
PHYTEC Messtechnik GmbH 2008 L-484e_2
Index of Figures
Figure 1: Block Diagram phyCORE-MPC5554........................................6
Figure 2: Top View of the phyCORE-MPC5554 Revision 1239.3...........7
Figure 3: Bottom View of the phyCORE-MPC5554 Revision 1239.3.....8
Figure 4: Pinout of the phyCORE-MPC5554 (Bottom View)................10
Figure 5: Numbering of the Jumper Pads................................................24
Figure 6: Location of the Jumpers (Controller Side)and Default Settings
(phyCORE-MPC5554 Standard Version)................................25
Figure 7: Location of the Jumpers (Connector Side) and Default Settings
(phyCORE-MPC5554 Standard Version)................................26
Figure 8: Serial Memory I2C Slave Address...........................................44
Figure 9: 14-Pin JTAG/OnCE Connector (X3) and Corresponding Pins
on the phyCORE-Connector (X2)............................................52
Figure 10: Location of Connectors, Buttons and LED's on the phyCORE
Development Board PCM-979.................................................60
Figure 11: Numbering of Jumper Pads......................................................61
Figure 12: Location of the Jumpers (View of the Component Side) ........62
Figure 13: Default Jumper Settings of the phyCORE Development Board
PCM-979 with phyCORE-MPC5554 ......................................64
Figure 14: Connecting the Supply Voltage at X5......................................66
Figure 15: Pin Assignment of P2A as First RS-232 (Front View)............67
Figure 16: Pin Assignment of P2B as Second RS-232 (Front View)........67
Figure 17: Pin Assignment of the DB-9 Plug P1A (CAN Transceiver on
phyCORE- MPC5554, Front View).........................................68
Figure 18: Pin Assignment of the DB-9 Plug P1A (CAN Transceiver on
Development Board with Galvanic Separation) ......................69
Figure 19: Pin Assignment of the DB-9 Plug P1B (CAN Transceiver on
phyCORE-MPC5554, Front View)..........................................70
Figure 20: Pin Assignment of the DB-9 Plug P1B (CAN Transceiver on
Development Board)................................................................71
Figure 21: Pin Assignment Scheme of the Expansion Bus.......................73
Figure 22: Pin Assignment Scheme of the Patch Field.............................73
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phyCORE-MPC5554
PHYTEC Messtechnik GmbH 2008 L-484e_2
Figure 23 Physical Dimensions of the Development Board PCM-979 ... 92
Figure 24: Physical Dimensions (Top View)............................................ 95
Index of Tables
Table 1: Pinout of the phyCORE-Connector X2 for MPC5554............ 22
Table 2: Pinout of the phyCORE-Connector X2 for MPC5567............ 23
Table 3: Jumper Settings........................................................................ 33
Table 4: Serial Boot Mode Baud Rate................................................... 37
Table 5: Choice of Standard Flash Memory Devices and Manufacturers40
Table 6: Memory Options for the Synchronous Burst SRAM .............. 42
Table 7: Serial Memory Options for U15.............................................. 43
Table 8: Serial Memory I2C Address (Examples) ................................. 44
Table 8: Memory map FPGA register structure .................................... 48
Table 9: Development Board Jumper Overview.................................... 63
Table 10: JP8, JP9 Configuration of the Main Supply Voltages............ 65
Table 11: Jumper Configuration for CAN Plug P1A using the CAN
Transceiver on the phyCORE- MPC5554............................... 68
Table 12: Jumper Configuration for CAN Plug P1A Using Transceiver on
the Development Board with Galvanic Separation ................. 69
Table 13: Jumper Configuration for CAN Plug P1B Using the CAN
Transceiver on the phyCORE-MPC5554................................ 70
Table 14: Jumper Configuration for CAN Plug P1B using the CAN
Transceiver on the Development Board PCM-979 ................. 71
Table 15: JP7 Configuration of the Programmable LED D6.................. 72
Table 16: Signal Pin Assignment for the phyCORE-MPC5554 /
Development Board / Expansion Board .................................. 80
Table 17: Pin Assignment Power Supply for the phyCORE-MPC5554 /
Development Board / Expansion Board .................................. 81
Table 18: Signal Pin Assignment for the phyCORE-MPC5567 /
Development Board / Expansion Board .................................. 88
Table 19: Pin Assignment Power Supply for the phyCORE-MPC5567 /
Development Board / Expansion Board .................................. 89
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Contents
PHYTEC Messtechnik GmbH 2008 L-484e_2
Table 20: Pin Assignment of the Reduced JTAG/OnCE/Nexus Pin
Header X2 ................................................................................90
Table 21: Pin Assignment of the Full JTAG/OnCE/Nexus Pin Header X391
Table 22: Technical Data of the Development Board PCM-979.............93
Table 23: Technical Data .........................................................................96
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phyCORE-MPC5554
PHYTEC Messtechnik GmbH 2008 L-484e_2
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Preface
Preface
This phyCORE-MPC5554 Hardware Manual describes the board’s
design and functions. Precise specifications for the Freescale
MPC55xx microcontroller series can be found in the MPC55xx
microcontroller Data Sheet/User’s Manual. If software is included
please also refer to additional documentation for this software.
In this hardware manual and in the attached schematics, low active
signals are denoted by a “/” in front of the signal name (i.e.: /RD). A
“0” indicates a logic-zero or low-level signal, while a “1” represents a
logic-one or high-level signal. The MSB and LSB of the data and
address busses shown in the circuit diagram are based on the
conventions of Freescale. Accordingly, D31 and A31 represent the
LSB, while D0 and A0 represent the MSB. These conventions are also
valid for the parallel I/O signals.
Declaration regarding Electro Magnetic Conformity
of the PHYTEC phyCORE-MPC5554
PHYTEC Single Board Computers (henceforth products) are designed
for installation in electrical appliances or as dedicated Evaluation
Boards (i.e.: for use as a test and prototype platform for
hardware/software development) in laboratory environments.
Note:
PHYTEC products lacking protective enclosures are subject to
damage by ESD and, hence, may only be unpacked, handled or
operated in environments in which sufficient precautionary measures
have been taken in respect to ESD dangers. It is also necessary that
only appropriately trained personnel (such as electricians, technicians
and engineers) handle and/or operate these products. Moreover,
PHYTEC products should not be operated without protection circuitry
if connections to the product’s pin header rows are longer than 3 m.
PHYTEC Messtechnik GmbH 2008 L-484e_2 1
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phyCORE-MPC5554
2PHYTEC Messtechnik GmbH 2008 L-484e_2
PHYTEC products fulfill the norms of the European Union’s
Directive for Electro Magnetic Conformity only in accordance to the
descriptions and rules of usage indicated in this hardware manual
(particularly in respect to the pin header rows or connectors, power
connector and serial interface to a host-PC).
Implementation of PHYTEC products into target devices, as well as
user modifications and extensions of PHYTEC products, is subject to
renewed establishment of conformity to, and certification of, Electro
Magnetic Directives. Users should ensure conformance following any
modifications to the products as well as implementation of the
products into target systems.
The phyCORE-MPC5554 is one of a series of PHYTEC Single Board
Computers that can be populated with different controllers and, hence,
offers various functions and configurations. PHYTEC supports
common 8-, 16- and selected 32-bit controllers on two types of Single
Boards Computers:
(1) as the basis for Rapid Development Kits which serve as a
reference and evaluation platform
(2) as insert-ready, fully functional phyCORE OEM modules, which
can be embedded directly into the user’s target design.
PHYTEC’s microcontroller modules allow engineers to shorten
development horizons, reduce design costs and speed project concepts
from design to market.
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Introduction
PHYTEC Messtechnik GmbH 2008 L-484e_2 3
1Introduction
The phyCORE-MPC5554 belongs to PHYTEC’s phyCORE Single
Board Computer module family. The phyCORE SBCs represent the
continuous development of PHYTEC Single Board Computer
technology. Like its mini-, micro- and nanoMODUL predecessors, the
phyCORE boards integrate all core elements of a microcontroller
system on a sub-miniature board and are designed in a manner that
ensures their easy expansion and embedding in peripheral hardware
developments.
As independent research indicates that approximately 70 % of all EMI
(Electro Magnetic Interference) problems stem from insufficient
supply voltage grounding of electronic components in high frequency
environments the phyCORE board design features an increased pin
package. The increased pin package allows dedication of
approximately 20 % of all pin header connectors on the phyCORE
boards to Ground. This improves EMI and EMC characteristics and
makes it easier to design complex applications meeting EMI and EMC
guidelines using phyCORE boards even in high noise environments.
phyCORE boards achieve their small size through modern SMD
technology and multi-layer design. In accordance with the complexity
of the module, 0402-packaged SMD and laser-drilled Microvias
components are used on the boards, providing phyCORE users with
access to this cutting edge miniaturization technology for integration
into their own design.
The phyCORE-MPC5554 is a subminiature (84 x 57 mm) insert-ready
Single Board Computer populated with Freescale's PowerPC
MPC5554 microcontroller. Its universal design enables its insertion in
a wide range of embedded applications. All controller signals and
ports extend from the controller to high-density (0.635 mm) Molex pin
header connectors aligning two sides of the board, allowing it to be
plugged like a "big chip" into a target application.
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phyCORE-MPC5554
4PHYTEC Messtechnik GmbH 2008 L-484e_2
Precise specifications for the controller populating the board can be
found in the applicable controller User's Manual or Data Sheet. The
descriptions in this manual are based on the MPC5554 controller. No
description of compatible microcontroller derivative functions is
included, as such functions are not relevant for the basic functioning
of the phyCORE-MPC5554.
The phyCORE-MPC5554 offers the following features:
Single Board Computer in subminiature form factor (84 x 57 mm)
according to phyCORE specifications
all applicable controller and other logic signals extend to two high-
density 200-pin Molex connectors
processor: Freescale embedded PowerPC MPC5554 (up to 132
MHz clock)
Internal Features of the MPC5554:
32-bit PowerPC core, up to 132 MHz CPU speed
32 kByte Cache memory
SPE Signal Processing Extention (Single Precison FPU, MAC
Unit)
Memory Management Unit (MMU)
Direct Memory Access (DMA) controller
Interrupt latency <70ns @132MHz
64 kByte SRAM; 32 kByte capable of battery buffering
2 MByte Flash (read while write functionality)
two UART's (eSCI), LIN support
four SPI interfaces (DSPI)
three CAN 2.0B interfaces
two Time Processing Units (TPU) with 32 channels (pins) each
24 channels (pins) timer system (eMIOS) for PWM etc.
dual 12-bit ADC with 40 (65) channels (ext. MUX)
multi-purpose I/O signals
JTAG/OnCE/Nexus test/debug port
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Introduction
PHYTEC Messtechnik GmbH 2008 L-484e_2 5
Memory Configuration1:
SRAM: 2 MByte to 16 MByte Synchronous Flow-Through Burst-
RAM, 32-bit access, 0 wait states, 2-1-1-1 burst mode
Flash: 2 MByte to 8 MByte asynchronous standard Flash, 32-bit
access
I2C Memory: 4 kByte EEPROM (up to 32 kByte, alternatively I2C
FRAM, I2C SRAM)
Other Board-Level Features:
UART: two RS-232 transceivers for channel A and B (RxD/TxD),
also configurable as TTL
CAN: two 82C250-compatible CAN transceivers for channels A
and B; also configurable as TTL
Ethernet: 10/100 Mbit/s LAN91C111
FPGA: Lattice XP FPGA XP6/10/15 or XP20 device for
IP cores: e.g. I2C Master, 1-Wire-Master, UART, SPI etc.
programmable bus bridge (simple address-/data bus, PCI bus,
DDR-RAM etc.)
84 external GPIO with programmable characteristics (TTL,
CMOS, differential logic, LVDS etc.)
application specific control logic and clock generation (PLL)
embedded memory: single-/dual-port SRAM, FIFO etc.
in-system programmable over JTAG emulation
I2C Real-Time Clock with calendar and alarm function
JTAG/OnCE/Nexus test/debug port
industrial temperature range (-40…+85C)
Other CPU configurations:
The phyCORE-MPC5554 is also available equipped with Freescale’s
embedded PowerPC MPC5567.
1: Please contact PHYTEC for more information about additional product configurations.
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phyCORE-MPC5554
6PHYTEC Messtechnik GmbH 2008 L-484e_2
1.1 Block Diagram
LAN_TPO+, LAN_TPO-
LAN_TPI+, LAN_TPI-
LAN_LEDA, LAN_LEDB
FPGA_B1[25..0]
FPGA_B4[25..0]
FPGA_B3[19..0]
FPGA_B2[11..0]
+3.3V/900mA (bare)
+5V/60mA (bare)
JTAG/Nexus Debug Port
AN[39..0]
ETRIG[1,2], VRH
VBat
GPIO[207..203]
EMIOS[23..0]
/RTC_IRQ
CANHA, CANLA
CANHB, CANLB
CANTXB, CANRXB
CANTXA, CANRXA
2MB to 16MB
Sync. Burst-
SRAM
32-bit, 0 Wait
I
2
C-RTC
Clock
Calendar
Alarm
I
2
C-Memory
FRAM or
EEPROM or
SRAM
RS232 Transceiver
CAN Transceiver
CAN Transceiver
FlexCAN A
FlexCAN B
eSCI UART B
eSCI UART A
32 bit PowerPC
Core
32 kByte Cache
FPU
MMU
DMA
MPC5554
8 MHz Quarz p
h
y
C
O
R
E
-
C
o
n
n
e
c
t
o
r
40 channels, 12-bit
FlexCAN C CANTXC, CANRXC
2 to 8MB
FLASH-
EEPROM
32-bit
10/100Mbit/s
Ethernet
LAN91C111
32-bit
FPG
A
Bus-Bridge
User-Interface
User-Logic
FPG
A
84 free GPIO for
Bus-Bridge
PCI-Bus
LVDS-Ports
User Logic and I/O
etc.
DAC
12-Bit
1 channel
I2C Bus
12-Bit DAC, 1 channel
Power Suppl
y
+1V2
+1V5
VPD
RS232 Transceiver
TXDA_RS232, RXDA_RS232
TXDA, RXDA
TXDB_RS232, RXDB_RS232
TXDB, RXDB
SCL, SDA
I2C-Bus
DSPI
eMIOS
GPIO
eTPU A
eTPU B
eQADC 0 / 1
JTAG/Nexus
FM PLL
EBI
2 MB
FLASH SRAM
32 kByte
32 kByte
VPD
ETPUB[31..0], TCRCLKB
ETPUA[31..0], TCRCLKA
SCKA, SINA, SOUTA, PSCA[5..0]
SCKB, SINB, SOUTB, PSCB[5..0]
Figure 1: Block Diagram phyCORE-MPC5554
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Introduction
PHYTEC Messtechnik GmbH 2008 L-484e_2 7
1.2 View of the phyCORE-MPC5554
J39
U1
U6
J29
J11
J34
J40
J42
J20
U21
U14
U25
U5
U13
J38
J9
J2
J23
J6
J8
J7
U3
J1
J19
J10
U2
U4
J3
J12
J44
U16
J33
U15
J4
J43
J5
J35
J41
Figure 2: Top View of the phyCORE-MPC5554 Revision 1239.3
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phyCORE-MPC5554
U18
J31
J32
J37
J16
J25
J18
J27
J30
U19
J14
J17
U24
J36
J24
U23
U12
J21
J45
J22
U17
U22
J15
J13
U10
U11
U20
J28
J26
Figure 3: Bottom View of the phyCORE-MPC5554 Revision 1239.3
8PHYTEC Messtechnik GmbH 2008 L-484e_2
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Introduction
PHYTEC Messtechnik GmbH 2008 L-484e_2 9
1.3 Minimum Requirements to Operate the
phyCORE-MPC5554
Basic operation of the phyCORE-MPC5554 only requires a
+3V3 and a +5 V input voltage and the corresponding DGND
connections.
These supply pins are located at the phyCORE-connector X2:
+3V3 X2 1C, 2C, 1D, 2D, 4D, 5D
+5 V X2 4C, 5C
GND X2 3C, 3D, 7C, 9D, 12C, 14D
Caution:
We recommend connecting all available +3V3 and +5 V input pins to
the power supply system on a custom carrier board housing the
phyCORE-MPC5554 and at least the matching number of DGND pins
neighboring the +3V3 and +5 V pins.
In addition, proper implementation of the phyCORE module into a
target application also requires connecting all GND pins neighboring
signals that are being used in the application circuitry.
If no further external configuration is attached, the system will start
with reading the Reset Configuration Half Word (RCHW) from the
internal MPC5554 Flash memory. In order to force starting from the
external (on-board) Flash memory at U3/4, the /RSTCFG signal
located at X2C9 must be pulled to DGND for at least the duration of
the /RESET phase.
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phyCORE-MPC5554
2Pin Description
Please note that all module connections are not to exceed their
expressed maximum voltage or current. Maximum signal input values
are indicated in the corresponding controller manuals/data sheets. As
damage from improper connections varies according to use and
application, it is the user’s responsibility to take appropriate safety
measures to ensure that the module connections are protected from
overloading through connected peripherals.
As Figure 4 indicates, all controller signals extend to surface mount
technology (SMT) connectors (0.635 mm) lining two sides of the
module (referred to as phyCORE-connector; refer to section 12). This
allows the phyCORE-MPC5554 to be plugged into any target
application like a "big chip".
/ D C
X2
BA
X
2
11
100 100
11
100 100
Figure 4: Pinout of the phyCORE-MPC5554 (Bottom View)
Many of the controller port pins accessible at the edges of the board
have been assigned alternate functions that can be activated via soft-
ware.
10 PHYTEC Messtechnik GmbH 2008 L-484e_2
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Pin Descriotion
PHYTEC Messtechnik GmbH 2008 L-484e_2 11
2.1 phyCORE equipped with MPC5554
Table 1 provides an overview of the pinout of the phyCORE-
connector , as well as descriptions of possible alternative functions.
Please refer to the Freescale MPC5554 User Manual/Data Sheet for
details on the functions and features of controller signals and port
pins.
Pin Number Signal I/O Comments
Pin Row X2A
1A EXTCLK I Optional external clock input of the MPC5554
2A, 7A, 12A,
17A, 22A, 27A,
32A, 37A, 42A,
47A, 52A, 57A,
62A, 67A, 72A,
77A, 82A, 87A,
92A, 97A
DGND - Ground 0 V
3A IRQ4 I IRQ4 interrupt of the MPC5554
Alternative: GPIO208
4A IRQ5 I IRQ5 interrupt of the MPC5554
Alternative: GPIO209
5A FPGA_B1_IO0
6A FPGA_B1_IO1
8A FPGA_B1_IO6
9A FPGA_B1_IO7
10A FPGA_B1_IO8
11A FPGA_B1_IO9
13A FPGA_B1_IO14
14A FPGA_B1_IO15
15A FPGA_B1_IO16
16A FPGA_B1_IO17
18A FPGA_B1_IO22
19A FPGA_B1_IO23
20A FPGA_B1_IO24
21A FPGA_B1_IO25
I/O FPGA GPIO Top Side Bank 1
Functionality depends on the loaded FPGA
firmware.
The signals of a blank device are inputs with an
internal weak pull-up.
FPGA_VDDIO1 (Jumper J9)
23A FPGA_B4_IO4 I/O
24A FPGA_B4_IO5
25A FPGA_B4_IO6
26A FPGA_B4_IO7
28A FPGA_B4_IO12
29A FPGA_B4_IO13
30A FPGA_B4_IO14
31A FPGA_B4_IO15
33A FPGA_B4_IO20
34A FPGA_B4_IO21
35A FPGA_B4_IO22
36A FPGA_B4_IO23
FPGA GPIO Bottom Side Bank 4
Functionality depends on the loaded FPGA
firmware.
The signals of a blank device are inputs with an
internal weak pull-up.
FPGA_VDDIO4 (Jumper J10)
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phyCORE-MPC5554
12 PHYTEC Messtechnik GmbH 2008 L-484e_2
38A FPGA_B2_IO0 I/O
39A FPGA_B2_IO1
40A FPGA_B2_IO2
41A FPGA_B2_IO3
43A FPGA_B2_IO8
44A FPGA_B2_IO9
45A FPGA_B2_IO10
46A FPGA_B2_IO11
48A FPGA_B2_IO16
49A FPGA_B2_IO17
50A FPGA_B2_IO18
51A FPGA_B2_IO19
FPGA GPIO Right Side Bank 2
Functionality depends on the loaded FPGA
firmware.
The signals of a blank device are inputs with an
internal weak pull-up.
FPGA_VDDIO2 (Jumper J11)
53A FPGA_B3_IO4 I/O
54A FPGA_B3_IO5
55A FPGA_B3_IO6
56A FPGA_B3_IO7
FPGA GPIO Right Side Bank 3
Functionality depends on the loaded FPGA
firmware.
The signals of a blank device are inputs with an
internal weak pull-up.
58A FPGA_VDDIO_B2 I FPGA VCCIO2 of Right Side Bank 2
Alternative: FPGA_B2_IO20 (J28)
59A FPGA_VDDIO_B3 I FPGA VCCIO2 of Right Side Bank 3
Alternative: FPGA_B3_IO12 (J29)
60A ETPUB30 I/O eTPU B channel 30
Alternative: GPIO177
61A TCRCLKB I eTPU B TCR clock
Alternative: IRQ6, GPIO146
63A ETPUB28 I/O eTPU B channel 28
Alternative: GPIO175
64A ETPUB26 I/O eTPU B channel 26
Alternative: GPIO173
65A ETPUB24 I/O eTPU B channel 24
Alternative: GPIO171
66A ETPUB22 I/O eTPU B channel 22
Alternative: GPIO169
68A ETPUB20 I/O eTPU B channel 20
Alternative: GPIO167
69A ETPUB18 I/O eTPU B channel 18
Alternative: PCSA3, GPIO165
70A ETPUB16 I/O eTPU B channel 16
Alternative: PCSA1, GPIO163
71A ETPUB14 I/O eTPU B channel 14
Alternative: ETPUB30, GPIO161
73A ETPUB12 I/O eTPU B channel 12
Alternative: ETPUB28, GPIO159
74A ETPUB10 I/O eTPU B channel 10
Alternative: ETPUB26, GPIO157
75A ETPUB8 I/O eTPU B channel 8
Alternative: ETPUB24, GPIO155
76A ETPUB6 I/O eTPU B channel 6
Alternative: ETPUB22, GPIO153
78A ETPUB4 I/O eTPU B channel 4
Alternative: ETPUB20, GPIO151
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