Phytec phyCORE-AM62Ax User manual

A product of a PHYTEC Technology Holding company
phyCORE®-AM62Ax Direct
Solder Connection (DSC)
Hardware Manual
Document No.:
L-1061e.A0
SOM Prod. No.:
PCL-075
SOM PCB. No.:
1598.0
CB Prod. No.:
PBA-C-24
CB PCB. No.:
1576.3
Edition:
Oct 2023

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1Table of Contents
1Table of Contents.................................................................................................................................. 2
1.1 List of Figures................................................................................................................................. 6
1.2 List of Tables.................................................................................................................................. 7
2SOM Features....................................................................................................................................... 9
3Conventions, Abbreviations and Acronyms........................................................................................... 10
3.1 Conventions................................................................................................................................. 10
3.2 Abbreviations and Acronyms......................................................................................................... 10
3.3 Types of Signals........................................................................................................................... 11
4Introduction......................................................................................................................................... 13
4.1 Block Diagram.............................................................................................................................. 14
4.2 Physical Dimensions..................................................................................................................... 15
4.3 Component Placement Diagram.................................................................................................... 17
4.4 Technical and Electrical Specifications.......................................................................................... 19
4.5 Minimum Requirements for Operation ........................................................................................... 19
4.6 Solder Jumpers............................................................................................................................ 20
4.7 Pin Descriptions ........................................................................................................................... 23
4.8 Pinout Table................................................................................................................................. 28
4.9 Thermal Management................................................................................................................... 33
4.10 Layout Guidelines......................................................................................................................... 34
4.10.1 High-Speed Differential Signal Routing Guidelines.................................................................. 34
4.10.2 General Signal Routing Guidelines......................................................................................... 35
5Power................................................................................................................................................. 35
5.1 Primary System Power (VIN)......................................................................................................... 36
5.1.1 Primary Power Reference Circuit............................................................................................ 36
5.2 Backup Power (VBAT).................................................................................................................. 38
5.3 Reset........................................................................................................................................... 38
5.4 Power Sequencing ....................................................................................................................... 40

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5.5 Safe Shutdown and Sudden Power Loss....................................................................................... 41
6System Memory.................................................................................................................................. 41
6.1 SOM Memory............................................................................................................................... 42
6.1.1 LPDDR4 RAM....................................................................................................................... 42
6.1.2 EEPROM .............................................................................................................................. 42
6.1.3 eMMC Flash.......................................................................................................................... 42
6.1.4 OSPI..................................................................................................................................... 42
6.2 External Memory Bus ................................................................................................................... 43
6.2.1 GPMC................................................................................................................................... 43
6.2.2 SD/MMC/SDIO...................................................................................................................... 45
6.3 System Boot Configuration............................................................................................................ 50
7Serial Interfaces.................................................................................................................................. 53
7.1 CAN............................................................................................................................................. 53
7.1.1 CAN Pinout ........................................................................................................................... 53
7.1.2 CAN Reference Circuit........................................................................................................... 53
7.2 Ethernet....................................................................................................................................... 54
7.2.1 Ethernet Pinout...................................................................................................................... 54
7.2.2 Ethernet Design In Guide....................................................................................................... 55
7.2.3 Ethernet Reference Circuits ................................................................................................... 57
7.3 I2C............................................................................................................................................... 60
7.3.1 I2C Pinout.............................................................................................................................. 61
7.4 SPI .............................................................................................................................................. 61
7.4.1 SPI Pinout............................................................................................................................. 61
7.5 UART........................................................................................................................................... 62
7.5.1 UART Pinout ......................................................................................................................... 62
7.6 USB............................................................................................................................................. 65
7.6.1 USB Pinout............................................................................................................................ 65
7.6.2 USB Design In Considerations............................................................................................... 65
7.6.3 USB Reference Circuits......................................................................................................... 65

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7.7 MCASP........................................................................................................................................ 67
7.7.1 MCASP Pinout ...................................................................................................................... 67
8Display and Camera Interfaces............................................................................................................ 69
8.1 VOUT .......................................................................................................................................... 69
8.1.1 VOUT Pinout......................................................................................................................... 70
8.2 CSI.............................................................................................................................................. 71
8.2.1 CSI Pinout............................................................................................................................. 71
8.2.2 CSI Design In Considerations................................................................................................. 71
8.2.3 CSI Reference Circuits........................................................................................................... 72
9Control Interfaces................................................................................................................................ 74
9.1 Enhanced Capture........................................................................................................................ 74
9.1.1 ECAP Pinout ......................................................................................................................... 75
9.2 Enhanced Pulse-Width Modulation................................................................................................ 75
9.2.1 EPWM Pinout........................................................................................................................ 75
9.3 Enhanced Quadrature Encoder Pulse ........................................................................................... 76
9.3.1 EQEP Pinout......................................................................................................................... 76
10 Peripheral Interfaces ........................................................................................................................... 76
10.1 CPTS........................................................................................................................................... 77
10.1.1 CPTS Pinout ......................................................................................................................... 77
10.2 GPIO ........................................................................................................................................... 77
10.2.1 GPIO Pinout.......................................................................................................................... 78
10.3 TIMER......................................................................................................................................... 81
10.3.1 Timer Pinout.......................................................................................................................... 81
11 Debug Interfaces................................................................................................................................ 82
11.1 JTAG........................................................................................................................................... 82
11.1.1 JTAG Pinout.......................................................................................................................... 82
11.1.2 JTAG Reference Circuit......................................................................................................... 83
11.2 TRACE (TRC).............................................................................................................................. 84
11.2.1 TRC Pinout............................................................................................................................ 84

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11.3 UART0......................................................................................................................................... 85
11.3.1 UART0 Pinout ....................................................................................................................... 85
11.3.2 UART0 Reference Circuits..................................................................................................... 85
12 System Interfaces................................................................................................................................ 89
12.1 MAIN Pinout................................................................................................................................. 89
12.2 MCU Pinout.................................................................................................................................. 89
12.3 WKUP Pinout............................................................................................................................... 90
12.4 RTC............................................................................................................................................. 90
12.4.1 RTC Pinout............................................................................................................................ 90
12.5 Heartbeat LEDs............................................................................................................................ 90
13 Integrating and Updating the phyCORE-AM62Ax DSC.......................................................................... 91
13.1 Integration.................................................................................................................................... 91
13.2 Modification.................................................................................................................................. 91
13.3 In-Field Updates........................................................................................................................... 91
13.4 Product Change Management....................................................................................................... 92
14 Additional Information.......................................................................................................................... 93
15 Revision History.................................................................................................................................. 95

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1.1 List of Figures
Figure 1. phyCORE-AM62Ax DSC SOM.................................................................................................. 13
Figure 2. phyCORE-AM62Ax DSC Block Diagram .................................................................................. 14
Figure 3. phyCORE-AM62Ax DSC Dimensions Top View....................................................................... 15
Figure 4. phyCORE-AM62Ax DSC Dimensions End View....................................................................... 16
Figure 5. phyCORE-AM62Ax DSC Component Placement (processor side).......................................... 17
Figure 6. phyCORE-AM62Ax DSC Component Placement (connector side)........................................... 18
Figure 7. Position Solder Jumper Pad Numbering Scheme .................................................................... 20
Figure 8. Jumper Locations (Connector side)......................................................................................... 22
Figure 9. Landing Pattern Pinning Detail................................................................................................ 23
Figure 10. Landing Pattern (SOM Edge Dimensions) ............................................................................. 24
Figure 11. Landing Pattern Detail (SOM Corner Dimensions) ................................................................ 25
Figure 12. Landing Pattern Dimensions (Pin Alignment) ....................................................................... 26
Figure 13. Pinout example using X_VOUT0_VSYNC in our schematic................................................... 27
Figure 14. Fan design reference circuit................................................................................................... 34
Figure 15. Primary Power VIN(VCC_5V0_MAIN) reference circuit........................................................... 37
Figure 16. SOM current reader reference circuit ..................................................................................... 37
Figure 17. Phoenix connector power input with overload protection reference circuit.......................... 38
Figure 18. Reset signals pullups, pulldowns, and capacitors populated on the SOM ............................ 39
Figure 19. Carrier board power reference circuit..................................................................................... 41
Figure 20. OSPI0 CSN signal use............................................................................................................. 43
Figure 21. MMC1 SD-card Reader Reference Schematic......................................................................... 47
Figure 22. MMC1 Load Switch Reference Schematic .............................................................................. 48
Figure 23. M.2 WIFI MMC2 Connector Reference Schematic................................................................... 48
Figure 24. M.2 WIFI MMC2 Level Translators Reference Schematic ....................................................... 49
Figure 25. BOOTMODE pullups/pulldowns.............................................................................................. 50
Figure 26. Reference Schematic for BOOTMODE configuration............................................................. 52
Figure 27. MCAN0 Reference Schematic................................................................................................. 53
Figure 28. RJ45 Reference Schematic..................................................................................................... 58
Figure 29. RGMII PHY RJ45 Reference Schematic .................................................................................. 58
Figure 30. RGMII PHY Strapping Resistors Reference Schematic .......................................................... 59
Figure 31. RGMII PHY Reference Schematic ........................................................................................... 59
Figure 32. USB-HUB Reference Schematic.............................................................................................. 66
Figure 33. USB 2.0 Connector Reference Schematic .............................................................................. 66
Figure 34. USB-C Connector Reference Schematic................................................................................. 67
Figure 35. CSI Power Toggle Reference Schematic ................................................................................ 73

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Figure 36. CSI Connector Reference Schematic...................................................................................... 74
Figure 37. JTAG Reference Schematic.................................................................................................... 83
Figure 38. UART0 to USB Bridge Reference Schematic.......................................................................... 86
Figure 39. UART0 to USB Buffers and Regulator Reference Schematic................................................. 87
Figure 40. Simple UART0 Reference Schematic...................................................................................... 88
1.2 List of Tables
Table 1 Abbreviations and Acronyms used in this Manual ..................................................................... 10
Table 2 Signal Types Used in this Manual............................................................................................... 12
Table 3 Technical Specifications............................................................................................................. 19
Table 4 Recommended Operating Conditions for the Input and Output Power Domains....................... 19
Table 5 Solder Jumper Settings............................................................................................................... 20
Table 6 Voltage Domain Configurations.................................................................................................. 21
Table 7 phyCORE-AM62Ax DSC Connector X1, Pins 1-47 Pinout........................................................... 28
Table 8 phyCORE-AM62Ax DSC Connector X1, Pins 48-94 Pinout......................................................... 29
Table 9 phyCORE-AM62Ax DSC Connector X1, Pins 95-141 Pinout....................................................... 30
Table 10 phyCORE-AM62Ax DSC Connector X1, Pins 142-188 Pinout ................................................... 31
Table 11 phyCORE-AM62Ax DSC Connector X1, Pins 189-270 Pinout ................................................... 32
Table 12 Thermal Management Parts....................................................................................................... 33
Table 13 External Supply Voltages.......................................................................................................... 35
Table 14 Reset Pin Description................................................................................................................ 39
Table 15 GPMC Signal Connections at the SOC footprint....................................................................... 44
Table 16 MMC Connections at the SOC footprint.................................................................................... 46
Table 17 phyCORE-AM62Ax DSC MMC1 Layout Characteristics............................................................ 46
Table 18 BOOTMODE Description ........................................................................................................... 51
Table 19 MCAN Connections at the SOC footprint.................................................................................. 53
Table 20 Ethernet PHY Default Strapping Configuration......................................................................... 54
Table 21 Ethernet Connections at the SOC footprint .............................................................................. 54
Table 22 phyCORE-AM62Ax DSC CPSW_ETH0 Layout Characteristics................................................. 56
Table 23 phyCORE-AM62Ax DSC RGMII Timing Requirements.............................................................. 56
Table 24 phyCORE-AM62Ax DSC RGMII2 Trace Length Characteristics................................................ 57
Table 25 I2C Connections at the SOC footprint........................................................................................ 61
Table 26 SPI Connections at the SOC footprint....................................................................................... 61
Table 27 UART Connections at the SOC footprint................................................................................... 62
Table 28 USB Connections at the SOC footprint..................................................................................... 65
Table 29 phyCORE-AM62Ax DSC USB0 Layout Characteristics............................................................. 65

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Table 30 MCASP Connections at the SOC footprint................................................................................ 67
Table 31 VOUT Connections at the SOC footprint................................................................................... 70
Table 32 CSI Connections at the SOC footprint....................................................................................... 71
Table 33 phyCORE-AM62Ax DSC CSI0 Layout Characteristics .............................................................. 72
Table 34 ECAP Connections at the SOC footprint................................................................................... 75
Table 35 EPWM Connections at the SOC footprint.................................................................................. 75
Table 36 EQEP Connections at the SOC footprint................................................................................... 76
Table 37 CPTS Connections at the SOC footprint................................................................................... 77
Table 38 Total Available GPIO.................................................................................................................. 77
Table 39 GPIO0 Accessibility at SOC footprint........................................................................................ 78
Table 40 GPIO1 Accessibility at SOC footprint........................................................................................ 80
Table 41 MCU_GPIO0 Accessibility at SOC footprint.............................................................................. 81
Table 42 Timer Signals............................................................................................................................. 81
Table 43 JTAG Connections at the SOC footprint................................................................................... 82
Table 44 TRC Connections at the SOC footprint..................................................................................... 84
Table 45 UART0 Connections at the SOC footprint................................................................................. 85
Table 46 MAIN Connections at the SOC footprint.................................................................................... 89
Table 47 MCU Connections at the SOC footprint .................................................................................... 89
Table 48 WKUP Connections at the SOC footprint.................................................................................. 90
Table 49 RTC Connections at the SOC footprint ..................................................................................... 90
Table 50 Document Revision History....................................................................................................... 95

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2SOM Features
The phyCORE-AM62Ax Direct Solder Connection (DSC) offers the following features:
•Insert-ready, small (40.8 mm x 40.8 mm) System on Module (SOM) subassembly in low EMI design, achieved
through advanced SMD technology
•Populated with the Texas Instruments AM62Ax System on Chip (SoC) (18 x 18 mm, 0.8 mm pitch BGA)
•Single supply voltage of 5V with on-board power management IC
•Up to 4GB LPDDR4 RAM
•Up to 128GB on-board eMMC
•1x Octal/Quad SPI Flash Subsystem connected to a 64MB NOR Flash
•1x Gigabit Ethernet PHY (signals brought out to connector as differential pairs)
•1x 4KB I2C EEPROM
•1x On-board RTC
•1x 270 pin 0.8mm pitch castellated edge DSC footprint that expose the following interfaces:
•2x MMC/SDIO modules
•2x USB 2.0 Ports
•1x 10/100/1000 Mbit Ethernet (signals brought out as RGMII)
•3x MCAN with CAN-FD support
•9x UART
•6x I2C
•1x JTAG debug port
•4x SPI
•3.3V/1.8V GPIOs
•4x EPWM (Enhanced Pulse Width Modulator) modules
•3x ECAP (Enhanced Capture) modules
•3x EQEP (Enhanced Quadrature Encoder Pulse) modules
•1x GPMC (General Purpose Memory Controller) module
•1x TRC (Trace) module
•1x CPTS (Common Platform Time Sync) module
•12x Timer modules
•1x CSI (Camera Serial Interface) module
•3x McASP (Multichannel Audio Serial ports) modules
•1x 24-bit RGB parallel display module
NOTE:
Some of the features listed are not available simultaneously due to the multiplexing options of the various
processor pins. Refer to the sections 5-12 of this manual for further information on available multiplexing
options and the pinout of signals.

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3Conventions, Abbreviations and Acronyms
This hardware manual describes the PCL-075 System on Module, henceforth referred to as phyCORE-AM62Ax DSC. The
manual specifies the phyCORE-AM62Ax DSC's design and function. Precise specifications for the Texas Instruments
AM62Ax SoC can be found in the AM62Ax Technical Reference Manual.
We refrain from providing detailed part specific information within this manual which can be subject to changes. This is
due to the continuous maintenance of our products. Please read 13.4 Product Change Management for more information.
The BSP delivered with the phyCORE-AM62Ax DSC includes drivers and/or software for controlling all components such
as interfaces, memory, etc. Therefore, programming close to the hardware (at the register level) is not necessary in most
cases. For this reason, this manual contains no detailed description of the processor's registers, or information relevant
for software development. Please refer to the AM62Ax Technical Reference Manual if such information is needed.
3.1 Conventions
The conventions used in this manual are as follows:
•Signals that are preceded by an "n" or end in z (e.g.: nRD or RDz), are designated as active low signals. That is,
their active state is when they are driven low, or are driving low.
•A "0" indicates a logic zero or low-level signal, while a "1" represents a logic one or high-level signal.
•The hex-numbers given for addresses of I2C devices always represent the 7 most-significant bits (MSB) of the
address byte. The correct value of the least-significant bit (LSB) will depend on the desired command (read (1) or
write (0)) and must be added to get the complete address byte. E.g. given the address in this manual 0x41 => the
complete address byte = 0x83 reads from the device and 0x82 to writes to the device
•Text in blue italics indicate a cross-reference to an internal section of this Document. Click these links to quickly
jump to the applicable part, chapter, table, or figure.
•Text in underlined in blue indicate an external link. Click these links to quickly jump to the applicable URL.
•References made to the DSC footprint always refer to the direct solder connector on the underside of the
phyCORE-AM62Ax DSC System on Module.
3.2 Abbreviations and Acronyms
Many acronyms and abbreviations are used throughout this manual. Use the table below to navigate unfamiliar terms
used in this document.
Table 1 Abbreviations and Acronyms used in this Manual
Abbreviation
Definition
BSP
Board Support Package (Software delivered with the Development Kit including an operating system
(Linux) preinstalled on the module and Development Tools)

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CB
Carrier Board; used in reference to the phyCORE Development Kit Carrier Board
DDR
Double data rate
DRAM
Dynamic random access memory
DSC
Direct Solder Connection
EMC
Electromagnetic Compatibility
EMI
Electromagnetic Interference
GPIO
General-Purpose Input/Output
GPT
General-Purpose Timer
J
Solder Jumper: these types of jumpers require solder equipment to remove and place
JP
Solderless Jumper: these types of jumpers can be removed and placed by hand with no special tools
JTAG
Joint Test Action Group (a serial bus protocol usually used for test purposes)
LCD
Liquid Crystal Display
PCB
Printed circuit board
PCI
Peripheral Component Interconnect
PCIe
PCI express
PCM/PCL
phyCORE Module (connectorized / direct solder)
PCN
Product Change Notification
PDI
PHYTEC Display Interface; defined to connect PHYTEC display adapter boards, or custom adapters
PEB
PHYTEC Expansion Board
PMIC
Power management IC
POR
Power-on reset
PRU
Programmable Realtime Unit
PWM
Pulse-width Modulation
RTC
Real-time clock
SOC
System on Chip
SD
Secure Digital
SMT
Surface mount technology
SOM
System on Module; used in reference to the BOARD DESIGNATOR/ SOM BOARD NAME module
SPI
Serial Peripheral Interface
Sx
User button Sx(e.g. S1, S2, etc.) used in reference to the available user buttons, or DIP-Switches on
the Carrier Board
UART
Universal Asynchronous Receiver/Transmitter
USB
Universal Serial Bus
3.3 Types of Signals
Different types of signals are brought out at the DSC footprint. Table 2 below lists the abbreviations used to specify the
type of a signal.

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Table 2 Signal Types Used in this Manual
Signal Type
Description
Abbreviation
Analog
Analog
A
Power
Supply voltage input
PWR_I
Input
Digital input
I
Output
Digital output
O
IO
Bidirectional input/output
I/O
OD-Bidir PU
Open drain input/output with pull up
OD-BI
OD-Output
Open drain output without pull-up, requires an external pull-up
OD
5V Input PD
5 V tolerant input with pull down
5V_PD
USB IO
Differential line pairs 90 Ω USB level bidirectional input/output
USB_I/O
ETHERNET IO
Differential line pairs 100 Ω Ethernet level bidirectional input/output
ETH_I/O
MIPI CSI Input
Differential line pairs 100 Ω MIPI CSI level input
CSI_I

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4Introduction
Figure 1. phyCORE-AM62Ax DSC SOM
The phyCORE-AM62Ax DSC belongs to PHYTEC’s phyCORE System on Module family. The phyCORE boards integrate all
core elements of a SoC system on a single module and are designed in a manner that ensures their easy expansion and
embedding in peripheral hardware developments.
The phyCORE-AM62Ax DSC is a small (40.8 mm x 40.8 mm) insert-ready System on Module populated with the Texas
Instrument’s AM62Ax SoC. Its universal design enables its insertion in a wide range of embedded applications. Most of
the SoC signals and ports extend from the SoC to the DSC footprint on the bottom of the board, allowing it to be soldered
down on a target application.
Implementing a phyCORE-AM62Ax DSC SOM as the core of your embedded design allows for increased focus on hardware
peripherals and firmware without expending resources to re-invent microprocessor circuitry or other commonly used
circuitry that has already been implemented on the phyCORE-AM62Ax DSC including a LPDDR4 RAM, an eMMC, an OSPI
Flash, a power distribution network, an Ethernet PHY, an RTC, and an EEPROM. Production-ready board support packages
(BSPs), design services for our hardware, and lifecycle maintenance of our parts will further reduce development time,
risk, and allows for increased focus on product expertise. Take advantage of PHYTEC products to shorten time-to-market,
reduce development costs, and avoid substantial design issues and risks. With this new innovative full system solution,
new ideas can be brought to market in the most timely and cost-efficient manner.
Precise specifications for the processor populating the board can be found in the applicable processor reference manual
or datasheet. The descriptions in this manual are based on the Texas Instrument’s AM62Ax. No descriptions of compatible
SoC derivative functions are included; these are not relevant for the basic functioning of the phyCORE-AM62Ax DSC.

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4.1 Block Diagram
Figure 2. phyCORE-AM62Ax DSC Block Diagram

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4.2 Physical Dimensions
Figure 3. phyCORE-AM62Ax DSC Dimensions Top View

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Figure 4. phyCORE-AM62Ax DSC Dimensions End View

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4.3 Component Placement Diagram
Figure 5. phyCORE-AM62Ax DSC Component Placement (processor side)

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Figure 6. phyCORE-AM62Ax DSC Component Placement (connector side)
A searchable pdf of the phyCORE-AM62Ax DSC component placement can be found here: here.

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4.4 Technical and Electrical Specifications
Table 3 Technical Specifications
Specification
Dimensions
40.8 mm x 40.8 mm x 4.18 mm
Mass
~11.3g
Storage Temperature
-40C to +85C
Operating Temperature
-40C to +85C
Typical Idling Power Consumption1
2.2W1
1Calculated from idle Ivcc in Table 4
Table 4 Recommended Operating Conditions for the Input and Output Power Domains
Symbol
Description
Conditions
Min
Typical
Max
Unit
VIN
5V SOM input voltage
4.5
5
5.5
VDC
VBAT
Backup battery for RTC
1.2
3
5.5
VDC
IVIN
5V SOM operating current
Idle in Linux with external interfaces
down/disconnected (except for Serial RS-232 and SD
card)
-
433
-
mA
Measured while device was under load1
-
693
-
mA
Measured with VDD_3V3_OUT supplying 2A of current
alongside the test suite in the row above
-
2013
-
mA
IVBAT
RTC operating current
-
40
-
nA
1The load included the following interfaces/commands: the “memtester 500M” command was run, ETH0 was plugged in with iperf3 running, and two instances of the
following command were run (yes > /dev/null &), The Yes Command
4.5 Minimum Requirements for Operation
PHYTEC recommends the following minimum requirements for basic operation of the phyCORE-AM62Ax DSC SOM:
•Connect all available 5V input pins to a power supply on a custom carrier board that provides at least 2500 mA
(1250 mA if VDD_3V3_OUT is not used in your design).
•Connect all ground pins to ground.
•Implement a power sequencing circuit to avoid driving external power to the I/O pins of the PHYCORE-AM62Ax
DSC SOM before the module is fully powered up. More details on this can be found in section 5.4 Power
Sequencing.
•Implement at least one of the supported boot devices to support loading and executing application software.
Refer to section 6.3 System Boot Configuration for more details regarding supported boot modes. The phyCORE-
AM62Ax DSC SOM provides an on-board eMMC, but it is recommended to support another boot source for
development and debugging. PHYTEC suggests SD boot for which an example circuit can be seen in section 6.2.2.3
MMC Reference Circuit

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•Strap the boot signals to the desired levels at Power on Reset (POR) to configure the required boot mode for your
application (i.e. using a DIP switch). This is required on the carrier board to override the default boot mode set on
the SOM. Refer to section 6.3 System Boot Configuration for more information.
•Implement a serial debug port (such as via UART0) to interface with the module for development. An example can
be found in section 11.3 UART0.
•Implement a reset button for easy reset of the module.
4.6 Solder Jumpers
For configuration purposes the phyCORE-AM62Ax DSC SOM has several solder jumpers. Figure 7 illustrates the numbering
of the solder jumper pads, while Figure 8 indicates the location and the default configuration of the solder jumpers on the
board. Table 5 provides a functional summary of the solder jumpers whichcan be changed to adapt the phyCORE-AM62Ax
DSC SOM to specific design needs. It shows their default positions, possible alternative positions, type, and functions. The
jumpers are a 0201 package size with a 1/16Wor higher power rating.
Figure 7. Position Solder Jumper Pad Numbering Scheme
Table 5 Solder Jumper Settings
Jumper
Position
Description
Type
J1
1+2
Sets the VDDSHV0 domain to 3.3V
0 Ω
2+3
Sets the VDDSHV0 domain to 1.8V
J3
1+2
Sets the VDDSHV2 domain to 3.3V
0 Ω
2+3
Sets the VDDSHV2 domain to 1.8V
J4
1+2
Sets the VDDSHV3 domain to 3.3V
0 Ω
2+3
Sets the VDDSHV3 domain to 1.8V
J12
1+2
Sets the VDDSHV6 domain to 3.3V
0 Ω
2+3
Sets the VDDSHV6 domain to 1.8V
J13
1+2
Sets the VDDSHV_MCU domain to 3.3V
0 Ω
2+3
Sets the VDDSHV_MCU domain to 1.8V
J14
1+2
Sets the VDDSHV_CANUART domain to 3.3V
0 Ω
2+3
Sets the VDDSHV_CANUART domain to 1.8V
2+4
Connects the VDDSHV_CANUART domain to PIO_VDDSHV (a 3.3V domain)
J19
1+2
Connect GPMC0_CLK to X_GPMC0_CLK
0 Ω
2+3
Connect GPMC0_CLK to SD_VSEL